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Revision B User Manual
for the VME-SIO4: Board Revision: A
General Standards Corporation
8302A Whitesburg Drive Huntsville, AL 3580, Phone: [phone]
1
VME-SIO4A
User Manual
Manual Revision: B
General Standards Corporation
8302A Whitesburg Drive
Huntsville, AL 35802
Phone: [phone]
Fax: [phone]
URL :http://www.generalstandards.com
E-mail: [email protected]

Revision B User Manual
for the VME-SIO4: Board Revision: A
General Standards Corporation
8302A Whitesburg Drive Huntsville, AL 3580, Phone: [phone]
2
PREFACE
Copyright © 1997 General Standards Corp.
Additional copies of this manual or other General Standards Corporation literature may be obtained from:
General Standards Corporation
8302A Whitesburg Drive
Huntsville, Alabama 35802
Telephone: [phone]
Fax: [phone]
Company URL: www.generalstandards.com
The information in this document is subject to change without notice.
General Standards Corporation makes no warranty of any kind with regard to this material, including, but not
limited to, the implied warranties of merchantability and fitness for a particular purpose. Although extensive editing
and reviews are performed before release to ECO control, General Standards Corporation assumes no
responsibility for any errors that may exist in this document. No commitment is made to update or keep current the
information contained in this document.
General Standards Corporation does not assume any liability arising out of the application or use of any product
or circuit described herein, nor is any license conveyed under any patent right of any rights of others.
General Standards Corporation assumes no responsibility resulting from omissions or errors in this manual, or
from the use of information contained herein.
General Standards Corporation reserves the right to make any changes, without notice, to this product to improve
reliability, performance, function, or design.
All rights reserved
No parts of this document may be copied or reproduced in any form or by any means without prior written consent of
General Standards Corporation.
This user’s manual provides information on the specifications, theory of operation, register level programming, and
installation of the VME-SIO4 board.
Information required for customized hardware/software development.
This manual assumes that the user is familiar with the VMEbus interface specification. In an effort to avoid
redundancy, this manual relies on data books, other manuals, and specifications as indicated in the related
publication section.

Revision B User Manual
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8302A Whitesburg Drive Huntsville, AL 3580, Phone: [phone]
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Related Publications
The following manuals and specifications provide the necessary information for in-depth understanding of the
VMEbus and specialized parts used on this board.
EIA Standard for the RS-422-A Interface (EIA order number EIA-RS-422A)
VMEbus Specification Manual (also known as IEC 821 BUS and IEEE P10114/D1/2), for information submit
request to:
VITA10229 North Scottsdale Road, Suite B
Scottsdale, AZ 85253
Telephone: [phone]
Zilog’s USC Universal Serial Controller (part number: Z16C30) User’s Manual and Databook, for information
submit request to: Zilog, Inc.
210 East Hacienda Ave.
Campbell, CA 95008-6600
Telephone: [phone]

Revision B User Manual
for the VME-SIO4: Board Revision: A
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8302A Whitesburg Drive Huntsville, AL 3580, Phone: [phone]
4
VME-SIO4 Documentation History
1) The Vme-SIO4 documentation was updated March 1997.
2) The manual was reformatted, for conformity of text, and the table of contents was corrected.
3) The jumper field drawings in Chapter 4 were redrawn and double checked.
4) April 27, 1997: Chapter 3, page 3, Section 3.1.2.1, D6 & D7 bit descriptions were corrected, instead of: 0 will
enable Rx…, it was corrected to be a 1 will enable Rx.., and instead of 1 will disable Rx.., it was corrected to be
a 0 will disable Rx…
5) April 27, 1997: Chapter 4, page 2, Section 4.3, added pin numbers for J11 & J14 drawing, changed pin 6, & 11
to circles, they were previously squares which represent pin 1.
6) August 15, 1997: merged all files into one.
7) September 15, 1997: corrected errors Section 4.0 and 4.1, typos.
8) September 29, 1997: corrected errors, Section 1.2: deleted reference to figure 1.2-1 Corrected addresses,
Sections: 3.1.6.14.2, 3.1.6.15.1, 3.1.6.15.2, 3.1.6.25.1, and 3.1.6.25.2. Temporarily inserted Figure 1.1-1 after
Section 1.2. Verified all serial control register offset addresses.
9) September 30, 1997: Section 3.1.5.3, moved D3..7 and D8..15 to end of list, deleted D0..7(text). Changed
heading format, created new table of contents. Section 2.3: Reworded, Section 3.1.2.1: added note about self-
timed pulse, Section 3.1.4: changed reference to: is status and is not status to: is empty and is not empty. Section
3.1.5.1: added almost to bit descriptions D11and D13. Section 3.1.5.3: inserted description of vector register
encoding. Section 3.1.6: inserted reference to Zilog references, which were also inserted into related
publications. Section 3.1.6.1.1: added WO to description. Inserted block diagram (figure 1.1-1) directly after
section 1.2. Section 1.0,a., (6): added note about VME DMA controller.
10) October 1, 1997: Section 3.1.1.3: added self-timed note to bit D0’s description, Section 3.1.4, Section 3.1.5.1,
and Section 3.1.5.2: reworded bit descriptions to be more understandable. Section 3.1.5.3: Changed to hardware
encoded and software selectable. Section 3.1.5: reworded serial controller note. Section 3.1.6.16: changed
Receive Data Register to Status Interrupt Control (which was left out) and inserted it’s bit descriptions. Section
3.1.6.17: made Low and High both Tx and Rx.
11) October 21, 1997: Section 3.0, Table 3.0-1, adress offset 0x20, changed to RO.
12) Sept 25, 2003 cleaned up Address Jumper Tables –Corrected error where text did not match jumpers shown.
Changed Manual Revision to B.

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TABLE OF CONTENTS
CHAPTER 1: INTRODUCTION............................................................................................................................8
1.0 INTRODUCTION.......................................................................................................................................8
1.1 FUNCTIONAL DESCRIPTION.................................................................................................................8
1.2 BOARD IDENTIFICATION.......................................................................................................................8
1.3 BOARD CONTROL REGISTER..............................................................................................................10
1.4 BOARD STATUS REGISTER .................................................................................................................10
1.5 SYNC WORD SELECTION.....................................................................................................................10
1.6 DATA RECEPTION .................................................................................................................................10
1.7 DATA TRANSMIT...................................................................................................................................10
1.8 LOOP-BACK TESTING...........................................................................................................................10
1.9 ERROR DETECTION...............................................................................................................................10
1.10 INTERRUPTS...........................................................................................................................................10
1.11 DIAGNOSTIC LED DISPLAYS...............................................................................................................11
1.12 CABLE INTERFACE CONNECTIONS...................................................................................................11
CHAPTER 2: THEORY OF OPERATION.........................................................................................................12
2.0 THE BOARD INTERFACE......................................................................................................................12
2.1 INTERRUPTS...........................................................................................................................................12
2.2 DESCRIPTION OF DMA.........................................................................................................................12
2.3 CABLE ......................................................................................................................................................13
2.4 TRANSMIT RECEIVE CLOCK...............................................................................................................13
CHAPTER 3: PROGRAMMING.........................................................................................................................14
3.0 REGISTER MAP.......................................................................................................................................14
3.1 REGISTER BIT MAPS.............................................................................................................................15
3.1.1 BOARD CONTROL/STATUS REGISTERS: ......................................................................................15
3.1.1.1 Board ID Register:......................................................................................................................................15
3.1.1.2 Device Type Register: ................................................................................................................................15
3.1.1.3 Board Control Register:..............................................................................................................................15
3.1.1.4 Board Status Register:................................................................................................................................15
3.1.2 I/O CONTROL REGISTERS:.............................................................................................................15
3.1.2.1 Channel 0 Control Register: (same format for Channels 1..3 Control Registers).....................................15
3.1.3 Channel 0 FIFO: (same format for Channels 1..3 FIFO) ................................................................16
3.1.4 Channel 0 FIFO Status Register: (same format for Channels 1..3 FIFO Status Registers).............16
3.1.5 INTERRUPT CONTROL/STATUS REGISTERS: ..............................................................................17
3.1.5.1 Interrupt Control Register...........................................................................................................................17
3.1.5.2 Interrupt Status Register (Dual Purpose Bits): (ICR -Interrupt Control Register)....................................18
3.1.5.3 Interrupt Vector Register............................................................................................................................21
3.1.5 SERIAL CONTROLLER REGISTERS................................................................................................21
3.1.6.1 Channel Command/Address Register (Address: 00000)................................................................................21
3.1.6.1.1 Low WO: (Offset Address: 0x00) ..........................................................................................................21
3.1.6.1.2 High WO: (Offset Address: 0x02)..........................................................................................................22
3.1.6.2 Channel Mode Register (Address: 00001).....................................................................................................22
3.1.6.2.1 Low: (Offset Address: 0x04)..................................................................................................................23
3.1.6.2.2 High: (Offset Address: 0x06).................................................................................................................23
3.1.6.3 Channel Command/Status Register (Address: 00010)...................................................................................24
3.1.6.3.1 Low: (Offset Address: 0x08)..................................................................................................................24
3.1.6.3.2 High: (Offset Address: 0x0A) ................................................................................................................24
3.1.6.4 Channel Control Register (Address: 00011)..................................................................................................25
3.1.6.4.1 Low: (Offset Address: 0x0C) .................................................................................................................25
3.1.6.4.2 High: Address: 00011 ............................................................................................................................25
3.1.6.5 Primary Reserved Register (Address: 00100)................................................................................................25
3.1.6.5.1 Low: (Offset Address: 0x10)..................................................................................................................25

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3.1.6.5.2 High: (Offset Address: 0x12).................................................................................................................25
3.1.6.6 Secondary Reserved Register (Address: 00101)...............................................................................26
3.1.6.6.1 Low: (Offset Address: 0x14)..................................................................................................................26
3.1.6.6.2 High: (Offset Address: 0x16).................................................................................................................26
3.1.6.7 Test Mode Data Register (Address: 00110)......................................................................................26
3.1.6.7.1 Low: (Offset Address: 0x18)......................................................................................................................26
3.1.6.7.2 High: (Offset Address: 0x1A) ................................................................................................................26
3.1.6.8 Test Mode Control Register (Address: 00111) .................................................................................26
3.1.6.8.1 Low: (Offset Address: 0x1C) .................................................................................................................26
3.1.6.8.2 High: (Offset Address: 0x1E).................................................................................................................27
3.1.6.9 Clock Mode Control Register (Address: 01000)...............................................................................27
3.1.6.9.1 Low: (Offset Address: 0x20)..................................................................................................................27
3.1.6.9.2 High: (Offset Address: 0x22).................................................................................................................28
3.1.6.10 Hardware Configuration Register (Address: 01001) ......................................................................28
3.1.6.10.1 Low: (Offset Address: 0x24).....................................................................................................................28
3.1.6.10.2 High: (Offset Address: 0x26)....................................................................................................................29
3.1.6.11 Interrupt Vector Register (Address: 01010) ....................................................................................30
3.1.6.11.1 Low: (Offset Address: 0x28).....................................................................................................................30
3.1.6.11.2 High: (Offset Address: 0x2A) ...................................................................................................................30
3.1.6.12 I/O Control Register (Address: 01011)............................................................................................30
3.1.6.12.1 Low: (Offset Address: 0x2C)....................................................................................................................30
3.1.6.12.2 High: (Offset Address: 0x2E)....................................................................................................................31
3.1.6.13 interrupt Control Register (Address: 01100)...................................................................................31
3.1.6.13.1 Low: (Offset Address: 0x30).....................................................................................................................31
3.1.6.13.2 High: (Offset Address: 0x32)....................................................................................................................32
3.1.6.14 Daisy-Chain Control Register (Address: 01101).............................................................................32
3.1.6.14.1 Low: (Offset Address: 0x34).....................................................................................................................32
3.1.6.14.2 High RW: (Offset Address: 0x36)..............................................................................................................32
3.1.6.15 Misc. Interrupt Status Register (Address: 01110)...........................................................................33
3.1.6.15.1 Low: (Offset Address: 0x38).....................................................................................................................33
3.1.6.15.2 High: (Offset Address: 0x3A) ...................................................................................................................33
3.1.6.16 status interrupt control Register (Address: 01111) .........................................................................33
3.1.6.16.1 Low: (Offset Address: 0x3C)....................................................................................................................33
3.1.6.16.2 High: (Offset Address: 0x3E65)................................................................................................................33
3.1.6.17 Tx/Rx Data Register (Address: 1x000) ............................................................................................34
3.1.6.17.1 Low: (Offset Address: 0x40).....................................................................................................................34
3.1.6.17.2 High: (Offset Address: 0x42)....................................................................................................................34
3.1.6.18 Receiver Mode Register (Address: 10001) ......................................................................................34
3.1.6.18.1 Low: (Offset Address: 0x44).....................................................................................................................34
3.1.6.18.2 High: (Offset Address: 0x46)....................................................................................................................34
3.1.6.19 Receive Command Status Register (Address: 10010)......................................................................35
3.1.6.19.1 Low: (Offset Address: 0x48).....................................................................................................................35
3.1.6.19.2 High: (Offset Address: 0x4A) ...................................................................................................................35
3.1.6.20 Receive Interrupt Control Register (Address: 10011).....................................................................36
3.1.6.20.1 Low: (Offset Address: 0x4C)....................................................................................................................36
3.1.6.20.2 High: (Offset Address: 0x4E)....................................................................................................................36
3.1.6.21 Receive Sync Register (Address: 10100) .........................................................................................36
3.1.6.21.1 Low: (Offset Address: 0x50).....................................................................................................................36
3.1.6.21.2 High: (Offset Address: 0x52).....................................................................................................................36
3.1.6.22 Receive Count Limit Register (Address: 10101)..............................................................................36
3.1.6.22.1 Low: (Offset Address: 0x54)......................................................................................................................36
3.1.6.22.2 High: (Offset Address: 0x56).....................................................................................................................36
3.1.6.23 Receive Character Count Register (Address: 10110)......................................................................36
3.1.6.23.1 Low: (Offset Address: 0x58).....................................................................................................................36
3.1.6.23.2 High: (Offset Address: 0x5A) ...................................................................................................................37
3.1.6.24 Time Constant 0 Register (Address: 10111)....................................................................................37
3.1.6.24.1 Low: (Offset Address: 0x5C)....................................................................................................................37
3.1.6.24.2 High: (Offset Address: 0x5E)....................................................................................................................37

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3.1.6.25 Transmit Mode Register (Address: 11001)......................................................................................37
3.1.6.25.1 Low: (Offset Address: 0x64).....................................................................................................................37
3.1.6.25.2 High: (Offset Address: 0x66)....................................................................................................................37
3.1.6.26 Transmit Command/Status Register (Address: 11010)....................................................................38
3.1.6.26.1 Low: (Offset Address: 0x68).....................................................................................................................38
3.1.6.26.2 High: (Offset Address: 0x6A) ...................................................................................................................38
3.1.6.27 Transmit Interrupt Control Register (Address: 11011) ...................................................................39
3.1.6.27.1 Low: (Offset Address: 0x6C)....................................................................................................................39
3.1.6.27.2 High: (Offset Address: 0x6E)....................................................................................................................39
3.1.6.28 Transmit Sync Register (Address: 11100) .......................................................................................39
3.1.6.28.1 Low: (Offset Address: 0x70).....................................................................................................................39
3.1.6.28.2 High: (Offset Address: 0x72)....................................................................................................................39
3.1.6.29 Transmit Count Limit Register (Address: 11101)............................................................................39
3.1.6.29.1 Low: (Offset Address: 0x74).....................................................................................................................39
3.1.6.29.2 High: (Offset Address: 0x76)....................................................................................................................40
3.1.6.30 Transmit Character Count Register (Address: 11110)....................................................................40
3.1.6.30.1 Low: (Offset Address: 0x78).....................................................................................................................40
3.1.6.30.2 High: (Offset Address: 0x7A) ...................................................................................................................40
3.1.6.31 Time Constant 1 Register (Address: 11111)....................................................................................40
3.1.6.31.1 Low: (Offset Address: 0x7C)....................................................................................................................40
3.1.6.31.2 High: (Offset Address: 0x7E)....................................................................................................................40
CHAPTER 4: HARDWARE CONFIGURATION..............................................................................................41
4.0 THE ON-BOARD TRANSMIT/RECEIVE CLOCK................................................................................41
4.1 IRQ LEVEL SELECT JUMPERS (J6).....................................................................................................41
4.2 BASE ADDRESS JUMPERS (J1, J4, J5) ................................................................................................41
4.3 THE ZILOG CLOCK SELECT JUMPERS (J11, J14).............................................................................42
4.4 THE CHANNEL PIN-OUT JUMPERS (J10, J12, J13, J15) ...................................................................43

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CHAPTER 1: INTRODUCTION
1.0 INTRODUCTION
The VME-SI04 interface card is capable of transmitting and receiving serial data, generating interrupts, and
providing loop-back testing.
This card provides the following specific functionality:
a. VMEbus Interface:
(1) 6U card (single slot. IEEE/ANSI-1014 compliant; A16/D16 support or better.
(2) VMEbus interrupter functionality.
(3) Jumper selectable configuration of the interrupt level and programmable interrupt vectors.
(4) FIFOs (32K x 8 bit) are provided for data transmit and for data receive to increase the size of the
transmit and receive buffers
(5) User interface signal connections are provided via 4 connectors on the front panel.
(6) All data transfers to/from the FIFOs will be via host CPU writes/reads, i.e., the board does not
include a VME DMA controller, hence this board cannot act as a VME bus master.
(7) The card also provides for self-test loop-back for verification of proper operation.
b. The following two modes of loop-back testing will be supported:
(1) internal loop-back testing (does not drive cable);
(2) external loop-back testing via an external loop-back test cable.
1.1 FUNCTIONAL DESCRIPTION
As shown in the functional block diagram (see Figure 1.1-1), this board includes the following:
a. VMEbus slave interface;
b. VMEbus interrupt module;
c. board control/status registers;
d. transceiver control logic;
e. LEDs for board status indication;
f. an oscillator (for synchronization of all logic on the board);
g. a cable data driver;
h. a cable data receiver (receive voltage level converter);
i. a transmit FIFO;
j. a receive FIFO.
1.2 BOARD IDENTIFICATION
Two (2) read-only registers will be provided for board identification:
a. manufacturer’s ID; and
b. board type.
These two registers will be modeled after the VXI specification.
The manufacturer’s ID register will return 0xFEAC when read, while the board type register will return 0xF4E4
when read. These two registers will give an indication of basic board response.

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Figure 1.1-1: Functional Block Diagram

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1.3 BOARD CONTROL REGISTER
The board control register will provide configuration of the board, including the self-test modes.
1.4 BOARD STATUS REGISTER
The board status register will provide status with regard to receive FIFO status and transmit FIFO status.
1.5 SYNC WORD SELECTION
The sync word selection is used to provide an interrupt upon the reception of a particular character. This character is
software programmable.
1.6 DATA RECEPTION
Data is received into the Zilog Z16C30, after which the software may retrieve the data from the Z16C30 or the main
Rx FIFOs, depending on how the Z16C30 has been initialized.
1.7 DATA TRANSMIT
Data is received into the Zilog Z16C30, after which the software may write data to the master FIFOs or to the Zilog
depending on how the Z16C30 has been initialized. At this point, the Zilog can be placed into a transmit mode.
1.8 LOOP-BACK TESTING
The card is designed with sufficient built-in loop-back testing capability in order to allow software to perform fault
isolation to the VME card level, and replacement within 30 minutes.
The following modes of loop-back testing are supported:
a. internal loop-back testing (does not drive the cable);
b. external loop-back testing via an external loop-back test cable.
1.9 ERROR DETECTION
Error detection built into the board includes the following:
a. parity error detection;
b. CRC error detection;
c. Rx overrun;
d. Tx underrun.
1.10 INTERRUPTS
Interrupts will be provided for the following conditions:
a. Sync word detected;
b. Tx FIFO empty;
c. Rx FIFO not empty;
d. Rx FIFO almost full.

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Interrupt status bits are cleared by writing a 1 to the respective bit in the interrupt status register. A second interrupt
from that bit will not occur until after that status bit has been cleared.
1.11 DIAGNOSTIC LED DISPLAYS
LEDs provide for indication of the following conditions:
a. BIT loop-back pass/fail status (FAIL LED);
b. Channel 0 Receiver is empty
c. Channel 1 Receiver is empty
d. Channel 2 Receiver is empty
e. Channel 3 receiver is empty
f. IRQ Pending
g. VME Access
h. Spare LED.
1.12 CABLE INTERFACE CONNECTIONS
There are four female DB25 cable interface (user I/O interface) connectors mounted at the front edge of the board:
P3 –Channel 0, P4 –Channel 1, P5 –Channel 2, P6 –Channel 3. The pinout is shown below:
Signal Name Rev N/R Rev A
Lower TxD/RxD + Pin 25 Pin 3
Lower TxD/RxD -Pin 12 Pin 16
Lower CTS/DCD + Pin 24 Pin 5
Lower CTS/DCD -Pin 11 Pin 18
Lower Tx/Rx CLK + Pin 23 Pin 9
Lower Tx/Rx CLK -Pin 10 Pin 22
Upper TxD/RxD -Pin 9 Pin 10
Upper TxD/RxD + Pin 22 Pin 23
Upper CTS/DCD -Pin 8 Pin 11
Upper CTS/DCD + Pin 21 Pin 24
Upper Tx/Rx CLK -Pin 7 Pin 12
Upper Tx/Rx CLK + Pin 20 Pin 25

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CHAPTER 2: THEORY OF OPERATION
2.0 THE BOARD INTERFACE
This board operates as an interface for two Zilog Z16C30s, giving it Quad Channel capabilities. The Zilogs are
mapped into the base address of this board and all reads and writes are PIOs. This board does not offer DMA across
the VMEbus. All references to DMA in this documentation are in reference to moving data from the external FIFOs
into the Zilogs or from the Zilogs into the receive FIFOs, by means of an “onboard only” DMA. These FIFOs
operate as additional buffering of 32 K bytes for both transmit and receive. These FIFOs are in addition to the
internal FIFOs of the Zilog; however, these FIFOs are not at the same address location. To implement the use of the
external FIFOs, the software must first initialize the Zilog to request DMA services for transmit or receive. When
the request is made, the onboard logic will either move the data from the transmit FIFO into the Zilog or from the
Zilog into the receive FIFOs depending on which request was made.
2.1 INTERRUPTS
The interrupts on this board are divided into two sections:
a. Master Board Interrupts: For use with conditions on the board, not pertaining to the Zilogs.
b. Zilog Interrupts: For use with conditions within the Zilog, not pertaining to the Board.
The interrupts for the onboard logic use the master vector register. The interrupts for the Zilog use the Zilog vector
registers. All interrupts are mapped directly to the VME and they are prioritized via “Round Robin” going from 0 to
3 and then to the master board. No two levels of interrupts will occur at the same time. The interrupt level is
selected via jumper.
2.2 DESCRIPTION OF DMA
DMA for all channels is performed in the same manner. The request is made, that is, one of the transmit or receive
DMA request signals go active from the Zilog. The onboard DMA logic will handshake with the Zilog to either
acknowledge valid data going to the Zilog or to get receive data from the Zilog. This activity will continue until the
Zilog no longer needs DMA service, or the external FIFOs can no longer comply. If the Zilog no longer wants
DMA, it will remove its request and the DMA will stop. The conditions at which the FIFOs can no longer comply
are when during a transmit request and the transmit FIFO is empty or during a receive request when a receive FIFO
is full. Channel 0 and 1 operate using the same Zilog bus, so therefore it must arbitrate between Channel 0 transmit
and receive, as well as Channel 1 transmit and receive. This arbitration takes place without any software
initialization.
If all four (4) DMA requests are active at the same time, this will handshake one word for one request and then
proceed to the next. It will start with the receive data and will acknowledge one word for the receive of Channel 0,
then one word of the receive for Channel 1, then one word for the transmit for Channel 0, then one word of the
transmit for Channel 1 and then it will start over.
This transmission of data from one point to another will only occur if the FIFO’s are in a valid state, i.e., transmit
FIFO must not be empty; otherwise the handshake will not take place with the Zilog. Then, the Zilog will not get an
acknowledge for its’ transmit request and will get no data.
The same is true for the receive FIFO. If the receive FIFO is full, the DMA will not remove data from the Zilog.
Therefore the Zilog will not get an acknowledge, and will not have any data removed from it.
Channels 2 and 3 work in the same way, but work on a different data bus. Therefore DMAs for Channels 2 and 3, to
or from the Zilog will not affect Channels 0 and 1. This means Channel 0 can run at full speed and Channel 2 can

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run at full speed without interfering with each other. The VME can read and write the Zilog during DMA cycles.
However, it must wait until the end of the current DMA access when the DMA finishes its current access, then the
VME will be allowed onto the Zilog bus.
When the Zilog bus is free from the VME, the DMA will restart. The same holds true for interrupts. If a VME or
interrupt access to or from the Zilog is currently taking place, and a DMA request is made, the DMA will wait until
the current access cycle has completed and the bus for the Zilog is free before it starts the DMA transfers.
2.3 CABLE
The Cable is configured as upper and lower so that one cable can be used for both transmit and receive, therefore
allowing full duplex capabilities for each channel. Each channel has a control register that can be set to transmit
upper or lower and to receive upper or lower. It is not possible to receive both but it is possible to transmit both. If
the channel control register is not told to transmit or receive upper and not told to transmit or receive lower, then this
board will not drive the cable, nor will it load the cable, i.e., this channel will be tri-stated.
If an external loopback test is desired to be performed without a cable, the software can set it up to do transmit,
upper or lower, and to receive the same. The effect given will be an external loopback without a cable.
2.4 TRANSMIT RECEIVE CLOCK
The transmit receive clock is controlled via a 3 x 5 jumper. If the jumper is removed, for a particular clock, it is
expected that the Zilog will produce the transmit receive clock. It cannot output a clock to the half of the cable that
it is receiving from. It can output a clock to the cable it is transmitting to. If the jumper is selected for “receive
clock”, the Zilog will get its’ clock from the cable, given that the software has chosen the cable as receive. If the
Zilog clock is chosen for the onboard transmit receive clock, then the Zilog will get its’ clock from the local
oscillator, factory installed at 20.0 megahertz.
NOTE: Care must be taken when setting these jumpers. If the jumper is installed and the Zilog drives a clock out,
then a conflict between clocks will exist.

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CHAPTER 3: PROGRAMMING
3.0 REGISTER MAP
The register address map for the VME-SI04 is shown below.. This board contains registers for Board Control, I/O
Control, FIFO Control, Interrupt Control and Serial Controller.
Table 3.0-1 VME-SI04 Register Address Map
Address
Offset Size* Access** Register Name
Board 0x00 D16 RO Board ID
Control/Status 0x02 D16 RO Device Type
Registers 0x08 D16 RW Board Control
0x0A D16 RO Board Status
Channel 0x10 D16 RW Channel 0 Control
Control 0x12 D16 RW Channel 1 Control
Registers 0x14 D16 RW Channel 2 Control
0x16 D16 RW Channel 3 Control
FIFOs 0x18 D16 RW Channel 0 FIFO
0x1A D16 RW Channel 1 FIFO
0x1C D16 RW Channel 2 FIFO
0x1E D16 RW Channel 3 FIFO
FIFO 0x20 D16 RO Channel 0 FIFO Status
Status 0x22 D16 RO Channel 1 FIFO Status
Registers 0x24 D16 RO Channel 2 FIFO Status
0x26 D16 RO Channel 3 FIFO Status
Sync Word 0x28 D16 RW Channel 0 Sync Word Register
Registers 0x2A D16 RW Channel 1 Sync Word Register
0x2C D16 RW Channel 2 Sync Word Register
0x2E D16 RW Channel 3 Sync Word Register
Interrupt 0x30 D16 RW Interrupt Control
Control/Status 0x32 D16 RW Interrupt Status
Registers 0x34 D16 RW Interrupt Vector
Serial 0x200-27E D16 BD Channel 0 USC Control
Controller 0x280-2EE D16 BD Channel 1 USC Control
Registers 0x300-37E D16BD Channel 2 USC Control
0x380-3EE D16 BD Channel 3 USC Control
* The register address offset can be selected to be in short address space (A16) or in standard address
space (A24).
** RO = read only
WO = write only
RW = read/write capability
BD = Bit Dependent

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3.1 REGISTER BIT MAPS
All Reserved bits should be set to 0for future compatibility. Also, the value read from a reserved bit will be
indeterminate.
3.1.1 BOARD CONTROL/STATUS REGISTERS:
3.1.1.1 Board ID Register:
D0..D16 Reads back hex CEAC
3.1.1.2 Device Type Register:
D0..D16 Reads back hex F4E4
3.1.1.3 Board Control Register:
D0 Board Reset L (pulsed)
1will generate a self-timed pulse that will reset the board.
(There is no need for the software to return to clear this bit)
0will not generate a self-timed pulse that will reset the board
(There is no need for the software to return to clear this bit)
D1 Enable Interrupts
1 will enable this board to generate VME interrupts.
0will disable the board from generating VME interrupts.
D2..3 Reserved
D4 Spare LED On (A software controlled bit.)
1will turn off the Fail LED
0 will turn on the Fail LED
D5..6 Reserved
D7 Fail LED On L (A software controlled bit.)
1 will turn off the Fail LED
0 will turn on the Fail LED.
D8..D15 Reserved
3.1.1.4 Board Status Register:
D0..D15 Reserved
3.1.2 I/O CONTROL REGISTERS:
3.1.2.1 Channel 0 Control Register: (same format for Channels 1..3 Control Registers)
D0 Reset Tx Buffer (pulsed)
1 will generate a self-timed pulse that will reset the Tx Buffer.
(There is no need for the software to return to clear this bit)
D1 Reset Rx Buffer (pulsed)
1will generate a self-timed pulse that will reset the Rx Buffer.
(There is no need for the software to return to clear this bit)
D2 Enable interrupts for channel number.
1will enable this board to generate interrupts for this channel number.
0will disable the board from generating interrupts for this channel number.
D3 Reserved

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D4 En Drive Lower Cable H
1will enable this board to drive the lower cable.
0will disable this board from driving the lower cable.
D5 En Drive Upper Cable H
1 will enable this board to drive the upper cable.
0 will disable this board from driving the upper cable.
D6 En Rx Lower Cable L
1will enable RX to drive the lower cable.
0will disable RX from driving the lower cable.
D7 En Rx Upper Cable L
1 will enable Rx to drive the upper cable.
0will disable Rx from driving the upper cable.
D8..D15 Reserved
3.1.3 CHANNEL 0 FIFO: (SAME FORMAT FOR CHANNELS 1..3 FIFO)
D0..D7 Valid
D8..D15 Reserved
3.1.4 CHANNEL 0 FIFO STATUS REGISTER: (SAME FORMAT FOR CHANNELS 1..3 FIFO STATUS
REGISTERS)
D0Tx FIFO Empty L
0indicates that the Tx FIFO is empty.
1indicates that the Tx FIFO is not empty.
D1 Tx FIFO Almost Empty L
0indicates that the Tx FIFO is almost empty.
1 indicates that the Tx FIFO is not almost empty.
D2 Tx FIFO Almost Full L
0indicates that the Tx FIFO is almost full.
1 indicates that the Tx FIFO is not almost full.
D3 Tx FIFO Full L
0 indicates that the Tx FIFO Full L is full.
1indicates that the Tx FIFO Full L is not full.
D4 Rx FIFO Empty L
0indicates that the Rx FIFO is empty.
1 indicates that the Rx FIFO is not empty.
D5 Rx FIFO Almost Empty L
0indicates that the Rx FIFO is almost empty.
1indicates that the Rx FIFO is not almost empty.
D6 Rx FIFO Almost Full L
0 indicates that the Rx FIFO is almost full.
1indicates that the Rx FIFO is not almost full.
D7 Rx FIFO Full L
0indicates that the Rx FIFO is full.
1 indicates that the Rx FIFO is not full.
D8..D15 Reserved

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3.1.5 INTERRUPT CONTROL/STATUS REGISTERS:
3.1.5.1 Interrupt Control Register
D0 Enable Channel 0 Sync Detected
1will enable this board to generate an interrupt when a sync word is detected.
0 will disable this board from generating an interrupt when a sync word is
detected.
D1 Enable Channel 0 Tx FIFO Empty Interrupt
1will enable this board to generate an interrupt when the Tx FIFO is empty.
0will disable this board from generating an interrupt when the Tx FIFO is
empty.
D2 Enable Channel 1 Sync Detected
1will enable this board to generate an interrupt when a Sync word is detected
0 will disable this board from generating an interrupt when a Sync word is
detected.
D3 Enable Channel 1 Tx FIFO Empty Interrupt
1will enable this board to generate an interrupt when the Tx FIFO is empty.
0will disable this board from generating an interrupt when the Tx FIFO is
empty.
D4 Enable Channel 2 Tx Sync Detected
1will enable this board to generate an interrupt when a Tx Sync word is
detected.
0will disable this board from generating an interrupt when a Tx Sync word is
detected.
D5 Enable Channel 2 Tx FIFO Empty Interrupt
1 will enable this board to generate an interrupt when the Tx FIFO is empty.
0will disable this board from generating an interrupt when the Tx FIFO is
empty.
D6 Enable Channel 3 Tx Sync Detected
1will enable this board to generate an interrupt when a Tx Sync word is
detected.
0will disable this board from generating an interrupt when a Tx Sync word is
detected.
D7 Enable Channel 3 Tx FIFO Empty Interrupt
1 will enable this board to generate an interrupt when the Tx FIFO is empty.
0will disable this board from generating an interrupt when the Tx FIFO is
empty.
D8 Enable Channel 0 Rx FIFO Not Empty Interrupt
1will enable this board to generate an interrupt when the Rx FIFO is not empty.
0will disable this board from generating an interrupt when the Rx FIFO is not
empty.
D9 Enable Channel 0 Rx FIFO Almost Full Interrupt
1will enable this board to generate an interrupt when the Rx FIFO is full.
0will disable this board from generating an interrupt when the Rx FIFO is full.
D10 Enable Channel 1 Rx FIFO Not Empty Interrupt
1will enable this board to generate an interrupt when Rx FIFO is not empty.
0 will disable this board from generating an interrupt when Rx FIFO is not
empty.
D11 Enable Channel 1 Rx FIFO Almost Full Interrupt
1will enable this board to generate an interrupt when the Rx FIFO is almost full.
0will disable this board from generating an interrupt when the Rx FIFO is
almost full.
D12 Enable Channel 2 Rx FIFO Not Empty Interrupt

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1will enable this board to generate an interrupt when the Rx FIFO is not empty.
0will disable this board from generating an Interrupt when the Rx FIFO is not
empty.
D13 Enable Channel 2 Rx FIFO Almost Full Interrupt
1will enable this board to generate an interrupt when the Rx FIFO is almost full.
0 will disable this board from generating an interrupt when the Rx FIFO is
almost full.
D14 Enable Channel 3 Rx FIFO Not Empty Interrupt
1will enable this board to generate an interrupt when the Rx FIFO is not empty.
0will disable this board from generating an interrupt when the Rx FIFO is not
empty.
D15 Enable Channel 3 Rx FIFO Almost Full Interrupt
1 will enable this board to generate an interrupt when the Rx FIFO is almost full.
0will disable this board from generating an interrupt when the Rx FIFO is
almost full.
3.1.5.2 Interrupt Status Register (Dual Purpose Bits): (ICR -Interrupt Control Register)
D0 Channel 0 Tx FIFO Sync Detected
If this interrupt is enabled:
1indicates an interrupt has occurred.
0indicates an interrupt has not occurred.
If this interrupt is not enabled:
0indicates the current status of this interrupt
source.
1being the source of the interrupt is present.
0being not true the source of the interrupt is not present.
D1 Channel 0 Tx FIFO Empty Interrupt
If this interrupt is enabled:
1 indicates an interrupt has occurred.
0indicates an interrupt has not occurred.
If this interrupt is not enabled:
0indicates the current status of this interrupt source.
1being the source of the interrupt is present.
0being the source of the interrupt is not present.
D2 Channel 1 Tx FIFO Sync Detected
If this interrupt is enabled:
1indicates an interrupt has occurred.
0indicates an interrupt has not occurred.
If this interrupt is not enabled:
0 indicates the current status of this interrupt source.
1being the source of the interrupt is present.
0being the source of the interrupt is not present.
D3 Channel 1 Tx FIFO Empty Interrupt
If this interrupt is enabled:
1indicates an interrupt has occurred.
0indicates an interrupt has not occurred.
If this interrupt is not enabled:
0indicates the current status of this interrupt source.
1being the source of the interrupt is present.
0being the source of the interrupt is not present.
D4 Channel 2 Sync Detected
If this interrupt is enabled:
1indicates an interrupt has occurred.

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0indicates an interrupt has not occurred.
If this interrupt is not enabled:
0 indicates the current status of this interrupt source.
1being the source of the interrupt is present.
0 being the source of the interrupt is not present.
D5 Channel 2 Tx FIFO Empty Interrupt
If this interrupt is enabled:
1indicates an interrupt has occurred.
0 indicates an interrupt has not occurred.
If this interrupt is not enabled:
0indicates the current status of this interrupt source.
1being the source of the interrupt is present.
0being the source of the interrupt is not present.
D6 Channel 3 Sync Detected
If this interrupt is enabled:
1indicates an interrupt has occurred.
0indicates an interrupt has not occurred.
If this interrupt is not enabled:
0indicates the current status of this interrupt source.
1being the source of the interrupt is present.
0being the source of the interrupt is not present.
D7 Channel 3 Tx FIFO Empty Interrupt
If this interrupt is enabled:
1indicates an interrupt has occurred.
0indicates an interrupt has not occurred.
If this interrupt is not enabled:
0indicates the current status of this interrupt source.
1 being the source of the interrupt is present.
0being the source of the interrupt is not present.
D8 Channel 0 Rx FIFO Not Empty Interrupt
If this interrupt is enabled:
1indicates an interrupt has occurred.
0indicates an interrupt has not occurred.
If this interrupt is not enabled:
0indicates the current status of this interrupt source.
1being the source of the interrupt is present.
0being the source of the interrupt is not present.
D9 Channel 0Rx FIFO Almost Full Interrupt
If this interrupt is enabled:
1 indicates an interrupt has occurred.
0indicates an interrupt has not occurred.
If this interrupt is not enabled:
0indicates the current status of this interrupt source.
1 being the source of the interrupt is present.
0being the source of the interrupt is not present.
D10 Channel 1 Rx FIFO Not Empty Interrupt
If this interrupt is enabled:
1 indicates an interrupt has occurred.
0indicates an interrupt has not occurred.
If this interrupt is not enabled:
0indicates the current status of this interrupt source.
1being the source of the interrupt is present.
0 being the source of the interrupt is not present.
D11 Channel 1 Rx FIFO Almost Full Interrupt