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Revision B User Manual
for the VME-SIO4: Board Revision: A
General Standards Corporation
8302A Whitesburg Drive Huntsville, AL 3580, Phone: [phone]
1
VME-SIO4A
User Manual
Manual Revision: B
General Standards Corporation
8302A Whitesburg Drive
Huntsville, AL 35802
Phone: [phone]
Fax: [phone]
URL :http://www.generalstandards.com
E-mail: [email protected]

Revision B User Manual
for the VME-SIO4: Board Revision: A
General Standards Corporation
8302A Whitesburg Drive Huntsville, AL 3580, Phone: [phone]
2
PREFACE
Copyright © 1997 General Standards Corp.
Additional copies of this manual or other General Standards Corporation literature may be obtained from:
General Standards Corporation
8302A Whitesburg Drive
Huntsville, Alabama 35802
Telephone: [phone]
Fax: [phone]
Company URL: www.generalstandards.com
The information in this document is subject to change without notice.
General Standards Corporation makes no warranty of any kind with regard to this material, including, but not
limited to, the implied warranties of merchantability and fitness for a particular purpose. Although extensive editing
and reviews are performed before release to ECO control, General Standards Corporation assumes no
responsibility for any errors that may exist in this document. No commitment is made to update or keep current the
information contained in this document.
General Standards Corporation does not assume any liability arising out of the application or use of any product
or circuit described herein, nor is any license conveyed under any patent right of any rights of others.
General Standards Corporation assumes no responsibility resulting from omissions or errors in this manual, or
from the use of information contained herein.
General Standards Corporation reserves the right to make any changes, without notice, to this product to improve
reliability, performance, function, or design.
All rights reserved
No parts of this document may be copied or reproduced in any form or by any means without prior written consent of
General Standards Corporation.
This user’s manual provides information on the specifications, theory of operation, register level programming, and
installation of the VME-SIO4 board.
Information required for customized hardware/software development.
This manual assumes that the user is familiar with the VMEbus interface specification. In an effort to avoid
redundancy, this manual relies on data books, other manuals, and specifications as indicated in the related
publication section.

Revision B User Manual
for the VME-SIO4: Board Revision: A
General Standards Corporation
8302A Whitesburg Drive Huntsville, AL 3580, Phone: [phone]
3
Related Publications
The following manuals and specifications provide the necessary information for in-depth understanding of the
VMEbus and specialized parts used on this board.
EIA Standard for the RS-422-A Interface (EIA order number EIA-RS-422A)
VMEbus Specification Manual (also known as IEC 821 BUS and IEEE P10114/D1/2), for information submit
request to:
VITA10229 North Scottsdale Road, Suite B
Scottsdale, AZ 85253
Telephone: [phone]
Zilog’s USC Universal Serial Controller (part number: Z16C30) User’s Manual and Databook, for information
submit request to: Zilog, Inc.
210 East Hacienda Ave.
Campbell, CA 95008-6600
Telephone: [phone]

Revision B User Manual
for the VME-SIO4: Board Revision: A
General Standards Corporation
8302A Whitesburg Drive Huntsville, AL 3580, Phone: [phone]
4
VME-SIO4 Documentation History
1) The Vme-SIO4 documentation was updated March 1997.
2) The manual was reformatted, for conformity of text, and the table of contents was corrected.
3) The jumper field drawings in Chapter 4 were redrawn and double checked.
4) April 27, 1997: Chapter 3, page 3, Section 3.1.2.1, D6 & D7 bit descriptions were corrected, instead of: 0 will
enable Rx…, it was corrected to be a 1 will enable Rx.., and instead of 1 will disable Rx.., it was corrected to be
a 0 will disable Rx…
5) April 27, 1997: Chapter 4, page 2, Section 4.3, added pin numbers for J11 & J14 drawing, changed pin 6, & 11
to circles, they were previously squares which represent pin 1.
6) August 15, 1997: merged all files into one.
7) September 15, 1997: corrected errors Section 4.0 and 4.1, typos.
8) September 29, 1997: corrected errors, Section 1.2: deleted reference to figure 1.2-1 Corrected addresses,
Sections: 3.1.6.14.2, 3.1.6.15.1, 3.1.6.15.2, 3.1.6.25.1, and 3.1.6.25.2. Temporarily inserted Figure 1.1-1 after
Section 1.2. Verified all serial control register offset addresses.
9) September 30, 1997: Section 3.1.5.3, moved D3..7 and D8..15 to end of list, deleted D0..7(text). Changed
heading format, created new table of contents. Section 2.3: Reworded, Section 3.1.2.1: added note about self-
timed pulse, Section 3.1.4: changed reference to: is status and is not status to: is empty and is not empty. Section
3.1.5.1: added almost to bit descriptions D11and D13. Section 3.1.5.3: inserted description of vector register
encoding. Section 3.1.6: inserted reference to Zilog references, which were also inserted into related
publications. Section 3.1.6.1.1: added WO to description. Inserted block diagram (figure 1.1-1) directly after
section 1.2. Section 1.0,a., (6): added note about VME DMA controller.
10) October 1, 1997: Section 3.1.1.3: added self-timed note to bit D0’s description, Section 3.1.4, Section 3.1.5.1,
and Section 3.1.5.2: reworded bit descriptions to be more understandable. Section 3.1.5.3: Changed to hardware
encoded and software selectable. Section 3.1.5: reworded serial controller note. Section 3.1.6.16: changed
Receive Data Register to Status Interrupt Control (which was left out) and inserted it’s bit descriptions. Section
3.1.6.17: made Low and High both Tx and Rx.
11) October 21, 1997: Section 3.0, Table 3.0-1, adress offset 0x20, changed to RO.
12) Sept 25, 2003 cleaned up Address Jumper Tables –Corrected error where text did not match jumpers shown.
Changed Manual Revision to B.

Revision B User Manual
for the VME-SIO4: Board Revision: A
General Standards Corporation
8302A Whitesburg Drive Huntsville, AL 3580, Phone: [phone]
5
TABLE OF CONTENTS
CHAPTER 1: INTRODUCTION............................................................................................................................8
1.0 INTRODUCTION.......................................................................................................................................8
1.1 FUNCTIONAL DESCRIPTION.................................................................................................................8
1.2 BOARD IDENTIFICATION.......................................................................................................................8
1.3 BOARD CONTROL REGISTER..............................................................................................................10
1.4 BOARD STATUS REGISTER .................................................................................................................10
1.5 SYNC WORD SELECTION.....................................................................................................................10
1.6 DATA RECEPTION .................................................................................................................................10
1.7 DATA TRANSMIT...................................................................................................................................10
1.8 LOOP-BACK TESTING...........................................................................................................................10
1.9 ERROR DETECTION...............................................................................................................................10
1.10 INTERRUPTS...........................................................................................................................................10
1.11 DIAGNOSTIC LED DISPLAYS...............................................................................................................11
1.12 CABLE INTERFACE CONNECTIONS...................................................................................................11
CHAPTER 2: THEORY OF OPERATION.........................................................................................................12
2.0 THE BOARD INTERFACE......................................................................................................................12
2.1 INTERRUPTS...........................................................................................................................................12
2.2 DESCRIPTION OF DMA.........................................................................................................................12
2.3 CABLE ......................................................................................................................................................13
2.4 TRANSMIT RECEIVE CLOCK...............................................................................................................13
CHAPTER 3: PROGRAMMING.........................................................................................................................14
3.0 REGISTER MAP.......................................................................................................................................14
3.1 REGISTER BIT MAPS.............................................................................................................................15
3.1.1 BOARD CONTROL/STATUS REGISTERS: ......................................................................................15
3.1.1.1 Board ID Register:......................................................................................................................................15
3.1.1.2 Device Type Register: ................................................................................................................................15
3.1.1.3 Board Control Register:..............................................................................................................................15
3.1.1.4 Board Status Register:................................................................................................................................15
3.1.2 I/O CONTROL REGISTERS:.............................................................................................................15
3.1.2.1 Channel 0 Control Register: (same format for Channels 1..3 Control Registers).....................................15
3.1.3 Channel 0 FIFO: (same format for Channels 1..3 FIFO) ................................................................16
3.1.4 Channel 0 FIFO Status Register: (same format for Channels 1..3 FIFO Status Registers).............16
3.1.5 INTERRUPT CONTROL/STATUS REGISTERS: ..............................................................................17
3.1.5.1 Interrupt Control Register...........................................................................................................................17
3.1.5.2 Interrupt Status Register (Dual Purpose Bits): (ICR -Interrupt Control Register)....................................18
3.1.5.3 Interrupt Vector Register............................................................................................................................21
3.1.5 SERIAL CONTROLLER REGISTERS................................................................................................21
3.1.6.1 Channel Command/Address Register (Address: 00000)................................................................................21
3.1.6.1.1 Low WO: (Offset Address: 0x00) ..........................................................................................................21
3.1.6.1.2 High WO: (Offset Address: 0x02)..........................................................................................................22
3.1.6.2 Channel Mode Register (Address: 00001).....................................................................................................22
3.1.6.2.1 Low: (Offset Address: 0x04)..................................................................................................................23
3.1.6.2.2 High: (Offset Address: 0x06).................................................................................................................23
3.1.6.3 Channel Command/Status Register (Address: 00010)...................................................................................24
3.1.6.3.1 Low: (Offset Address: 0x08)..................................................................................................................24
3.1.6.3.2 High: (Offset Address: 0x0A) ................................................................................................................24
3.1.6.4 Channel Control Register (Address: 00011)..................................................................................................25
3.1.6.4.1 Low: (Offset Address: 0x0C) .................................................................................................................25
3.1.6.4.2 High: Address: 00011 ............................................................................................................................25
3.1.6.5 Primary Reserved Register (Address: 00100)................................................................................................25
3.1.6.5.1 Low: (Offset Address: 0x10)..................................................................................................................25

Revision B User Manual
for the VME-SIO4: Board Revision: A
General Standards Corporation
8302A Whitesburg Drive Huntsville, AL 3580, Phone: [phone]
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3.1.6.5.2 High: (Offset Address: 0x12).................................................................................................................25
3.1.6.6 Secondary Reserved Register (Address: 00101)...............................................................................26
3.1.6.6.1 Low: (Offset Address: 0x14)..................................................................................................................26
3.1.6.6.2 High: (Offset Address: 0x16).................................................................................................................26
3.1.6.7 Test Mode Data Register (Address: 00110)......................................................................................26
3.1.6.7.1 Low: (Offset Address: 0x18)......................................................................................................................26
3.1.6.7.2 High: (Offset Address: 0x1A) ................................................................................................................26
3.1.6.8 Test Mode Control Register (Address: 00111) .................................................................................26
3.1.6.8.1 Low: (Offset Address: 0x1C) .................................................................................................................26
3.1.6.8.2 High: (Offset Address: 0x1E).................................................................................................................27
3.1.6.9 Clock Mode Control Register (Address: 01000)...............................................................................27
3.1.6.9.1 Low: (Offset Address: 0x20)..................................................................................................................27
3.1.6.9.2 High: (Offset Address: 0x22).................................................................................................................28
3.1.6.10 Hardware Configuration Register (Address: 01001) ......................................................................28
3.1.6.10.1 Low: (Offset Address: 0x24).....................................................................................................................28
3.1.6.10.2 High: (Offset Address: 0x26)....................................................................................................................29
3.1.6.11 Interrupt Vector Register (Address: 01010) ....................................................................................30
3.1.6.11.1 Low: (Offset Address: 0x28).....................................................................................................................30
3.1.6.11.2 High: (Offset Address: 0x2A) ...................................................................................................................30
3.1.6.12 I/O Control Register (Address: 01011)............................................................................................30
3.1.6.12.1 Low: (Offset Address: 0x2C)....................................................................................................................30
3.1.6.12.2 High: (Offset Address: 0x2E)....................................................................................................................31
3.1.6.13 interrupt Control Register (Address: 01100)...................................................................................31
3.1.6.13.1 Low: (Offset Address: 0x30).....................................................................................................................31
3.1.6.13.2 High: (Offset Address: 0x32)....................................................................................................................32
3.1.6.14 Daisy-Chain Control Register (Address: 01101).............................................................................32
3.1.6.14.1 Low: (Offset Address: 0x34).....................................................................................................................32
3.1.6.14.2 High RW: (Offset Address: 0x36)..............................................................................................................32
3.1.6.15 Misc. Interrupt Status Register (Address: 01110)...........................................................................33
3.1.6.15.1 Low: (Offset Address: 0x38).....................................................................................................................33
3.1.6.15.2 High: (Offset Address: 0x3A) ...................................................................................................................33
3.1.6.16 status interrupt control Register (Address: 01111) .........................................................................33
3.1.6.16.1 Low: (Offset Address: 0x3C)....................................................................................................................33
3.1.6.16.2 High: (Offset Address: 0x3E65)................................................................................................................33
3.1.6.17 Tx/Rx Data Register (Address: 1x000) ............................................................................................34
3.1.6.17.1 Low: (Offset Address: 0x40).....................................................................................................................34
3.1.6.17.2 High: (Offset Address: 0x42)....................................................................................................................34
3.1.6.18 Receiver Mode Register (Address: 10001) ......................................................................................34
3.1.6.18.1 Low: (Offset Address: 0x44).....................................................................................................................34
3.1.6.18.2 High: (Offset Address: 0x46)....................................................................................................................34
3.1.6.19 Receive Command Status Register (Address: 10010)......................................................................35
3.1.6.19.1 Low: (Offset Address: 0x48).....................................................................................................................35
3.1.6.19.2 High: (Offset Address: 0x4A) ...................................................................................................................35
3.1.6.20 Receive Interrupt Control Register (Address: 10011).....................................................................36
3.1.6.20.1 Low: (Offset Address: 0x4C)....................................................................................................................36
3.1.6.20.2 High: (Offset Address: 0x4E)....................................................................................................................36
3.1.6.21 Receive Sync Register (Address: 10100) .........................................................................................36
3.1.6.21.1 Low: (Offset Address: 0x50).....................................................................................................................36
3.1.6.21.2 High: (Offset Address: 0x52).....................................................................................................................36
3.1.6.22 Receive Count Limit Register (Address: 10101)..............................................................................36
3.1.6.22.1 Low: (Offset Address: 0x54)......................................................................................................................36
3.1.6.22.2 High: (Offset Address: 0x56).....................................................................................................................36
3.1.6.23 Receive Character Count Register (Address: 10110)......................................................................36
3.1.6.23.1 Low: (Offset Address: 0x58).....................................................................................................................36
3.1.6.23.2 High: (Offset Address: 0x5A) ...................................................................................................................37
3.1.6.24 Time Constant 0 Register (Address: 10111)....................................................................................37
3.1.6.24.1 Low: (Offset Address: 0x5C)....................................................................................................................37
3.1.6.24.2 High: (Offset Address: 0x5E)....................................................................................................................37

Revision B User Manual
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8302A Whitesburg Drive Huntsville, AL 3580, Phone: [phone]
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3.1.6.25 Transmit Mode Register (Address: 11001)......................................................................................37
3.1.6.25.1 Low: (Offset Address: 0x64).....................................................................................................................37
3.1.6.25.2 High: (Offset Address: 0x66)....................................................................................................................37
3.1.6.26 Transmit Command/Status Register (Address: 11010)....................................................................38
3.1.6.26.1 Low: (Offset Address: 0x68).....................................................................................................................38
3.1.6.26.2 High: (Offset Address: 0x6A) ...................................................................................................................38
3.1.6.27 Transmit Interrupt Control Register (Address: 11011) ...................................................................39
3.1.6.27.1 Low: (Offset Address: 0x6C)....................................................................................................................39
3.1.6.27.2 High: (Offset Address: 0x6E)....................................................................................................................39
3.1.6.28 Transmit Sync Register (Address: 11100) .......................................................................................39
3.1.6.28.1 Low: (Offset Address: 0x70).....................................................................................................................39
3.1.6.28.2 High: (Offset Address: 0x72)....................................................................................................................39
3.1.6.29 Transmit Count Limit Register (Address: 11101)............................................................................39
3.1.6.29.1 Low: (Offset Address: 0x74).....................................................................................................................39
3.1.6.29.2 High: (Offset Address: 0x76)....................................................................................................................40
3.1.6.30 Transmit Character Count Register (Address: 11110)....................................................................40
3.1.6.30.1 Low: (Offset Address: 0x78).....................................................................................................................40
3.1.6.30.2 High: (Offset Address: 0x7A) ...................................................................................................................40
3.1.6.31 Time Constant 1 Register (Address: 11111)....................................................................................40
3.1.6.31.1 Low: (Offset Address: 0x7C)....................................................................................................................40
3.1.6.31.2 High: (Offset Address: 0x7E)....................................................................................................................40
CHAPTER 4: HARDWARE CONFIGURATION..............................................................................................41
4.0 THE ON-BOARD TRANSMIT/RECEIVE CLOCK................................................................................41
4.1 IRQ LEVEL SELECT JUMPERS (J6).....................................................................................................41
4.2 BASE ADDRESS JUMPERS (J1, J4, J5) ................................................................................................41
4.3 THE ZILOG CLOCK SELECT JUMPERS (J11, J14).............................................................................42
4.4 THE CHANNEL PIN-OUT JUMPERS (J10, J12, J13, J15) ...................................................................43

Revision B User Manual
for the VME-SIO4: Board Revision: A
General Standards Corporation
8302A Whitesburg Drive Huntsville, AL 3580, Phone: [phone]
8
CHAPTER 1: INTRODUCTION
1.0 INTRODUCTION
The VME-SI04 interface card is capable of transmitting and receiving serial data, generating interrupts, and
providing loop-back testing.
This card provides the following specific functionality:
a. VMEbus Interface:
(1) 6U card (single slot. IEEE/ANSI-1014 compliant; A16/D16 support or better.
(2) VMEbus interrupter functionality.
(3) Jumper selectable configuration of the interrupt level and programmable interrupt vectors.
(4) FIFOs (32K x 8 bit) are provided for data transmit and for data receive to increase the size of the
transmit and receive buffers
(5) User interface signal connections are provided via 4 connectors on the front panel.
(6) All data transfers to/from the FIFOs will be via host CPU writes/reads, i.e., the board does not
include a VME DMA controller, hence this board cannot act as a VME bus master.
(7) The card also provides for self-test loop-back for verification of proper operation.
b. The following two modes of loop-back testing will be supported:
(1) internal loop-back testing (does not drive cable);
(2) external loop-back testing via an external loop-back test cable.
1.1 FUNCTIONAL DESCRIPTION
As shown in the functional block diagram (see Figure 1.1-1), this board includes the following:
a. VMEbus slave interface;
b. VMEbus interrupt module;
c. board control/status registers;
d. transceiver control logic;
e. LEDs for board status indication;
f. an oscillator (for synchronization of all logic on the board);
g. a cable data driver;
h. a cable data receiver (receive voltage level converter);
i. a transmit FIFO;
j. a receive FIFO.
1.2 BOARD IDENTIFICATION
Two (2) read-only registers will be provided for board identification:
a. manufacturer’s ID; and
b. board type.
These two registers will be modeled after the VXI specification.
The manufacturer’s ID register will return 0xFEAC when read, while the board type register will return 0xF4E4
when read. These two registers will give an indication of basic board response.

Revision B User Manual
for the VME-SIO4: Board Revision: A
General Standards Corporation
8302A Whitesburg Drive Huntsville, AL 3580, Phone: [phone]
9
Figure 1.1-1: Functional Block Diagram