Atmel AT697F User manual

APPLICATION NOTE
AT697F Evaluation Kit
USER GUIDE
Features
The AT697F evaluation board provides the following features:
On-board power supply circuitry
for external power supply sources connection
for board powering by the CPCI interface
On-board reset
On-board memories
FLASH (40-bit capability)
SRAM (40-bit SRAM capability)
SDRAM (40-bit SDRAM capability)
Status indicators
Power
Processor Error + Run
DSU activity
Clock circuitry
On board oscillator for clock generator
External clock source connection
RS232 hardware connector dedicated to the Debug Support Unit (DSU)
RS232 hardware connector dedicated to a universal UART
PCI interface
Host / Satellite capability
User defined push-buttons
User defined LEDs
Expansion connector
10-pin JTAG interface connector
Description
The AT697F Evaluation Kit is a development system for the ATMEL AT697F, 32-bit
SPARC® V8 processor based on LEON2 fault tolerant model.
The kit is equipped with a rich set of peripherals that make the AT697F Evaluation Kit
perfect evaluation platform to quickly and easily develop application on the AT697F
processor. This guide shows the user how to quickly get started with this kit.
7540HAERO10/15

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Table of Contents
1. Overview............................................................................................4
1.1 Scope4
1.2 Deliverables ......................................................................................................4
1.3 Features............................................................................................................5
2. Hardware description.........................................................................6
2.1 Block diagram ...................................................................................................6
2.2 Evaluation board...............................................................................................7
2.3 Manufacturing configuration..............................................................................8
2.4 Board power supply ..........................................................................................9
2.5 Processor........................................................................................................10
2.5.1 Processor Package...........................................................................10
2.5.2 Processor Pin-out.............................................................................10
2.6 Memories ........................................................................................................13
2.6.1 Memory organization overview .........................................................13
2.6.2 PROM (or Flash)...............................................................................13
2.6.2.1 PROM Overview .............................................................13
2.6.2.2 PROM40 Configuration (SW37.7 is OFF).......................14
2.6.2.3 PROM8 Configuration (SW37.7 is ON)...........................14
2.6.2.4 PROM Expansion ...........................................................15
2.6.3 RAM Overview..................................................................................15
2.6.3.1 SRAM Configuration.......................................................15
2.6.3.2 SDRAM Configuration.....................................................16
2.7 Board HMI.......................................................................................................17
2.7.1 Board press buttons..........................................................................17
2.7.2 Board LEDs ......................................................................................17
2.7.3 Board display....................................................................................18
2.8 UART interface................................................................................................18
2.8.1 Serial link 1.......................................................................................18
2.8.2 Serial link 2.......................................................................................19
2.9 PCI interface ...................................................................................................19
2.10 Clock management.........................................................................................20
2.10.1 Clock overview..................................................................................20
2.10.2 Internal clocks...................................................................................21
2.10.3 External clocks..................................................................................21
2.10.4 Processor clock configuration...........................................................21
2.11 Evaluation Kit Reset........................................................................................22
2.11.1 Hardware reset .................................................................................22
2.11.2 Alternate reset ..................................................................................22
2.11.3 Supply voltage supervisor.................................................................22
2.11.4 Space Programmer (SPP) reset.......................................................23
2.11.5 Watchdog reset.................................................................................23
2.12 Debug Support Unit.........................................................................................23
2.13 JTAG connector..............................................................................................24
2.14 Test Points......................................................................................................24
2.14.1 Current measurement test points......................................................24
2.14.2 Clocks test points..............................................................................25
2.14.3 System and CPCI test points............................................................26
2.15 Expansion connector.......................................................................................27
2.16 Mechanical drawing ........................................................................................29
2.17 Board History ..................................................................................................30
3. Appendix A –Getting Started...........................................................31
3.1 AT697 Development Kit Content.....................................................................31
3.2 Handling..........................................................................................................32
3.3 System requirements......................................................................................32

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3.4 Installing software development package .......................................................32
3.5 Hardware setup...............................................................................................33
3.5.1 Default switches configuration:.........................................................33
3.5.2 Power supply setup:..........................................................................33
3.5.3 Serial communication link:................................................................33
3.5.4 GRMON:...........................................................................................33
3.6 Run your first application.................................................................................34
4. Appendix B –Schematics ................................................................38
5. Revision History...............................................................................38

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1. Overview
Figure 1-1 AT697 Evaluation board v3.0
.
1.1 Scope
The AT697F eveluation kit aims at protoyping easly applications running on an AT697F processor.
This guide focuses on the description of the AT697F evlaluation kit.
1.2 Deliverables
The AT697F evaluation kit package contains the following items:
1x AT697F Evaluation kit Rev 3.0
1x AT697F processor in MQFP256 package
1x Power supply cable with 2.1mm Jack connector
2x RS232 cables
1 CD Rom

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1.3 Features
Here is an overview of the main operational features embedded on the evaluation board:
Table 1-1. AT697F V3.0 board features
Characteristics
Specifications
MCU
AT697F, powered in 3.3V and 1.8V
Board Power Supply
Audio jack connector (3.5mm)
3x Terminal blocks (direct 5V, 3.3V and 1.8V)
Compact-PCI powering
Clocks generator
25MHz clock generator –100MHz with PLL
33MHz PCI
Connector
1x RS232
1x Clock Configuration Manager (SPP)
2x SMB Clock input
1x JTAG
1x RS232 Debug Interface
2x Expansion Connectors
1x Compact-PCI
1x SMB Analog input
2x Expansion connector
Memory
8 Mbits flash / 32-bits wide (40-bits capability)
8 Mbits flash / 8-bits wide
16 Mbits SRAM / 32-bits wide (40-bits capability)
256 Mbits SDRAM / 32-bits wide (40-bits capability)
User Interface to AT697F
1x RESET button
5x push buttons
3x LED
1x LCD display
1x DSU break button
1x DSU LED activity
1x Potentiometer
1x Temperature sensor
2x Current measurement

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2. Hardware description
2.1 Block diagram
Figure 2-1 AT697F Evaluation board block diagram
AT697F
Interger Unit
(SPARC V8) I-Cache
D-Cache
FPU
Memory
controller
Flash
40 bits
SRAM 40 bits
SDRAM
Buffer
JTAG
DSU
SPP
Connector
Interrupt
Controller
Watchdog
Timers
RS232 serial link
PIO LEDs
Push Buttons
Clock
generator
RS232 serial link
JTAG Connector
Clock
PLL configuration
PCI
AMBA
Controller
AMBA
bridge
PCI/AMBA
bridge
DSUACT LED
DSUBRE Button
PCI interface
LCD Display
Current
measurement
Flash 8
bits
AIN Connector
Potentiometer
Temperature
Sensor
ADC
RS232
Reset control Reset
Reset configuration
Regulators
Alternate reset
Flash
conf
EDAC configuration
Clock
configuration
CLK EXT 1 connector
Reset button
UART Clock
configuration CLK EXT 2
connector
SKEW 1 configuration
SKEW 0 configuration
Expansion connectors
ALIM EXT
Direct 1V8
Direct 3V3
Direct 5V
1V8 Reg / Ext
3V3 Reg / Ext
5V Reg / Ext
Legend:
Switch Connector

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2.2 Evaluation board
Figure 2-2 Evaluation board overview
1V8 direct power
3V3 direct power
5V direct power
EXT power 8-12V
1V8 source selection
3V3 source selection
5V source selection
Power
Supply
CPCI
Connector
HMI Buttons
HMI LEDs
Configuration
switches
LCD 240x320
SRAM
SDRAM
Buffers
Clocks generator
Expansion
connector
Expansion
connector
DSU
interface

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Figure 2-3. Front panel overview
2.3 Manufacturing configuration
The Evaluation kit embeds a DIP switch allowing the user to configure several parameters. During this application note,
the switch is named SW37 and the switch number of the device is named with a “.x”. The following array describes the
initial configuration:
Figure 2-4. Configuration switches
Table 2-1 Initial configuration state
Name
Initial state
Function
SW37.1
OFF
Actives EDAC
SW37.2
ON
Actives the Bypass (thus disable the PLL)
SW37.3
OFF
SKEW 0 configuration
SW37.4
OFF
SKEW 1 configuration
SW37.5
OFF
Connect the processor watchdog to the RESET device
SW37.6
OFF
Select the processor clock.
SW37.7
OFF
This switch will select the PROM width.
SW37.8
OFF
Select PIO3 signal.
SW37.9
OFF
N.C.
SW37.10
OFF
N.C.
Processor
state
Power supply
state
ADC Ch 1
(Unused)
JTAG
Connector
Reset
Button
UART 1
DSU
Connector
SPP
Connector
Processor
Ext clock
UART
Ext clock

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2.4 Board power supply
With the default configuration, the AT697 board shall be powered from the 2.1mm Jack connector with a 8V up to 12V
power supply source. A power supply source capable to deliver up to 10W shall be used (10W figure can be achieved
when daughter boards are connected to the expansion connectors).
It is strongly recommended that the power supply is current limited in order to prevent damage to the board or power
supply in case of over-current.
Evaluation board can be powered through different ways:
Figure 2-5 Power supply diagram
When PCI is used, 3V3 regulator and 5V regulator are automatically shut down to avoid conflict with CPCI power
supplies.
Important: when the board is powered from the CPCI connector, switch for 3.3V and 5V shall be placed in “ext
position” whereas switch 1.8V shall be keep in “reg position”. Do not connect any power supply except the one
coming from CPCI connector.

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2.5 Processor
2.5.1 Processor Package
On the evaluation kit, the AT697 32-bit SPARC processor is embedded. The processor package is the MQFP-256
space qualified package.
Figure 2-6 MQFP-256 package
2.5.2 Processor Pin-out

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2.6 Memories
The AT697 Evaluation kit implements a full set of memories representative of the processor memory controller
capability. All three memories areas available are implemented, including PROM, SRAM and SDRAM memories.
2.6.1 Memory organization overview
To able the usage of AT697F processor with SDRAM memories at 100 MHz, a set of buffer is implemented to isolate
this kind of memory.
Logic glue set the buffer to “write” direction when SDRAM is used to avoid interferences with others memories.
Figure 2-7 Memory organization
Flash 40 bits
SRAM 40 bits
SDRAM 40 bits
Buffer
Flash 8 bits
AT697F
Logic to configure
buffer operation
Legend:
Fast memory
Slow memory
Flash
configuration
Switch
2.6.2 PROM (or Flash)
2.6.2.1 PROM Overview
The AT697F is able to work with two bus widths: 8 bits or 32 bits. In both cases, the processor can use the EDAC
mode. If EDAC is enabled on the PROM 40, the processor needs 8 more bits.
The evaluation kit is delivered with 8 Mbit flash - 32-bits wide (40-bits capability).
The ROM default configuration at delivery time is 32-bit mode (EDAC off).
The Flash memories can be programmed using the DSU interface.
To keep the same quantity of memory with or without the EDAC, the evaluation board embeds 3x 16bits flash
memories: 2 chips are for data and 1 is for the EDAC capability. The following array summarizes the different cases.

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Table 2-2 PROM code sizes
ROM bus width
EDAC
Code size
8 bits
Disabled
8 Mbits x1 –8 Mbits available
8 bits (add a 5th bit for EDAC)
Enabled
8 Mbits x1 –6.55 Mbits available
32 bits
Disabled
8 Mbits x2 –16 Mbits available
40 bits (32 bits data + 8 bits EDAC)
Enabled
8 Mbits x3 –16 Mbits available
IMPORTANT: until now, PROM8 is not recognized by GRMON.
The AT697 PROM bus width is configured at reset time according to PIO[1:0] value. Under reset the processor samples
PIO[1:0] and reports its value to the memory configuration register.
2.6.2.2 PROM40 Configuration (SW37.7 is OFF)
The 40-bit boot PROM is based on three M29W800D Flash memories (U19, U20 and U21). These chips are directly
soldered on the board. PROM 40 is implemented on the bottom side of the board as shows the following picture:
Figure 2-8. PROM40 implementation
In order to use the 40-bit mode, the following configuration shall be respected: SW37.7 is OFF.
2.6.2.3 PROM8 Configuration (SW37.7 is ON)
The 8-bit boot PROM is based on three M29W800D Flash memories (U22). The chip is directly soldered on the board.
PROM8 is implemented on the bottom side of the board close to the PROM40.
IMPORTANT: when EDAC is activated with PROM8, memory available is less than without EDAC.

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2.6.2.4 PROM Expansion
The AT697 processor can control up to 256Mbytes of PROM. The evaluation board can handle up to 2M bytes of
PROM code. For applications that need more PROM capacity, it is possible to extend the total PROM capacity by
connecting a daughter board to the expansion connectors.
All PROM control signals are provided on these expansion connectors.
Please refer to the ““Expansion Connectors - section 2.15” for details on signal assignment.
2.6.3 RAM Overview
The evaluation kit allows the user to work with SRAM and SDRAM.
2.6.3.1 SRAM Configuration
The evaluation kit implements one bank of SRAM which starts at memory address 0x40000000. There are 2
components for this function:
1x SRAM 32 bits for the data/code: AT68166F-YS18-E (U35)
1x SRAM 8 bits for the checkbit (EDAC protection): AT60142H-DS15M-E (U36)
This provides an access to 16MBits of SRAM data/code.
Because of an inversion of write enable signals WE[3:0], the processor can’t use SRAM in 8 bits mode without a patch.
Since V3.0.2 a modification has been is done to allow the processor the use SRAM in 8 bits mode. Following picture
illustrate the fixe in the schematic (p36):
Figure 2-9. SRAM 40 implementation
1
2
1: SRAM 32bits for data
2: SRAM 8 bits for EDAC

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2.6.3.2 SDRAM Configuration
The evaluation kit implements one bank of SDRAM which starts at memory address 0x60000000. There are 2
components for this function:
2x SDRAM 16 bits for the data/code: MT48LC16M16A2P-6A (U25, U26)
1x SDRAM 16 bits (only 8 bits are used) for the checkbit (EDAC protection): MT48LC16M16A2P-6A (U27)
This provides an access to 256MBits of SDRAM data/code
Figure 2-10. SDRAM implementation
Bottom side
Top side
2
1: SDRAM for data
2: SDRAM for EDAC
1

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2.7 Board HMI
The user can interact with the board through 5 press buttons, 3 LEDs and 1 LCD display.
2.7.1 Board press buttons
Press buttons are all pulled up to 3.3V with a 4.7KΩ resistor.
Figure 2-9. Press button implantation
Table 2-3 Press buttons mapping
Name
Function
Processor connexion
HMI_PB1
Press button left
PIO 13
HMI_PB2
Press button right
PIO 12
HMI_PB3
Press button up
PIO 10
HMI_PB4
Press button down
PIO 11
HMI_PB5(1)
Press button enter(1)
PIO 3
(1): To use this function, SW37.8 must be OFF.
2.7.2 Board LEDs
LEDs are driven by a NPN transistor. A hight level on a PIO put the LED on.
Figure 2-13. LEDs implantation
Table 2-4 LEDs mapping

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Name
Function
Processor connexion
HMI_LED0
LED0
PIO 0
HMI_LED1
LED1
PIO 1
HMI_LED2
LED2
PIO 2
2.7.3 Board display
The LCD display reference is: ET024011DHU. It is connected to the processor in serial mode (BS0 = 0 and BS1 = 1).
Parallel mode and tactil wires are accessible only thourgh the expension connector.
Table 2-5 Display mapping
Name
Function
Processor connexion
HMI_LCD_SDA
Display serial data
PIO 5
HMI_LCD_NWR_SCL
Display serial clock
PIO 6
HMI_LCD_CS
Display chip select
PIO 9
2.8 UART interface
The AT697 evaluation board includes all the required hardware to manage a RS232 communication. Hardware flow
control (CTS & RTS) are not implemented on this Evaluation Kit.
2.8.1 Serial link 1
Serial link 1 is available on the board through the connector UART 1 accessible on the front panel (see Figure 2-3.
Front panel overview).
Table 2-6 UART 1 mapping
Serial link name
Function
Processor connexion
UART1_RX
Serial link receive data
PIO 14
UART1_TX
Serial link transmit data
PIO 15
UART1_RTS
Request to Send frame
N.C.
UART1_CTS
Clear to Send frame
N.C.

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2.8.2 Serial link 2
Serial link 2 is available through the expansion connector only and is only 3.3V tolerant. If serial link 2 is connected to a
RS232 interface on an expansion board, a line driver (like MAX3232) has to be implemented to adapt voltage.
2.9 PCI interface
The AT697 evaluation board implements a PCI interface capable to manage host and satellite configuration.
The PCI interface has been designed to be integrated in compact PCI back plane. Universal keying is implemented.
The board form factor fits with the 6U standard.
The HOST/SATELLITE mode is automatically configured through position of the board on the PCI rack.
.

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2.10 Clock management
2.10.1 Clock overview
Figure 2-14. AT697F Clock distribution
Figure 2-15. Development kit clock management
SPP Connector RS232 serial link
connector
Clock
generator
PLL configuration
AT697F
Clock
configuration
CLK EXT 1
connector
UART Clock
configuration CLK EXT 2
connector
Legend:
Configuration switch Connector
Clock
interface
PCI
interface
SKEW 1 configuration
SKEW 0 configuration
UART
interface
PIO
interface
UART Control Reg.
UACn
PB Enter
25 MHz
33 MHz