Cmsemicon Cms32h6157 User manual

CMS32H6157 User Manual

Ultra-low-power 32-bit measurement SOC based on the ARM® Cortex®-M0+

Rev. 0.1.1

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Rev.0.1.1

CMS32H6157 User Manual | Chapter 1 CPU

www.mcu.com.cn 2 / 822

Document Instructions

This manual is the user manual for the CMS32H6157 microcontroller product. The user manual is the application

instruction material on how to use this series of products, including the structure, function description, working mode

and register configuration of each functional module. Each function module is introduced in a special section.

The user manual is a description of all functional modules of this series of products. If you want to know the

feature description of the specific product (that is, the functional configuration), you can refer to the respective data

sheet.

The data sheet information is as follows::

CMS32H6157datasheet_vx.x.x pdf

Usually in the early stage of chip selection, you shall first check the data sheet to evaluate whether the product

can meet the functional requirements of the design. After basically selecting the required product, you need to check

the user manual to determine whether the working mode of each functional module does meet the requirement. When

determining the selection and entering the programming design stage, you need to read the user manual in detail to

understand the specific implementation and register configuration of each function. Refer to the datasheet for

information on voltages, currents, drive capabilities and pin assignments when designing the hardware.

For a detailed description of the ARM M0+ core, SysTick timer and NVIC, please refer to the respective ARM

documents.

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Contents 
Document Instructions........................................................................................................................................2 
 CPU................................................................................................................19 
 Overview .......................................................................................................................................19 
 Cortex-M0+ core features.............................................................................................................19 
 Debugging features.......................................................................................................................19 
 SWD interface pins .......................................................................................................................21 
 ARM reference document.............................................................................................................22 
 PORT FUNCTION..........................................................................................23
 Port general function.....................................................................................................................23 
 Port multiplexing function..............................................................................................................24 
 Registers for controlling port functions .........................................................................................27 
 Port output control register (PMxx)........................................................................................29 
 Port register (Pxx)..................................................................................................................30 
 Port set control register (PSETxx).........................................................................................31 
 Port clear control register (PCLRxx)......................................................................................32 
 Pull-up resistor selection register (PUxx) ..............................................................................33 
 Pull-down resistor selection register (PDxx)..........................................................................34 
 Port output mode register (POMxx).......................................................................................35 
 Port mode control register (PMCxx)......................................................................................36 
 Port readback register (PREADxx)........................................................................................37 
 Port multiplexing function configuration register (PxxCFG) ..................................................38 
 External interrupt port selection register (INTPnPCFG)........................................................41 
 External reset port mask register (RSTM).............................................................................44 
 Handling of unused ports..............................................................................................................45 
 Register settings when using the multiplexing function................................................................46 
Basic ideas when using multiplexing functions ...................................................................................46 
 SYSTEM STRUCTURE .................................................................................65
 Overview .......................................................................................................................................65 
 System address division...............................................................................................................66 
 Peripheral address assignment....................................................................................................67 
 CLOCK GENERATION CIRCUIT..................................................................68 
 Function of clock generation circuit ..............................................................................................68 
 Structure of clock generation circuit..............................................................................................70 
 Registers for controlling clock generation circuit..........................................................................73 
 Clock operation mode control register (CMC).......................................................................73 
 System clock control register (CKC)......................................................................................75 
 Clock operation status control register (CSC).......................................................................76 
 Status register of the oscillation stabilization time counter (OSTC)......................................78 

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 Oscillation stabilization time selection register (OSTS).........................................................80 
 Peripheral enabled registers 0, 1 (PER0, PER1)..................................................................82 
 Subsystem clock supply mode control register (OSMC).......................................................85 
 High-speed internal oscillator frequency selection register (HOCODIV) ..............................86 
 High-speed internal oscillator trim register (HIOTRM) ..........................................................87 
 Subsystem clock selection register (SUBCKSEL).................................................................88 
 System clock oscillation circuit......................................................................................................89 
 X1 oscillation circuit ...............................................................................................................89 
 XT1 oscillation circuit.............................................................................................................90 
 High-speed internal oscillator ................................................................................................93 
 Low-speed internal oscillator.................................................................................................93 
 Operation of clock generation circuit ............................................................................................94 
 Clock control .................................................................................................................................96 
 Example of setting up a high-speed internal oscillator..........................................................96 
 Example of setting X1 oscillation circuit ................................................................................98 
 Example of setting XT1 oscillation circuit..............................................................................99 
 CPU clock state transition diagram......................................................................................100 
 Conditions before CPU clock transfer and post-transfer processing..................................106 
 Time required to switch CPU clock and main system clock................................................108 
 Conditions before clock oscillation stops.............................................................................109 
 High-speed internal oscillation correction...................................................................................110 
 High-speed internal oscillation self-adjustment function .....................................................110 
 Register description.............................................................................................................111 
 High-speed internal oscillation frequency correction control register (HOCOFC)...........111 
 Action description.................................................................................................................113 
 Action summary................................................................................................................113 
 Action setting flow............................................................................................................116 
 Notes on use........................................................................................................................117 
 SFR Access......................................................................................................................117 
 Actions on resetting..........................................................................................................117 
 Oscillation stop detection circuit .................................................................................................118 
 Composition of the oscillation-stop detection circuit............................................................118 
 The registers used by the oscillation-stop detection circuit.................................................119 
 Peripheral enabled Register 1(PER1) .............................................................................119 
 Oscillation stop detection control register (SCMCTL)......................................................119 
 Oscillation stop detection mode register (SCMMD).........................................................120 
 Oscillation stop detection status register (SCMST).........................................................120 
 Operation of oscillation stop detection circuit......................................................................121 
 Operation method of oscillation stop detection circuit.....................................................121 

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 Operation of oscillation stop detection circuit in deep sleep mode.....................................122 
 Notes on the oscillation stop detection function ..................................................................122 
 GENERAL-PURPOSE TIMER UNIT TIMER8 .............................................123 
 General-purpose timer unit functions..........................................................................................125 
 Independent channel operation functions............................................................................125 
 Multi-channel linkage operation functions ...........................................................................127 
 LIN-bus support function (channel 3 only)...........................................................................129 
 Structure of the general-purpose timer unit................................................................................130 
 General-purpose timer unit register list ...............................................................................132 
 Timer count register mn (TCRmn).......................................................................................133 
 Timer data register mn (TDRmn).........................................................................................135 
 Registers that control the general-purpose timer unit ................................................................136 
 Peripheral enable register 0(PER0).....................................................................................137 
 Timer clock selection register m (TPSm).............................................................................138 
 Timer mode register mn (TMRmn) ......................................................................................141 
 Timer status register mn (TSRmn)......................................................................................145 
 Timer channel enable status register m (TEm) ...................................................................146 
 Timer channel start register m (TSm)..................................................................................147 
 Timer channel stop register m (TPSm)................................................................................148 
 Timer input output selection register (TIOS0)......................................................................149 
 Timer output enable register m (TOEm)..............................................................................150 
 Timer output register m (TOm)............................................................................................151 
 Timer output level register m (TOLm)..................................................................................152 
 Timer output mode register m (TOMm)...............................................................................153 
 Input switching control register (ISC)...................................................................................154 
 Noise filter enable register (NFEN1)....................................................................................155 
 Registers for controlling timer input/output pin port functions.............................................156 
 Basic rules of the general-purpose timer unit.............................................................................157 
 Basic rules of multi-channel linkage operation function......................................................157 
 Timer channel start register m (TSm)..................................................................................160 
 Operation of counters .................................................................................................................161 
 Counting clock (FTCLK)..........................................................................................................161 
 Start timing of counter..........................................................................................................163 
 Operation of counters ..........................................................................................................164 
 Control of channel outputs (TOmn pins).....................................................................................169 
 Block diagram of the TOmn pin output circuit......................................................................169 
 Settings of the TOmn pin output..........................................................................................170 
 Cautions for channel output operation.................................................................................171 
 One-time operation of TOmn bit..........................................................................................176 

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 Timer interrupt and TOmn pin output when counting starts................................................177 
 Control of Timer Input (TImn)......................................................................................................178 
 Block diagram of the TImn pin input circuit..........................................................................178 
 Noise filter............................................................................................................................178 
 Cautions for channel input operation...................................................................................179 
 Independent channel operation function for general purpose timer units..................................180 
 Operation as interval timer/square wave output..................................................................180 
 Operation as external event counter....................................................................................184 
 Operation as frequency divider............................................................................................187 
 Operation as input pulse interval measurement..................................................................190 
 Operation as input signal high and low level width measurement......................................194 
 Operation as delay counter..................................................................................................198 
 Multi-channel linkage operation function for general purpose timer units..................................201 
 Operation as single trigger pulse output function................................................................201 
 Operation as PWM function.................................................................................................208 
 Operation as multiple PWM output function........................................................................215 
 Cautions when using the general-purpose timer unit.................................................................224 
 Cautions when using timer output .......................................................................................224 
 TIMERA .......................................................................................................225 
 TimerA function...........................................................................................................................225 
 Structure of Timer A....................................................................................................................226 
 Registers for controlling Timer A.................................................................................................227 
 Peripheral enable register 0(PER0).....................................................................................228 
 Subsystem Clock Supply Mode Control Register (OSMC) .................................................229 
 Timer A count register 0 (TA0) ............................................................................................230 
 Timer A control register 0 (TACR0).....................................................................................231 
 Timer AI/O control register 0 (TAIOC0)...............................................................................232 
 Timer A control register 0 (TAMR0).....................................................................................234 
 Timer A event pin selection register 0 (TAISR0).................................................................235 
 Timer A operation........................................................................................................................236 
 Rewriting the reload register and counter............................................................................236 
 Timer mode..........................................................................................................................237 
 Pulse output mode...............................................................................................................238 
 Event counter mode.............................................................................................................239 
 Pulse width measurement mode .........................................................................................241 
 Pulse period measurement mode........................................................................................242 
 Collaboration with EVENTC.................................................................................................243 
 Output settings for each mode.............................................................................................244 
 Cautions when using timer A......................................................................................................245 

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 Start and stop control of counting........................................................................................245 
 Flag access (TEDGF bit and TUNDF bit of TACR0 register)..............................................245 
 Access to counting registers................................................................................................246 
 Change in mode...................................................................................................................246 
 Setting procedure for TAO pin and TAIO pin.......................................................................246 
 When timer A is not used.....................................................................................................247 
 Stop of timer A operation clock............................................................................................247 
 Setting steps for deep sleep mode (event counter mode)...................................................247 
 Function limitations in deep sleep mode (event counter mode only)..................................248 
 Forced count stop via the TSTOP bit...................................................................................248 
 Digital Filters ........................................................................................................................248 
 Selecting FIL as the count source........................................................................................249 
 REAL TIME CLOCK....................................................................................250 
 Functions of real-time clock........................................................................................................250 
 Structure of real-time clock.........................................................................................................250 
 Registers for controlling real-time clock......................................................................................252 
 Peripheral enable register 0 (PER0)....................................................................................253 
 Real-time clock selection register (RTCCL) ........................................................................254 
 Real-time clock control register 0 (RTCC0).........................................................................255 
 Real-time clock control register 1 (RTCC1).........................................................................256 
 Watch error correction register (SUBCUD) .........................................................................258 
 Second count register (SEC)...............................................................................................259 
 Minute count register (MIN).................................................................................................260 
 Hour count register (HOUR)................................................................................................261 
 Day count register (DAY).....................................................................................................263 
 Week count register (WEEK)...............................................................................................264 
 Month count register (MONTH) ...........................................................................................265 
 Year count register (YEAR).................................................................................................266 
 Alarm minute register (ALARMWM) ....................................................................................267 
 Alarm hour register (ALARMWH) ........................................................................................268 
 Alarm week register (ALARMWW) ......................................................................................269 
 Starting operation of real-time clock....................................................................................270 
 Shifting to sleep mode after starting operation....................................................................271 
 Reading/writing real-time clock............................................................................................272 
 Setting alarm of real-time clock ...........................................................................................274 
 1 Hz output of real-time clock..............................................................................................275 
 Example of watch error correction of real-time clock ..........................................................276 
 15-BIT INTERVAL TIMER ...........................................................................278 
 Functions of 15-bit Interval Timer...............................................................................................278 

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 Structure of 15-bit Interval Timer................................................................................................278 
 Registers controlling 15-bit Interval Timer..................................................................................279 
 Peripheral enable register 0 (PER0)....................................................................................279 
 Real-time clock selection register (RTCCL) ........................................................................280 
 15-bit interval timer control register (ITMC).........................................................................281 
 15-bit interval timer operation .....................................................................................................282 
 15-bit interval timer operation timing....................................................................................282 
 Start of count operation and re-enter to sleep mode after returned from sleep mode........283 
 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER................................284
 Functions of clock output/buzzer output controller.....................................................................284 
 Registers for controlling clock output/buzzer output controller...................................................286 
 Clock output select registers n (CKSn)................................................................................286 
 Operations of clock output/buzzer output controller...................................................................288 
 Cautions of clock output/buzzer output controller.......................................................................288 
 WATCH DOG TIMER...................................................................................289
 Functions of watchdog timer.......................................................................................................289 
 Structure of watch dog timer.......................................................................................................289 
 Registers for controlling watchdog timer.....................................................................................291 
 Watchdog timer enable register (WDTE).............................................................................291 
 LOCKUP control register (LOCKCTL)and its protection register(PRCR) ...........................292 
 WDTCFG configuration registers (WDTCFG0/1/2/3)..........................................................293 
 Operation of watchdog timer.......................................................................................................294 
 Operational control of watchdog timer.................................................................................294 
 Setting overflow time of watchdog timer..............................................................................296 
 Setting window open period of watchdog timer...................................................................297 
 Setting watchdog timer interval interrupt.............................................................................298 
 Operation of the watchdog timer during LOCKUP...........................................................298 
 Operation of the watchdog timer without WDTCFG configured......................................298 
 AD CONVERTER.........................................................................................299 
 Function of A/D converter...........................................................................................................299 
 Registers for controlling A/D converter.......................................................................................301 
 Peripheral enable register (PER1).......................................................................................302
 A/D converter mode register 0 (ADM0)...............................................................................303 
 A/D converter mode register 1 (ADM1)...............................................................................304 
 A/D converter mode register 2 (ADM2)...............................................................................305 
 A/D converter trigger mode register (ADTRG)....................................................................306 
 Analog input channel specification register (ADS)..............................................................307 
 12-bit A/D conversion result register (ADCR)......................................................................310 
 8-bit A/D conversion result register (ADCRH).....................................................................311 

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 Conversion result comparison upper limit setting register (ADUL).....................................311 
 Conversion result comparison lower limit setting register (ADLL)...................................312 
 A/D converter sampling time control register (ADNSMP)................................................313 
 A/D converter sampling time extension control register (ADSMPWAIT).........................315 
 A/D test register (ADTES)................................................................................................316 
 A/D converters charge-discharge control register (ADNDIS)..........................................317 
 Input voltage and conversion result............................................................................................318 
 Operation mode of A/D converter...............................................................................................319 
 Software trigger mode (select mode, sequential conversion mode)...................................319 
 Software trigger mode (select mode, single conversion mode)..........................................320 
 Software trigger mode (scan mode, sequential conversion mode).....................................321 
 Software trigger mode (scan mode, single conversion mode)............................................322 
 Hardware trigger no-wait mode (select mode, sequential conversion mode).....................323 
 Hardware trigger no-wait mode (select mode, single conversion mode)............................324 
 Hardware trigger no-wait mode (scan mode, sequential conversion mode).......................325 
 Hardware trigger no-wait mode (scan mode, single conversion mode)..............................326 
 Hardware trigger wait mode (select mode, sequential conversion mode)..........................327 
 Hardware trigger wait mode (select mode, single conversion mode) .............................328 
 Hardware trigger wait mode (scan mode, sequential conversion mode)........................329 
 Hardware trigger wait mode (scan mode, single conversion mode) ...............................330 
 A/D converter setup flowchart.....................................................................................................331 
 Setting up software trigger mode.........................................................................................331 
 Setting up hardware trigger no-wait mode...........................................................................332 
 Setting up hardware trigger wait mode................................................................................333 
 Setup when temperature sensor output voltage/internal reference voltage is selected .....334 
 Setting up test mode............................................................................................................335 
 SIGMA-DELTA ADC....................................................................................336
 Overview .....................................................................................................................................336 
 Description of basic functions.....................................................................................................336 
 Description of ADC working principle .........................................................................................337 
 LDO......................................................................................................................................337 
 Analog inputs .......................................................................................................................337 
 Temperature sensor.............................................................................................................337 
 Low noise programmable gain amplifier..............................................................................337 
 ADC clock, output data rate.................................................................................................338 
 Reset and sleep mode.........................................................................................................339 
 Setup time............................................................................................................................339 
 SPI Serial Interface.....................................................................................................................340 
 Digital output codes .............................................................................................................340 

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 Data ready/data input and output (DRDYB/DOUT).............................................................340 
 Serial input clock (SCLK).....................................................................................................340 
 Serial data transmission.......................................................................................................341 
 Function configuration..........................................................................................................342 
 Description of SPI opcode command..................................................................................343 
 Cautions for SPI Communication.........................................................................................343 
 Related registers.........................................................................................................................344 
 Sigma-Delta ADC control register 1.....................................................................................344 
 Sigma-Delta ADC control register 2.....................................................................................345 
 Sigma-Delta ADC control register 3.....................................................................................346 
 Sigma-Delta ADC control register 4.....................................................................................347 
 D/A CONVERTER........................................................................................348 
 Function of D/A converter...........................................................................................................348 
 Structure of D/A converter ..........................................................................................................349 
 Registers for controlling D/A converter.......................................................................................350 
 Peripheral enable register 1 (PER1)....................................................................................350 
 D/A converter mode register (DAM) ....................................................................................351 
 D/A conversion value setting register i (DACSi) (i=0) .........................................................351 
 Event output destination select register n (ELSELRn), n= 00~15.......................................351 
 Operation of D/A Converter ........................................................................................................352 
 Operation in Normal Mode...................................................................................................352 
 Operation in real-time output mode.....................................................................................353 
 D/A conversion output timing...............................................................................................354 
 Cautions for D/A Converter.........................................................................................................355 
 COMPARATOR...........................................................................................356 
 Function of comparator...............................................................................................................356 
 Structure of comparator..............................................................................................................357 
 Registers for controlling comparator...........................................................................................359 
 Peripheral enable register 1 (PER1)....................................................................................360 
 Comparator mode setting register (COMPMDR) ................................................................361 
 Comparator filter control register (COMPFIR).....................................................................362 
 Comparator output control register (COMPOCR) ...............................................................364 
 Comparator negative reference selection register (CnREFS).............................................366 
 Comparator positive input selection register (CMPSELn)...................................................367 
 Comparator hysteresis control register (CMPnHY).............................................................368 
 Operation.....................................................................................................................................369 
 Digital filter of comparator n (n=0, 1) ...................................................................................371 
 Comparator n interrupt (n=0, 1)...........................................................................................371 
 Event signal output to the coordination controller (EVENTC).............................................372 

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 Output of comparator n (n=0, 1)..........................................................................................373 
 Stopping or Supplying comparator clock.............................................................................374 
 OPERATIONAL AMPLIFIER (OPA)............................................................375
 Function of operational amplifier.................................................................................................375 
 Register of operational amplifier.................................................................................................376 
 Peripheral enable register 1 (PER1)....................................................................................376 
 Operational amplifier control register (OPACTL).................................................................377 
 Operational amplifier digital-to-analog control register (OPADAC).....................................378 
 GENERAL-PURPOSE SERIAL COMMUNICATION UNIT .........................379 
 Function of general-purpose serial communication unit.............................................................380 
 3-wire serial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20, SSPI21)............................380 
 UART (UART0~UART2)......................................................................................................381 
 Simplified I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21)......................................................382 
 Structure of general-purpose serial communication unit............................................................383 
 Shift register.........................................................................................................................385 
 Serial data register mn (SDRmn).........................................................................................385 
 Registers for controlling general-purpose serial communication unit.........................................387 
 Peripheral enable register 0 (PER0)....................................................................................389 
 Serial clock selection register m (SPSm) ............................................................................390 
 Serial mode register mn (SMRmn)......................................................................................391 
 Serial communication run setting register mn (SCRmn).....................................................393 
 Serial data register mn (SDRmn).........................................................................................396 
 Serial flag clear trigger register mn(SIRmn)........................................................................397 
 Serial status register mn (SSRmn)......................................................................................398 
 Serial channel start register m(SSm)...................................................................................400 
 Serial channel stop register m(STm)...................................................................................401 
 Serial channel enable status register m (SEm) ...............................................................402 
 Serial output enable register m (SOEm)..........................................................................403 
 Serial output register m (SOm)........................................................................................404 
 Serial output level register m (SOLm)..............................................................................405 
 Serial standby control register m (SSCm) .......................................................................406 
 Slave select function enable register m (SSEm) .............................................................407 
 Input switching control register (ISC)...............................................................................408 
 Noise filter enable register 0 (NFEN0).............................................................................409 
 Operation stop mode...................................................................................................................410 
 Stopping the operation by units...........................................................................................410 
 Stopping the operation by channels....................................................................................411 
 3-wire serial I/O(SSPI00, SSPI01, SSPI10, SSPI11, SSPI20, SSPI21) communication...........412 
 Master transmission.............................................................................................................413 

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 Master reception ..................................................................................................................421 
 Master transmission and reception......................................................................................429 
 Slave transmission...............................................................................................................437 
 Slave reception ....................................................................................................................445 
 Slave transmission and reception........................................................................................451 
 Calculation of transmission clock frequency........................................................................460 
 Procedureforhandling errorsduring3-wireserial I/Ocommunication(SSPI00,SSPI01,SSPI10, 
SSPI11, SSPI20, SSPI21).................................................................................................................462 
 Operation of clock-synchronous serial communication with slave selection input function.......463 
 Slave transmission...............................................................................................................466 
 Slave reception ....................................................................................................................476 
 Slave transmission and reception........................................................................................483 
 Calculation of transmission clock frequency........................................................................493 
 Procedure for handling errors during clock-synchronous serial communication with the slave 
selection input function ......................................................................................................................494 
 Operation of UART (UART0~UART2) communication...............................................................495 
 UART transmission..............................................................................................................496 
 UART reception....................................................................................................................504 
 Low-power UART mode function.........................................................................................511 
 Calculation of baud rate.......................................................................................................517 
 Handling steps when an error occurs during UART (UART0~UART2) communication.....521 
 Operation of LIN communication................................................................................................522 
 LIN transmission..................................................................................................................522 
 LIN reception........................................................................................................................525 
 Operation of simple I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21) communication....................530 
 Address segment sending ...................................................................................................531 
 Data transmission................................................................................................................536 
 Data reception......................................................................................................................539 
 Generation of stop condition................................................................................................543 
 Calculation of transfer rate...................................................................................................544 
 Processing steps when anerror occurs in a simple I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21) 
communication process.....................................................................................................................546 
 SERIAL INTERFACE SPI............................................................................547
 Function of SPI............................................................................................................................547 
 Structure of SPI...........................................................................................................................547 
 Registers for controlling SPI .......................................................................................................548 
 Peripheral enable register 1 (PER1)....................................................................................548 
 SPI operating mode register (SPIM)....................................................................................549 
 SPI clock selection register (SPIC)......................................................................................550 
 SPI status register (SPIS)....................................................................................................551 

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 Transmit buffer register (SOTB) ..........................................................................................552 
 Receive buffer register (SIO)...............................................................................................552 
 Operation of SPI..........................................................................................................................553 
 Master tramission and reception..........................................................................................554 
 Master reception ..................................................................................................................557 
 Slave transmission and reception........................................................................................560 
 Slave reception ....................................................................................................................563 
 SERIAL INTERFACE IICA ..........................................................................566
 Function of IICA ..........................................................................................................................566 
 Run stop mode.....................................................................................................................566 
 I2C-bus mode (supports multi-master).................................................................................566 
 Wake-up mode.....................................................................................................................566 
 Structure of IICA..........................................................................................................................569 
 IICA shift register n (IICAn)..................................................................................................570 
 Slave address register n(SVAn) ..........................................................................................570 
 SO latch ...............................................................................................................................570 
 Wake-up control circuitry .....................................................................................................571 
 Serial clock counter..............................................................................................................571 
 Interrupt request signal generation circuit ...........................................................................571 
 Serial clock control circuitry .................................................................................................571 
 Serial clock wait control circuit.............................................................................................571 
 Ack generation circuit, stop condition detection circuit, start condition detection circuit, Ack 
detection circuit..................................................................................................................................571 
 Data hold time correction circuit.......................................................................................571 
 Start conditional generation circuitry................................................................................571 
 Stop condition generation circuitry...................................................................................572 
 Bus status detection circuitry...........................................................................................572 
 Registers for controlling IICA......................................................................................................573 
 Peripheral enable register 0 (PER0)....................................................................................573 
 IICA control register n0 (IICCTLn0).....................................................................................574 
 IICA status register n(IICSn)................................................................................................578 
 IICA flag register n(IICFn)....................................................................................................581 
 IICA control register n1(IICCTLn1)......................................................................................583 
 IICA low-level width setting register n(IICWLn)...................................................................585 
 IICA high level width setting register n(IICWHn).................................................................585 
 Registers for controlling the IICA pin port function..............................................................586 
 Function of I2C-bus mode...........................................................................................................587 
 Pin structure.........................................................................................................................587 
 Setting the transmit clock via IICWLn register and IICWHn register...................................588 
 Definition and control method of I2C-bus....................................................................................590 

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 Start condition......................................................................................................................591 
 Address................................................................................................................................592 
 Designation of transmission direction..................................................................................592 
 ACK......................................................................................................................................593 
 Stop Condition......................................................................................................................594 
 Await.....................................................................................................................................595 
 Method of release from wait state........................................................................................597 
 Generation timing and waiting control of interrupt requests (INTIICAn) .............................598 
 Detection method for address matching..............................................................................599 
 Error detection..................................................................................................................599 
 Extension code.................................................................................................................600 
 Arbitration.........................................................................................................................601 
 Wake-up function.............................................................................................................603 
 Communication appointment...........................................................................................606 
 Other cautions..................................................................................................................610 
 Communication operation................................................................................................611 
 Timing of I2C interrupt request (INTIICAn) generation ....................................................621 
 Timing diagram ...........................................................................................................................641 
 IRDA ............................................................................................................658
19.1 Function of IrDA..........................................................................................................................658 
19.2 Registers for controlling IrDA......................................................................................................659 
19.2.1 Peripheral enable register 0 (PER0)....................................................................................659 
19.2.2 IrDA control register (IRCR).................................................................................................660 
19.3 Operation of IrDA........................................................................................................................661 
19.3.1 Procedure for IrDA communication......................................................................................661 
19.3.2 Transmission........................................................................................................................662 
19.3.3 Reception.............................................................................................................................662 
19.3.4 Selection of high level pulse width.......................................................................................663 
19.4 Cautions when using IrDA ..........................................................................................................664 
 LCD CONTROLLER/DRIVER .....................................................................665 
20.1 Function of LCD controller / driver..............................................................................................665 
20.2 Structure of LCD controller / driver.............................................................................................666 
20.3 Registers for controlling LCD controller/driver............................................................................668 
20.3.1 LCD mode register 0(LCDM0).............................................................................................669 
20.3.2 LCD mode register 1(LCDM1).............................................................................................671 
20.3.3 Subsystem Clock Supply Mode Control Register (OSMC) .................................................673 
20.3.4 LCD clock control register 0 (LCDC0).................................................................................674 
20.3.5 LCD Boost Level Control Register (VLCD)..........................................................................675 
20.3.6 LCD input switching control register (ISCLCD) ...................................................................677 

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3.7 LCD port function register....................................................................................................678 
4 LCD display data register............................................................................................................679 
5 LCD display register selection ....................................................................................................681 
5.1 Data display in graphic area A and graphic area B.............................................................682 
5.2 Blinking display (alternate display of data in graph area A and graph area B)...................682 
6 LCD drive voltage provided by VL1, VL2, VL3, VL4 ........................................................................683 
6.1 Internal resistor splitting method..........................................................................................683 
6.2 External resistance splitting method....................................................................................684 
6.3 Internal boost method..........................................................................................................685 
6.4 Capacitance splitting method...............................................................................................686 
 ENHANCED DMA........................................................................................687
1 Function of DMA .........................................................................................................................687 
2 Structure of DMA.........................................................................................................................689 
3 Registers for controlling DMA.....................................................................................................690 
3.1 DMA control data areas and DMA vector table areas allocation.........................................691 
3.2 Control data allocation.........................................................................................................692 
3.3 Vector table..........................................................................................................................694
3.4 Peripheral enable register 1 (PER1)....................................................................................696 
3.5 DMA control register j(DMACRj)(j=0~23)............................................................................697 
3.6 DMA block size register j (DMBLSj)(j=0~23).......................................................................699 
3.7 DMA transmit count register j(DMACTj)(j=0~23).................................................................700 
3.8 DMA transfer count reload register j (DMRLDj)(j=0~23).....................................................701 
3.9 DMA source address register j(DMSARj)(j=0~23) ..............................................................702 
3.10 DMA destination address register j(DMDARj)(j=0~23)....................................................703 
3.11 DMA start enable register i (DMAENi)(i=0~2)..................................................................704 
3.12 DMA base address register (DMABAR) ..........................................................................706 
3.13 DMAENi set register i(DMSETi)(i=0~2)...........................................................................707 
3.14 DMAENi reset register i(DMCLRi)(i=0~2)........................................................................707 
4 Operation of DMA .......................................................................................................................708 
4.1 Startup Source.....................................................................................................................708 
4.2 Normal mode........................................................................................................................709 
4.3 Repeat pattern .....................................................................................................................712 
4.4 Chain transmission ..............................................................................................................715 
5 Cautions when using DMA..........................................................................................................717 
5.1 DMA control data and vector table settings.........................................................................717 
5.2 Allocation of DMA control data area and DMA vector table area........................................717 
5.3 Number of execution clocks for DMA ..................................................................................718 
5.4 Response time of DMA........................................................................................................719 
5.5 Startup source of DMA.........................................................................................................719 

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21.5.6 Operation in standby mode..................................................................................................720 
 LINKAGE CONTROLLER (EVENTC) .........................................................721 
 Function of EVENTC...................................................................................................................721 
 Structure of EVENTC..................................................................................................................721 
 Control register............................................................................................................................722 
 Output target selection register n(ELSELRn)(n=00~15) .....................................................723 
 Operation of EVENTC.................................................................................................................726 
 INTERRUPT FUNCTION.............................................................................728
23.1 Types of interrupt function ..........................................................................................................728 
23.2 Interrupt Sources and Structures................................................................................................728 
23.3 Registers for controlling interrupt function..................................................................................732 
23.3.1 Interrupt request flag register (IF00~IF31)...........................................................................732 
23.3.2 Interrupt mask flag register (MK00~MK31) .........................................................................733 
23.3.3 External interrupt rising edge enable register (EGP0), External interrupt falling edge enable 
register (EGN0)..................................................................................................................................735 
23.4 Operation of interrupt handling ...................................................................................................736 
23.4.1 Acceptance of maskable interrupt requests ........................................................................736 
23.4.2 Acceptance of non-maskable interrupt requests.................................................................736 
 KEY INTERRUPT FUNCTION.....................................................................737 
 Function of key interrupt .............................................................................................................737 
 Structure of key interrupt.............................................................................................................737 
 Register controlling key interrupts ..............................................................................................739 
 Key return mode register (KRM)..........................................................................................739 
 STANDBY FUNCTION ................................................................................740 
 Standby function .........................................................................................................................740 
 Sleep mode.................................................................................................................................741 
 Setting of sleep mode..........................................................................................................741 
 Release of sleep mode........................................................................................................745 
 Deep sleep mode........................................................................................................................746 
 Setting of deep sleep mode.................................................................................................746 
 Release of deep sleep mode...............................................................................................749 
 RESET FUNCTION......................................................................................750
 Reset timing................................................................................................................................752 
 Register for confirming the reset source.....................................................................................755 
 Reset control flag register (RESF).......................................................................................755 
 POWER-ON RESET CIRCUIT.....................................................................757
 Function of power-on reset circuit...............................................................................................757 
 Structure of power-on reset circuit..............................................................................................758 
 Operation of power-on reset circuit.............................................................................................759 

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 VOLTAGE DETECTION CIRCUIT...............................................................763 
 Function of voltage detection circuit ...........................................................................................763 
 Structure of voltage detection circuit...........................................................................................764 
 Registers for controlling voltage detection circuit.......................................................................765 
 Voltage detection register (LVIM)........................................................................................765 
 Voltage detection level register (LVIS)................................................................................766 
 Operation of voltage detection circuit .........................................................................................769 
 Settings when used in reset mode.......................................................................................769 
 Settings when used in interrupt mode.................................................................................770 
 Settings for interrupt & reset mode......................................................................................772 
 Cautions for voltage detection circuits........................................................................................779 
 SECURITY FEATURE .................................................................................781
 Overview .....................................................................................................................................781 
 Registers Used for Security Functions .......................................................................................782 
 Operation of security features.....................................................................................................783 
 Flash CRC operational function (high-speed CRC) ............................................................783 
 Flash CRC control register (CRC0CTL) ..........................................................................783 
 Flash CRC operation result register (PGCRCL)..............................................................784 
 CRC operation function (general-purpose CRC).................................................................786 
 CRC input register (CRCIN).............................................................................................787 
 CRC data register (CRCD) ..............................................................................................787 
 RAM parity error detection function.....................................................................................789 
 RAM parity error control register (RPECTL)....................................................................789 
 SFR protection function .......................................................................................................791 
 SFR protect control register(SFRGD)..............................................................................791 
 Frequency detection function...............................................................................................792 
 Timer input selection register0(TIS0)...............................................................................792 
 A/D test function...................................................................................................................793 
 A/D test register (ADTES)................................................................................................795 
 Analog input channel specification register (ADS)..........................................................795 
 Product Unique Identification Register ................................................................................796 
 TEMPERATURE SENSOR AND INTERNAL REFERENCE VOLTAGE....797 
 Temperature sensor....................................................................................................................797 
 Register for temperature sensor.................................................................................................798 
 Temperature sensor calibration data register TSN25 .........................................................798 
 Temperature sensor calibration data register TSN85 .........................................................798 
 Instructions for using the temperature sensor............................................................................799 
 How temperature sensors are used.....................................................................................799 
 How to use temperature sensor...........................................................................................800 

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 Internal reference voltage...........................................................................................................801 
 VDD calibration data register VDDCDR..............................................................................801 
 Instructions for using the internal reference voltage............................................................801 
 OPTION BYTES ..........................................................................................802
 Function of option bytes..............................................................................................................802 
 User option bytes (000C0H~000C2H).................................................................................802 
 Flash data protection option bytes (000C3H, 500004H).....................................................803 
 Format of the user option bytes..................................................................................................804 
 Format of flash data protection option bytes ..............................................................................810 
 FLASH CONTROL.......................................................................................811 
 Description of FLASH control......................................................................................................811 
 Structure of FLASH memory.......................................................................................................811 
 Registers for controlling FLASH .................................................................................................812 
 Flash write protection register (FLPROT)............................................................................812 
 FLASH operation control register (FLOPMD1,FLOPMD2) .................................................813 
 Flash erase control register (FLERMD)...............................................................................814 
 Flash status register (FLSTS)..............................................................................................815 
 Flash full-chip erase time control register (FLCERCNT).....................................................815 
 Flash sector erase time control register (FLSERCNT)........................................................816 
 Flash write time control register (FLPROCNT)....................................................................817 
 Flash erase protection control register (FLSECPR)............................................................818 
 How to operate FLASH...............................................................................................................819 
 Sector erase.........................................................................................................................819 
 Chip erase............................................................................................................................820 
 Word program......................................................................................................................820 
 Flash Read..................................................................................................................................821 
 Cautions for FLASH operation....................................................................................................821 
 REVISION HISTORY...................................................................................822
 
 
 

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CPU

Overview

This chapter provides a brief introduction to the features and debugging features of the ARM Cortex-M0+ core.

For details, please refer to the ARM related documentation.

Cortex-M0+ core features

⚫ARM Cortex-M0+ processor is a 32-bit RISC core with a 2-stage pipeline that supports privileged and user

modes

⚫32-cycle hardware multiplier

⚫Nested Vector Interrupt Controller (NVIC)

◼1 non-maskable interrupt (NMI)

◼Support 32 maskable interrupt requests (IRQ)

◼4 interrupt priority levels

⚫System Timer (SysTick) is a 24-bit countdown timer with a choice of FCLK or FIL count clock

⚫Vector Table Offset Register (VTOR)

◼The software can write VTOR to relocate the vector table start address to a different location.

◼The default value of this register is 0x0000_0000, the lower 8 bits are ignored for writing and zero for

reading, which means the offset is 256 bytes aligned.

Debugging features

⚫2-wire SWD debug interface

⚫Support for suspending, resuming and single-step execution of programs

⚫Access to the processor's core registers and special function registers

⚫4 hardware breakpoints (BPU)

⚫Unlimited software breakpoints (BKPT instruction)

⚫2 data observation points (DWT)

⚫Accessing memory while the core is executing

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Figure 1-1: Debug block diagram of Cortex-M0+

MCU Debug Support

Cortex-M0+ Debug Support

Cortex-M0+

Core

Bus matrix

SW-DP

Bridge

NVIC

DWT

BPU

DBGMCU

Debug AP

SWDIO

SWCLK

System bus

Notice: SWD does not work in deep sleep mode, please do debug operation in active and sleep mode.

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