Avnet Xilinx spartan-3 User manual

Avnet Electronics Marketing 1 of 33 Rev 1.0 04/17/2006

Released Literature # ADS-005104

Xilinx®Spartan™-3 Development Kit

User Guide

Avnet Electronics Marketing 2 of 33 Rev 1.0 04/17/2006

Released Literature # ADS-005104

Table of Contents

1.0 Introduction...............................................................................................................................................................................4

1.1 Description............................................................................................................................................................................4

1.2 Features: ..............................................................................................................................................................................4

1.3 Demo Applications:...............................................................................................................................................................5

1.4 Ordering Information:............................................................................................................................................................5

2.0 Hardware ..................................................................................................................................................................................5

2.1 Spartan-3 FPGA...................................................................................................................................................................6

2.2 Configuration........................................................................................................................................................................6

2.3 Jumper Settings..................................................................................................................................................................10

2.4 Clocks.................................................................................................................................................................................14

2.5 On Board Displays (2x20 LCD & 128x64 OLED)................................................................................................................14

2.6 VGA (DB15 & Video DAC)..................................................................................................................................................17

2.7 Audio Codec.......................................................................................................................................................................19

2.8 PS2 Keyboard & Mouse Ports............................................................................................................................................20

2.9 Dip & Push-Button Switches...............................................................................................................................................20

2.10 LEDs ..............................................................................................................................................................................21

2.11 Piezo Buzzer..................................................................................................................................................................21

2.12 High-speed Serial Communication.................................................................................................................................21

2.13 Memory..........................................................................................................................................................................23

2.14 Communication (RS232, 10/100 Ethernet, USB2.0)......................................................................................................24

2.15 I/O Connectors...............................................................................................................................................................28

2.16 Power.............................................................................................................................................................................32

3.0 Software/BSP..........................................................................................................................................................................33

3.1 What is included.................................................................................................................................................................33

3.2 Hello World.........................................................................................................................................................................33

3.3 On-Chip Peripheral Bus (OPB) External Memory Project(s)...............................................................................................33

3.4 Web Server.........................................................................................................................................................................33

Figures

Figure 1 - Spartan-3 Dev (Top Side) Figure 2 - Spartan-3 Dev (Bottom Side).........................................................................4

Figure 3 - Spartan-3 Development Board Picture.......................................................................................................................................5

Figure 4 - Spartan-3 Development Board Block Diagram...........................................................................................................................6

Figure 5 – Boundary Scan Mode Selection via JP2 ...................................................................................................................................7

Figure 6 - Configuration / Debug Connections – Par3................................................................................................................................7

Figure 7 - Configuration / Debug Connections – Par IV .............................................................................................................................7

Figure 8 - JTAG Chain Standalone Mode (Default)....................................................................................................................................8

Figure 9 – Design Revision “BIT SEL” Jumpers JP3..................................................................................................................................8

Figure 10 - Fly Wire Connection J1............................................................................................................................................................9

Figure 11 - FPGA Configuration Mode Select..........................................................................................................................................10

Figure 12 - Design Revision Select..........................................................................................................................................................10

Figure 13 - I/O Voltage Selection Banks 4&5...........................................................................................................................................11

Figure 14 - I/O Voltage Selection Banks 1&2...........................................................................................................................................11

Figure 15 - I/O Voltage Selection Banks 2&3...........................................................................................................................................11

Figure 16 - Default Jumper Placement.....................................................................................................................................................13

Figure 17 - Resistor Jumper Pin-out.........................................................................................................................................................25

Figure 18 - Barrel Power Connector "J7"..................................................................................................................................................32

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Tables

Table 1: Ordering Information.....................................................................................................................................................................5

Table 2 - Spartan-3 Attributes by Density...................................................................................................................................................6

Table 3 - JTAG Headers (Par-3 & Par-4) Pin-Out......................................................................................................................................7

Table 4 - JTAG Chain Selection "JP6" .......................................................................................................................................................8

Table 5 – FPGA Configuration from PROM … Jumper Setting..................................................................................................................9

Table 6 – Available GCLK Sources..........................................................................................................................................................14

Table 7 – Available Non-GCLK Osc.........................................................................................................................................................14

Table 8 – 2x20 Character LCD Pin-out ....................................................................................................................................................15

Table 9 - OLED Display Pin-out ...............................................................................................................................................................16

Table 10 - OLED Display FPGA Pin-out...................................................................................................................................................17

Table 11 – Video DAC - FPGA Pin-out ....................................................................................................................................................18

Table 12 – Video DAC Jumpers...............................................................................................................................................................18

Table 13 – Audio Codec - FPGA Pin-out..................................................................................................................................................19

Table 14 – Audio Codec Jumpers ............................................................................................................................................................19

Table 15 - Dipswitch FPGA Pin-out..........................................................................................................................................................20

Table 16 - Pushbutton FPGA Pin-out.......................................................................................................................................................20

Table 17 - LED FPGA Pin-out..................................................................................................................................................................21

Table 18 - LVDS FPGA Pin-out................................................................................................................................................................22

Table 19 - Timing Parameters for DDR SDRAM Peripheral.....................................................................................................................23

Table 20 - RS232 FPGA Pin-out..............................................................................................................................................................24

Table 21 - RS232 Connector Pin-out .......................................................................................................................................................24

Table 22 - Ethernet PHY Modes...............................................................................................................................................................25

Table 23 - Ethernet Jumpers and LEDs ...................................................................................................................................................25

Table 24 - Ethernet FPGA Pin-out............................................................................................................................................................26

Table 25 - USB Interface FPGA Pin-out...................................................................................................................................................27

Table 26 - AvBus Connector "P1" Pin-out................................................................................................................................................29

Table 27 - AvBus Connector "P2" Pin-out................................................................................................................................................30

Table 28 - Header "JP1" Pin-out ..............................................................................................................................................................31

Avnet Electronics Marketing 4 of 33 Rev 1.0 04/17/2006

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1.0 Introduction

The purpose of this manual is to describe the functionality and contents of the Spartan-3 Development Kit from Avnet Electronics

Marketing. This document includes instructions for operating the board, descriptions of the hardware features and explanations of the

example projects.

1.1 Description

The Spartan-3 Development Kit provides a platform for engineers designing with the Xilinx Spartan-3 FPGA. The board provides the

necessary hardware to not only evaluate the features of the Spartan-3 but also to implement complete user applications. Example

projects are provided to help the user understand the design tool flow of the Xilinx Embedded Development Kit (EDK) software

environment.

1.2 Features:

¾FPGA

•Xilinx XC3S1500/2000-FG676 Spartan-3 FPGA

¾I/O Peripherals

•2x16 character LCD

•128x64 OSRAM OLED graphical display

•DB15 & video DAC

•Audio CODEC

•PS2 keyboard & mouse ports

•8-position DIP switch

•2 push-buttons

•8 discrete LEDs

•Piezo buzzer

•3, 140-pin general purpose I/O expansion connectors

(AvBus)

•Up to 30 LVDS pairs

•1, 50-pin 0.1" header for easy I/O access

¾Memory

•Micron DDR SDRAM (32 MB)

•16 MB FLASH

•2 MB SRAM

¾Communication

•RS-232 serial port

•10/100 Ethernet

•USB 2.0

¾Configuration

•Xilinx platform FLASH configuration PROM(s)

•Parallel IV cable support for JTAG

•Fly-wire support for Parallel III and MultiLINX™

Figure 1 - Spartan-3 Dev (Top Side) Figure 2 - Spartan-3 Dev (Bottom Side)

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1.3 Demo Applications:

The Spartan-3 Development Kit from Avnet Electronics Marketing comes with example projects designed in Xilinx Platform Studio

(XPS). XPS is a software tool in the Xilinx Embedded Development Kit that provides the user with a single tool flow for creating both

hardware and software systems. The example projects help the user to more quickly learn the XPS tool and develop user-specific

applications by leveraging already tested and functional designs. The example projects that will be discussed in detail later in this

document are listed below.

*Note: For additional demo applications, please contact your local Avnet FAE.

Hello World Project

External Memory Project(s)

oAn OPB_DDR SDRAM memory project uses the MicroBlaze for accessing on-board DDR SDRAM.

oAn OPB_EMC project uses the MicroBlaze for accessing on-board SRAM and Flash memory.

oUsing the MicroBlaze soft processor, execute code from internal Block RAM or external memory.

oUse the JTAG debug interface to download modified executable files to internal or external memories.

Ethernet Web Server

oMicroBlaze system uses the OPB_EMAC to serve up web pages.

oUses on-board 10/100 National PHY

Figure 3 - Spartan-3 Development Board Picture

1.4 Ordering Information:

The following table lists the evaluation kit part numbers and available software options.

Internet link at http://www.em.avnet.com/ads

Part Number Hardware

ADS-XLX-SP3-DEV1500 Spartan-3 Development Kit with an XC3S1500

ADS-XLX-SP3-DEV2000 Spartan-3 Development Kit with an XC3S2000

Table 1: Ordering Information

2.0 Hardware

This section of the manual describes the hardware of the Spartan-3 Development board. The hardware was designed with the

Spartan-3 FPGA as the focal point. The block diagram is shown in Figure 4.

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Spartan 3

XC3S2000-FG676

RS232

Clocks:

Socket

66MHz

100MHz

125MHz diff. (opt.)

Switches

Dip(8)

P.B.(2)

181 I/O

AVBus

16MB Flash /

2MB SRAM

Configuration

LEDs

(8)

128x64 OLED

Display

63 I/O 32

50-Pin Header

4 I/O

47 I/O

P4 JTAG Fly-wire

Header

10/100

Ethernet PHY

USB2.0

Cypress FX2

19 I/O

Platform Flash

XCFxxP (08-32)

(2) XCF04S

32MB DDR SDRAM

(1500 & 2000 only)

63 I/O 16

13 I/O

2x16 Char. LCD

Bus Switches

Audio

Codec

UBC1400

RGB DAC

ADV7123

AVBus

PS2

Buzzer

Figure 4 - Spartan-3 Development Board Block Diagram

2.1 Spartan-3 FPGA

The Spartan-3 Development board was designed to support the Spartan-3 FPGA in the 676-pin, BGA package (FG676). The FG676

package supports three mid-range densities (1000, 1500, and 2000). The board was designed to support two of the three densities: the

3S1500 and 3S2000. The schematic symbol used for the Spartan-3 device indicates the specific I/O pins available in each density (396

I/Os with 2VP7 and 556 I/Os with the 2VP20/30). Table 3 describes the attributes of the Spartan-3 device based on density.

Spartan-3 System Logic CLB Array

(One CLB=Four Slices) BlockRAM Dedicated Max

Part Gates Cells Rows Col Total CLBs (bits) BRAM Multipliers DCMs User I/O

XC3S1500 1.5M 29,952 64 52 3,328 576K 32 32 4

XC3S2000 2M 46,080 80 64 5,120 720K 40 40 4

Table 2 - Spartan-3 Attributes by Density

2.2 Configuration

The Spartan-3 Development board supports Boundary-scan as well as Master/Slave Serial and Master/Slave Parallel(SelectMAP)

using the on-board PROMs. All configuration pins are brought out to “J1”, should the user wish to program with an alternate method.

2.2.1 Boundary scan

Programming the Spartan-3 FPGA via Boundary-scan requires a JTAG download cable (not included in the kit). The Spartan-

3 Development board has connectors to support both the flying leads connection of the Parallel Cable III and the ribbon cable

connection of the Parallel Cable IV. These connectors are labeled “J1” and “J5” respectively.

The FPGA and Platform Flash are both in the JTAG chain and both may be configured via the chain. When programming the

FPGA via the JTAG interface, it is good practice to place the device in Boundary Scan mode. This may be accomplished

using the Mode select jumpers at JP2. The jumper positions are labeled M0 – M2 and are all LOW by default. So placing a

jumper provides a HIGH. The Spartan-3 FPGA is set to Master Serial mode when no jumpers are installed on JP2. To set the

FPGA to boundary-scan mode, install shunts on JP2 at locations 1-2 & 5-6 as shown in below. Note that power should be

removed when changing Mode select jumpers.

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JP2

Mode 0

Mode 1

Mode 2

For Boundary Scan mode,

place jumpers at JP2

positions 1-2 & 5-6.

Figure 5 – Boundary Scan Mode Selection via JP2

JTAG Header (J1)

J1 is a standard 0.1” header and is intended for use with flying leads, such as those of the Xilinx Parallel Cable 3 (PC3)

downloading/debugging cable. Connect the leads as indicated below for “J1”.

Signal Name Par-3 (J1) pin PAR-4 Ribbon (JP6) pin

VCC 20 2

TDI 9 10

TDO 15 8

TMS 13 4

TCK 11 6

GND 19, 21 1,3,5,7,9,11 or 13

Table 3 - JTAG Headers (Par-3 & Par-4) Pin-Out

Figure 6 - Configuration / Debug Connections – Par3

Parallel Cable IV / MultiPro Ribbon (J5)

J5 is intended for connection to a 14-pin ribbon as supplied with a Xilinx Parallel Cable IV or MultiPro Desktop Tool. Connect

the ribbon cable to JP6 as shown below. Note that the ribbon and connector are keyed to ensure proper connection.

Figure 7 - Configuration / Debug Connections – Par IV

For futher information regarding Xilinx configuration solutions, please visit:

http://www.xilinx.com/products/design_resources/config_sol/index.htm

Modifying the JTAG Chain

Pin 1

Keyed Connection–

Only Plugs in One way

Lower Right Edge

of Board

LEDs

(Shown here for reference only)

1 Heade

Flying Leads –

Such as used with Parallel Cable 3

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By default, the Spartan 3 Development board JTAG chain includes a Platform Flash and the FPGA. The board provides the

user with the ability to add/remove devices from the JTAG chain. Each device may be bypassed by way of 0 ohm resistor

jumpers. The header labeled “JP6” allows the user even more flexibility with the chain. By moving this jumper, you may add

in the chains of daughter-boards by way of the AvBus. Most users, however, will only use the JTAG chain in standalone mode

(default) with a jumper installed across pins 2-3 on JP6. It is recommended to start with this mode and review the schematic

carefully if you wish to change it.

“JP7” JTAG Chain Selection – Jumper Settings

Pins 2-3 Standalone Mode – Spartan-3 and XC18V04 PROMs

Pins 1-2 and 4-5 Add AvBus P1 Connector to standalone

Table 4 - JTAG Chain Selection "JP6"

Figure 8 - JTAG Chain Standalone Mode (Default)

2.2.2 Configuration With Platform Flash

The Platform Flash PROM(s) provide easy-to-use non-volatile storage for the configuration file. These devices are in–system

programmable via the boundary scan chain and may program the FPGA in Master Serial, Master SelectMAP, Slave Serial, or

Slave SelectMAP modes. After programming the proms with configuration data, remove power and set JP2 appropriately as

indicated below. When power is re-applied, the FPGA will clock data from the PROMs using the selected mode.

Figure 9 – Design Revision “BIT SEL” Jumpers JP3

Board Edge

umper on Pins 2-3

PROM FPGA

Default

Chain

Enables Prom CLKOUT –

FOR FPGA Slave Modes ONLY!

PROM Enabled JP25 = 1-2 Allows multiple revisions in PROM Mode Jumpers –

Select FPGA Configuration Mode

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Configuration Mode

(M0 : M1 : M2) Prom Clock En

JP24 Prom Enable

JP25 Mode Jumpers

JP2 Notes

Master Serial DEFAULT

(0:0:0)

DEFAULT

FPGA provides CCLK

Master Parallel (Master SelectMAP)

(1:1:0)

FPGA provides CCLK

Slave Serial

(1:1:1)

PROM provides CCLK

Slave Parallel (Slave SelectMAP)

(0:1:1)

PROM provides CCLK

Table 5 – FPGA Configuration from PROM … Jumper Setting

Design Revisioning With Platform Flash

The Spartan-3 Development Board is designed to support the advanced features of the parallel Platform Flash PROM

including support for multiple design revisions and compressed configuration files. These features are disabled by the default

jumper settings. If an MCS (prom file) has been built with multiple revisions, use the “BIT SEL” jumper (JP3) to select the

desired revision. By default, no jumpers are installed and rev 0 will be loaded. To load revision 1, a jumper would be placed

at JP3 position 1-2.

2.2.3 Custom Configuration Methods

In addition to JTAG chain signals, J1 provides the user with an interface to the FPGA dedicated and dual function

programming pins. This enables fly-wire support for the programming methods mentioned above and gives flexibility for

developing a custom programming solution.

TDI

TCK

TMS

TDO

GND

GND VCC

CS_B

DONE

PROG_B

INIT_B

BUSY/DOUT

RDWR_B

CCLK

Figure 10 - Fly Wire Connection J1

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2.3 Jumper Settings

This section provides a description of the jumper settings for the Development board. The jumpers are listed in order by JP number.

The board is ready to use out of the box with the default jumper settings.

JP1 “BNK 2&3 VRef” – Supplies a 1.25V reference voltage to the VREF inputs of banks 2 & 3. Use only if your I/O standard requires a

reference voltage of 1.25V. Note that when installed, all VREF pins in banks 2 & 3 will be connected to the 1.25V reference rail. Any

unused reference pins should be dealt with appropriately, or the FPGA may have an adverse affect on the rail. One option for unused

VREF pins is to use the config prohibit attribute in the UCF and then use tri-state option for unused I/O in bitgen. Another option may

be to use “dummy” inputs to ensure the FPGA will not drive the unused VREFs.

Default: Uninstalled; BNK 2&3 Vref not connected to 1.25V rail.

JP2 “MODE SELECT” – Configuration mode selection. Use to select the configuration mode for the FPGA. With no jumpers installed,

these pins are pulled low enabling Master Serial mode. Installing jumpers on JP2 will pull the corresponding mode pin high, as

indicated in the Figure below. See the Configuration section of this document for further information. Default: Uninstalled; Master

Serial mode; FPGA will be configured from Platform Flash.

Figure 11 - FPGA Configuration Mode Select

JP3 “Bit Select” – Design Revision Select, selects the configuration design when the PROM is programmed with multiple revisions.

When no jumpers are installed, the PROM is set for external selection mode with revision 0 selected. Installing jumpers on JP3 will pull

the corresponding select pin high, as indicated in the Figure below.

Default: Uninstalled; external enabled using Rev0

SEL0

SEL1

Figure 12 - Design Revision Select

JP4 “HSWAP_EN” – Enables pull-ups on the Spartan-3 I/O pins during configuration. A pull-down resistor is used to enable the I/O pull-

ups during configuration. Install a jumper to disable the configuration pull-ups.

Default: Open; pull-ups enabled.

JP6 – JTAG chain configuration. Selects the JTAG chain configuration. Install a jumper across pins 2-3 for standalone mode. Install

jumpers across pins 1-2 and pins 4-5 to add the AvBus connector labeled “P1” to the standalone chain. These settings are described in

the Hardware section of this manual (see “Modifying the JTAG Chain” in Boundary scan section).

Default: Installed across pins 2-3; standalone chain mode.

JP7 – JTAG TRST#, forces TRST low.

Default: Open, pulled-high.

JP8 “ETH EN” – Ethernet Enable, connects an I/O pin on the FPGA to the reset pin of the Ethernet PHY. See the “PHY_RST#” net on

the schematic. The PHY is held in reset by a pull-down resistor when a jumper is not installed. Default: Installed, FPGA drives the

PHY reset.

JP9 “USB 5V” – USB 5.0V Power, when installed allows the USB host to supply the 5.0V rail of the evaluation board over the USB

connection. This is not recommended since the evaluation board requires more current than USB specification provides for. Using the

USB port for board power may damage the USB host (the PC or laptop).

Default: Open, board power comes from J7 connector.

JP10 “USB EEPROM WC#” – Serial EEPROM write protect, install a shunt to protect programmed data.

Default: Open, read/write enabled.

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