Avnet Xilinx spartan-3 User manual

Avnet Electronics Marketing 1 of 33 Rev 1.0 04/17/2006

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Xilinx®Spartan™-3 Development Kit

User Guide

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Table of Contents

1.0 Introduction...............................................................................................................................................................................4

1.1 Description............................................................................................................................................................................4

1.2 Features: ..............................................................................................................................................................................4

1.3 Demo Applications:...............................................................................................................................................................5

1.4 Ordering Information:............................................................................................................................................................5

2.0 Hardware ..................................................................................................................................................................................5

2.1 Spartan-3 FPGA...................................................................................................................................................................6

2.2 Configuration........................................................................................................................................................................6

2.3 Jumper Settings..................................................................................................................................................................10

2.4 Clocks.................................................................................................................................................................................14

2.5 On Board Displays (2x20 LCD & 128x64 OLED)................................................................................................................14

2.6 VGA (DB15 & Video DAC)..................................................................................................................................................17

2.7 Audio Codec.......................................................................................................................................................................19

2.8 PS2 Keyboard & Mouse Ports............................................................................................................................................20

2.9 Dip & Push-Button Switches...............................................................................................................................................20

2.10 LEDs ..............................................................................................................................................................................21

2.11 Piezo Buzzer..................................................................................................................................................................21

2.12 High-speed Serial Communication.................................................................................................................................21

2.13 Memory..........................................................................................................................................................................23

2.14 Communication (RS232, 10/100 Ethernet, USB2.0)......................................................................................................24

2.15 I/O Connectors...............................................................................................................................................................28

2.16 Power.............................................................................................................................................................................32

3.0 Software/BSP..........................................................................................................................................................................33

3.1 What is included.................................................................................................................................................................33

3.2 Hello World.........................................................................................................................................................................33

3.3 On-Chip Peripheral Bus (OPB) External Memory Project(s)...............................................................................................33

3.4 Web Server.........................................................................................................................................................................33

Figures

Figure 1 - Spartan-3 Dev (Top Side) Figure 2 - Spartan-3 Dev (Bottom Side).........................................................................4

Figure 3 - Spartan-3 Development Board Picture.......................................................................................................................................5

Figure 4 - Spartan-3 Development Board Block Diagram...........................................................................................................................6

Figure 5 – Boundary Scan Mode Selection via JP2 ...................................................................................................................................7

Figure 6 - Configuration / Debug Connections – Par3................................................................................................................................7

Figure 7 - Configuration / Debug Connections – Par IV .............................................................................................................................7

Figure 8 - JTAG Chain Standalone Mode (Default)....................................................................................................................................8

Figure 9 – Design Revision “BIT SEL” Jumpers JP3..................................................................................................................................8

Figure 10 - Fly Wire Connection J1............................................................................................................................................................9

Figure 11 - FPGA Configuration Mode Select..........................................................................................................................................10

Figure 12 - Design Revision Select..........................................................................................................................................................10

Figure 13 - I/O Voltage Selection Banks 4&5...........................................................................................................................................11

Figure 14 - I/O Voltage Selection Banks 1&2...........................................................................................................................................11

Figure 15 - I/O Voltage Selection Banks 2&3...........................................................................................................................................11

Figure 16 - Default Jumper Placement.....................................................................................................................................................13

Figure 17 - Resistor Jumper Pin-out.........................................................................................................................................................25

Figure 18 - Barrel Power Connector "J7"..................................................................................................................................................32

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Tables

Table 1: Ordering Information.....................................................................................................................................................................5

Table 2 - Spartan-3 Attributes by Density...................................................................................................................................................6

Table 3 - JTAG Headers (Par-3 & Par-4) Pin-Out......................................................................................................................................7

Table 4 - JTAG Chain Selection "JP6" .......................................................................................................................................................8

Table 5 – FPGA Configuration from PROM … Jumper Setting..................................................................................................................9

Table 6 – Available GCLK Sources..........................................................................................................................................................14

Table 7 – Available Non-GCLK Osc.........................................................................................................................................................14

Table 8 – 2x20 Character LCD Pin-out ....................................................................................................................................................15

Table 9 - OLED Display Pin-out ...............................................................................................................................................................16

Table 10 - OLED Display FPGA Pin-out...................................................................................................................................................17

Table 11 – Video DAC - FPGA Pin-out ....................................................................................................................................................18

Table 12 – Video DAC Jumpers...............................................................................................................................................................18

Table 13 – Audio Codec - FPGA Pin-out..................................................................................................................................................19

Table 14 – Audio Codec Jumpers ............................................................................................................................................................19

Table 15 - Dipswitch FPGA Pin-out..........................................................................................................................................................20

Table 16 - Pushbutton FPGA Pin-out.......................................................................................................................................................20

Table 17 - LED FPGA Pin-out..................................................................................................................................................................21

Table 18 - LVDS FPGA Pin-out................................................................................................................................................................22

Table 19 - Timing Parameters for DDR SDRAM Peripheral.....................................................................................................................23

Table 20 - RS232 FPGA Pin-out..............................................................................................................................................................24

Table 21 - RS232 Connector Pin-out .......................................................................................................................................................24

Table 22 - Ethernet PHY Modes...............................................................................................................................................................25

Table 23 - Ethernet Jumpers and LEDs ...................................................................................................................................................25

Table 24 - Ethernet FPGA Pin-out............................................................................................................................................................26

Table 25 - USB Interface FPGA Pin-out...................................................................................................................................................27

Table 26 - AvBus Connector "P1" Pin-out................................................................................................................................................29

Table 27 - AvBus Connector "P2" Pin-out................................................................................................................................................30

Table 28 - Header "JP1" Pin-out ..............................................................................................................................................................31

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1.0 Introduction

The purpose of this manual is to describe the functionality and contents of the Spartan-3 Development Kit from Avnet Electronics

Marketing. This document includes instructions for operating the board, descriptions of the hardware features and explanations of the

example projects.

1.1 Description

The Spartan-3 Development Kit provides a platform for engineers designing with the Xilinx Spartan-3 FPGA. The board provides the

necessary hardware to not only evaluate the features of the Spartan-3 but also to implement complete user applications. Example

projects are provided to help the user understand the design tool flow of the Xilinx Embedded Development Kit (EDK) software

environment.

1.2 Features:

¾FPGA

•Xilinx XC3S1500/2000-FG676 Spartan-3 FPGA

¾I/O Peripherals

•2x16 character LCD

•128x64 OSRAM OLED graphical display

•DB15 & video DAC

•Audio CODEC

•PS2 keyboard & mouse ports

•8-position DIP switch

•2 push-buttons

•8 discrete LEDs

•Piezo buzzer

•3, 140-pin general purpose I/O expansion connectors

(AvBus)

•Up to 30 LVDS pairs

•1, 50-pin 0.1" header for easy I/O access

¾Memory

•Micron DDR SDRAM (32 MB)

•16 MB FLASH

•2 MB SRAM

¾Communication

•RS-232 serial port

•10/100 Ethernet

•USB 2.0

¾Configuration

•Xilinx platform FLASH configuration PROM(s)

•Parallel IV cable support for JTAG

•Fly-wire support for Parallel III and MultiLINX™

Figure 1 - Spartan-3 Dev (Top Side) Figure 2 - Spartan-3 Dev (Bottom Side)

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1.3 Demo Applications:

The Spartan-3 Development Kit from Avnet Electronics Marketing comes with example projects designed in Xilinx Platform Studio

(XPS). XPS is a software tool in the Xilinx Embedded Development Kit that provides the user with a single tool flow for creating both

hardware and software systems. The example projects help the user to more quickly learn the XPS tool and develop user-specific

applications by leveraging already tested and functional designs. The example projects that will be discussed in detail later in this

document are listed below.

*Note: For additional demo applications, please contact your local Avnet FAE.

Hello World Project

External Memory Project(s)

oAn OPB_DDR SDRAM memory project uses the MicroBlaze for accessing on-board DDR SDRAM.

oAn OPB_EMC project uses the MicroBlaze for accessing on-board SRAM and Flash memory.

oUsing the MicroBlaze soft processor, execute code from internal Block RAM or external memory.

oUse the JTAG debug interface to download modified executable files to internal or external memories.

Ethernet Web Server

oMicroBlaze system uses the OPB_EMAC to serve up web pages.

oUses on-board 10/100 National PHY

Figure 3 - Spartan-3 Development Board Picture

1.4 Ordering Information:

The following table lists the evaluation kit part numbers and available software options.

Internet link at http://www.em.avnet.com/ads

Part Number Hardware

ADS-XLX-SP3-DEV1500 Spartan-3 Development Kit with an XC3S1500

ADS-XLX-SP3-DEV2000 Spartan-3 Development Kit with an XC3S2000

Table 1: Ordering Information

2.0 Hardware

This section of the manual describes the hardware of the Spartan-3 Development board. The hardware was designed with the

Spartan-3 FPGA as the focal point. The block diagram is shown in Figure 4.

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Spartan 3

XC3S2000-FG676

RS232

Clocks:

Socket

66MHz

100MHz

125MHz diff. (opt.)

Switches

Dip(8)

P.B.(2)

181 I/O

AVBus

16MB Flash /

2MB SRAM

Configuration

LEDs

(8)

128x64 OLED

Display

63 I/O 32

50-Pin Header

4 I/O

47 I/O

P4 JTAG Fly-wire

Header

10/100

Ethernet PHY

USB2.0

Cypress FX2

19 I/O

Platform Flash

XCFxxP (08-32)

(2) XCF04S

32MB DDR SDRAM

(1500 & 2000 only)

63 I/O 16

13 I/O

2x16 Char. LCD

Bus Switches

Audio

Codec

UBC1400

RGB DAC

ADV7123

AVBus

PS2

Buzzer

Figure 4 - Spartan-3 Development Board Block Diagram

2.1 Spartan-3 FPGA

The Spartan-3 Development board was designed to support the Spartan-3 FPGA in the 676-pin, BGA package (FG676). The FG676

package supports three mid-range densities (1000, 1500, and 2000). The board was designed to support two of the three densities: the

3S1500 and 3S2000. The schematic symbol used for the Spartan-3 device indicates the specific I/O pins available in each density (396

I/Os with 2VP7 and 556 I/Os with the 2VP20/30). Table 3 describes the attributes of the Spartan-3 device based on density.

Spartan-3 System Logic CLB Array

(One CLB=Four Slices) BlockRAM Dedicated Max

Part Gates Cells Rows Col Total CLBs (bits) BRAM Multipliers DCMs User I/O

XC3S1500 1.5M 29,952 64 52 3,328 576K 32 32 4

XC3S2000 2M 46,080 80 64 5,120 720K 40 40 4

Table 2 - Spartan-3 Attributes by Density

2.2 Configuration

The Spartan-3 Development board supports Boundary-scan as well as Master/Slave Serial and Master/Slave Parallel(SelectMAP)

using the on-board PROMs. All configuration pins are brought out to “J1”, should the user wish to program with an alternate method.

2.2.1 Boundary scan

Programming the Spartan-3 FPGA via Boundary-scan requires a JTAG download cable (not included in the kit). The Spartan-

3 Development board has connectors to support both the flying leads connection of the Parallel Cable III and the ribbon cable

connection of the Parallel Cable IV. These connectors are labeled “J1” and “J5” respectively.

The FPGA and Platform Flash are both in the JTAG chain and both may be configured via the chain. When programming the

FPGA via the JTAG interface, it is good practice to place the device in Boundary Scan mode. This may be accomplished

using the Mode select jumpers at JP2. The jumper positions are labeled M0 – M2 and are all LOW by default. So placing a

jumper provides a HIGH. The Spartan-3 FPGA is set to Master Serial mode when no jumpers are installed on JP2. To set the

FPGA to boundary-scan mode, install shunts on JP2 at locations 1-2 & 5-6 as shown in below. Note that power should be

removed when changing Mode select jumpers.

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JP2

Mode 0

Mode 1

Mode 2

For Boundary Scan mode,

place jumpers at JP2

positions 1-2 & 5-6.

Figure 5 – Boundary Scan Mode Selection via JP2

JTAG Header (J1)

J1 is a standard 0.1” header and is intended for use with flying leads, such as those of the Xilinx Parallel Cable 3 (PC3)

downloading/debugging cable. Connect the leads as indicated below for “J1”.

Signal Name Par-3 (J1) pin PAR-4 Ribbon (JP6) pin

VCC 20 2

TDI 9 10

TDO 15 8

TMS 13 4

TCK 11 6

GND 19, 21 1,3,5,7,9,11 or 13

Table 3 - JTAG Headers (Par-3 & Par-4) Pin-Out

Figure 6 - Configuration / Debug Connections – Par3

Parallel Cable IV / MultiPro Ribbon (J5)

J5 is intended for connection to a 14-pin ribbon as supplied with a Xilinx Parallel Cable IV or MultiPro Desktop Tool. Connect

the ribbon cable to JP6 as shown below. Note that the ribbon and connector are keyed to ensure proper connection.

Figure 7 - Configuration / Debug Connections – Par IV

For futher information regarding Xilinx configuration solutions, please visit:

http://www.xilinx.com/products/design_resources/config_sol/index.htm

Modifying the JTAG Chain

Pin 1

Keyed Connection–

Only Plugs in One way

Lower Right Edge

of Board

LEDs

(Shown here for reference only)

1 Heade

Flying Leads –

Such as used with Parallel Cable 3

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By default, the Spartan 3 Development board JTAG chain includes a Platform Flash and the FPGA. The board provides the

user with the ability to add/remove devices from the JTAG chain. Each device may be bypassed by way of 0 ohm resistor

jumpers. The header labeled “JP6” allows the user even more flexibility with the chain. By moving this jumper, you may add

in the chains of daughter-boards by way of the AvBus. Most users, however, will only use the JTAG chain in standalone mode

(default) with a jumper installed across pins 2-3 on JP6. It is recommended to start with this mode and review the schematic

carefully if you wish to change it.

“JP7” JTAG Chain Selection – Jumper Settings

Pins 2-3 Standalone Mode – Spartan-3 and XC18V04 PROMs

Pins 1-2 and 4-5 Add AvBus P1 Connector to standalone

Table 4 - JTAG Chain Selection "JP6"

Figure 8 - JTAG Chain Standalone Mode (Default)

2.2.2 Configuration With Platform Flash

The Platform Flash PROM(s) provide easy-to-use non-volatile storage for the configuration file. These devices are in–system

programmable via the boundary scan chain and may program the FPGA in Master Serial, Master SelectMAP, Slave Serial, or

Slave SelectMAP modes. After programming the proms with configuration data, remove power and set JP2 appropriately as

indicated below. When power is re-applied, the FPGA will clock data from the PROMs using the selected mode.

Figure 9 – Design Revision “BIT SEL” Jumpers JP3

Board Edge

umper on Pins 2-3

PROM FPGA

Default

Chain

Enables Prom CLKOUT –

FOR FPGA Slave Modes ONLY!

PROM Enabled JP25 = 1-2 Allows multiple revisions in PROM Mode Jumpers –

Select FPGA Configuration Mode

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Configuration Mode

(M0 : M1 : M2) Prom Clock En

JP24 Prom Enable

JP25 Mode Jumpers

JP2 Notes

Master Serial DEFAULT

(0:0:0)

DEFAULT

FPGA provides CCLK

Master Parallel (Master SelectMAP)

(1:1:0)

FPGA provides CCLK

Slave Serial

(1:1:1)

PROM provides CCLK

Slave Parallel (Slave SelectMAP)

(0:1:1)

PROM provides CCLK

Table 5 – FPGA Configuration from PROM … Jumper Setting

Design Revisioning With Platform Flash

The Spartan-3 Development Board is designed to support the advanced features of the parallel Platform Flash PROM

including support for multiple design revisions and compressed configuration files. These features are disabled by the default

jumper settings. If an MCS (prom file) has been built with multiple revisions, use the “BIT SEL” jumper (JP3) to select the

desired revision. By default, no jumpers are installed and rev 0 will be loaded. To load revision 1, a jumper would be placed

at JP3 position 1-2.

2.2.3 Custom Configuration Methods

In addition to JTAG chain signals, J1 provides the user with an interface to the FPGA dedicated and dual function

programming pins. This enables fly-wire support for the programming methods mentioned above and gives flexibility for

developing a custom programming solution.

TDI

TCK

TMS

TDO

GND

GND VCC

CS_B

DONE

PROG_B

INIT_B

BUSY/DOUT

RDWR_B

CCLK

Figure 10 - Fly Wire Connection J1

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2.3 Jumper Settings

This section provides a description of the jumper settings for the Development board. The jumpers are listed in order by JP number.

The board is ready to use out of the box with the default jumper settings.

JP1 “BNK 2&3 VRef” – Supplies a 1.25V reference voltage to the VREF inputs of banks 2 & 3. Use only if your I/O standard requires a

reference voltage of 1.25V. Note that when installed, all VREF pins in banks 2 & 3 will be connected to the 1.25V reference rail. Any

unused reference pins should be dealt with appropriately, or the FPGA may have an adverse affect on the rail. One option for unused

VREF pins is to use the config prohibit attribute in the UCF and then use tri-state option for unused I/O in bitgen. Another option may

be to use “dummy” inputs to ensure the FPGA will not drive the unused VREFs.

Default: Uninstalled; BNK 2&3 Vref not connected to 1.25V rail.

JP2 “MODE SELECT” – Configuration mode selection. Use to select the configuration mode for the FPGA. With no jumpers installed,

these pins are pulled low enabling Master Serial mode. Installing jumpers on JP2 will pull the corresponding mode pin high, as

indicated in the Figure below. See the Configuration section of this document for further information. Default: Uninstalled; Master

Serial mode; FPGA will be configured from Platform Flash.

Figure 11 - FPGA Configuration Mode Select

JP3 “Bit Select” – Design Revision Select, selects the configuration design when the PROM is programmed with multiple revisions.

When no jumpers are installed, the PROM is set for external selection mode with revision 0 selected. Installing jumpers on JP3 will pull

the corresponding select pin high, as indicated in the Figure below.

Default: Uninstalled; external enabled using Rev0

SEL0

SEL1

Figure 12 - Design Revision Select

JP4 “HSWAP_EN” – Enables pull-ups on the Spartan-3 I/O pins during configuration. A pull-down resistor is used to enable the I/O pull-

ups during configuration. Install a jumper to disable the configuration pull-ups.

Default: Open; pull-ups enabled.

JP6 – JTAG chain configuration. Selects the JTAG chain configuration. Install a jumper across pins 2-3 for standalone mode. Install

jumpers across pins 1-2 and pins 4-5 to add the AvBus connector labeled “P1” to the standalone chain. These settings are described in

the Hardware section of this manual (see “Modifying the JTAG Chain” in Boundary scan section).

Default: Installed across pins 2-3; standalone chain mode.

JP7 – JTAG TRST#, forces TRST low.

Default: Open, pulled-high.

JP8 “ETH EN” – Ethernet Enable, connects an I/O pin on the FPGA to the reset pin of the Ethernet PHY. See the “PHY_RST#” net on

the schematic. The PHY is held in reset by a pull-down resistor when a jumper is not installed. Default: Installed, FPGA drives the

PHY reset.

JP9 “USB 5V” – USB 5.0V Power, when installed allows the USB host to supply the 5.0V rail of the evaluation board over the USB

connection. This is not recommended since the evaluation board requires more current than USB specification provides for. Using the

USB port for board power may damage the USB host (the PC or laptop).

Default: Open, board power comes from J7 connector.

JP10 “USB EEPROM WC#” – Serial EEPROM write protect, install a shunt to protect programmed data.

Default: Open, read/write enabled.

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JP11 “USB DIS” – USB Disable, install a shunt to hold the Cypress EZ-USB device in reset. When open, the USB reset line is

controlled by either an I/O pin of the FPGA or the push-button labeled “SW2”.

Default: Open, the FPGA or push-button controls the USB reset.

JP12 “FLASH WP#” – Flash write protect. When jumper is installed, WP# will be tied hard low. When uninstalled, WP# is pulled high

via pull-up resistor.

Default: Uninstalled; write protect not active.

JP13 “FLASH RESET” – Connects the flash reset pin to the FPGA. This connection is only available on the 2000 density part. When

uninstalled (or unavailable ie...1500 density part), the flash reset will be inactive (flash enabled) by way of resistor pull-up on the board.

Default: Installed

JP14 “LCD BACKLIGHT” – Enables the LED backlight panel on the 2x20 LCD.

Default: Installed

JP16 “BANK 4&5 VCCO VOLTAGE” – VIO Selection, selects the I/O voltage for FPGA banks 4 and 5. Only one jumper should be

placed at this connector. Valid placements are 1-2, 2-3 as indicated in the Figure below.

Default: Installed across pins 1-2; 3.3V supply.

Figure 13 - I/O Voltage Selection Banks 4&5

JP17 “BANK 0&1 VCCO VOLTAGE” – VIO Selection, selects the I/O voltage for FPGA banks 0 and 1. Only one jumper should be

placed at this connector. Valid placements are 1-2, 3-4, or 5-6 as indicated in the Figure below.

Default: Installed across pins 1-2; 3.3V supply.

Figure 14 - I/O Voltage Selection Banks 1&2

JP18 “BANK 2&3 VCCO VOLTAGE” – VIO Selection, selects the I/O voltage for FPGA banks 2 and 3. Only one jumper should be

placed at this connector. Valid placements are 1-2, 3-4, or 5-6 as indicated in the Figure below.

Default: Installed across pins 1-2; 3.3V supply.

3.3V

2.5V

1.2V

Figure 15 - I/O Voltage Selection Banks 2&3

JP20 “A/V ENABLE” – The Video DAC, Audio Codec, PS2 Ports, and Buzzer are connected to the FPGA by way of bus switches.

Installing this jumper will enable the switches, thereby connecting the peripherals to the FPGA. Removing this jumper will disable the

switches, disconnecting the peripherals from the FPGA. This may be desirable if the 50-pin I/O header is to be used instead of the A/V

peripherals.

Default: Installed; A/V peripherals enabled.

JP21 “CODEC CLK DISABLE” – Installing this jumper will disable the 24.576MHz oscillator to the Codec.

Default: Uninstalled, codec oscillator enabled

JP22 “AUDIO EN” – When uninstalled, the Codec is held in reset by a resistor pull-down. When installed, the reset line is connected to

the FPGA, allowing it to take the codec out of reset.

Default: Installed, FPGA controls reset line.

JP23 “VIDEO CLK DISABLE” – Installing this jumper will disable the 25.175MHz oscillator to the video DAC.

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Default: Uninstalled, DAC oscillator enabled

JP24 “PROM CLKOUT ENABLE” – When installed, Enables the prom clkout to drive the configuration clock (CCLK) for FPGA Slave

Mode configuration. If using the PROM device as the clock source, make sure the jumper on JP27 is not installed and that the jumper

settings on JP2 put the FPGA in a Slave configuration mode. Note: The PROM must supply CCLK when a compressed configuration

file is used.

Default: Open, the FPGA provides the configuration clock.

JP25 “PROM ENABLE” – PROM Enable, position 1-2 connects the DONE pin on the FPGA to the chip enable pin of the PROM(s).

Position 2-3 will pull the enable low. The PROM is disabled by a pull-up resistor when a jumper is not installed. Default: Installed on 1-

2; using the DONE pin, the PROM is enabled when the FPGA is not configured.

JP27 “USB CCLK ENABLE” – USB CCLK Enable, when installed enables the USB device to drive the configuration clock of the FPGA.

If using the USB device as the clock source, disable the PROM by removing the jumper on JP25 and make sure the jumper settings on

JP2 put the FPGA in a Slave configuration mode.

Default: Open, the FPGA or PROM provides the configuration clock.

JP28 “USB RS232 RX” – This signal is intended to be an output from the FPGA to either the RX Input of the EZUSB chip or the TXIN2

of the RS232 IC. Jumper on 2-3 connects the USB RX signal to the FPGA. Jumper on 1-2 connects RS232 signal TX2 to the FPGA.

Default: none; neither signal connected to the FPGA

JP29 “USB RS232 TX” – This signal is intended to be an input to the FPGA from either the TX output of the EZUSB chip or the

RXOUT2 of the RS232 IC. Jumper on 2-3 connects the USB TX signal to the FPGA. Jumper on 1-2 connects RS232 signal RX2 to

the FPGA.

Default: none; neither signal connected to the FPGA.

JP30 “Buzz Enable” – Connects “buzzer” net. Remove this jumper to disable the piezo buzzer.

Default: Installed, buzzer enabled.

JP31 “Prom Busy” – Connects net “prom_busy” to net “fpga_busy”. Support for a PROM errata which will likely be obsolete by the time

this document is published.

Default: Installed

The following figure illustrates the default placement of the jumpers installed on the Spartan-3 Development Board.

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Figure 16 - Default Jumper Placement

JTx Resistor Jumpers –

Additional flexibility has been designed into the circuit in the form of resistor jumpers “JTx” and series resistors that can be moved or

removed to alter the functionality of the board. The purpose of some of these components may be discussed in other sections of this

manual others may not be discussed at all. The position of these components should not be altered without careful review of the

schematics and associated component data sheets to prevent damage to the board.

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2.4 Clocks

The available clock sources on the Spartan-3 Development board are shown below. The following were brought in on global clock

inputs and are recommended for use as system clocks.

•Single-ended, 66MHz Oscillator – FPGA pin “AD13”

•Single-ended, 100MHz Oscillator – FPGA pin “A13”

•Single-ended socket , 40MHz Oscillator – FPGA pin “AE14”

•Single-ended SMA input – FPGA pin “AE13”

•Single-ended header input – FPGA pin “AF14”

•Differential, Optional Oscillator Pads (U14) – FPGA pins “C14” (P) and “B14” (N)

Freq GCLK Input FPGA pin# Notes

66MHz YES AD13

100MHz YES A13

40MHz typ. YES AE14 Socket

- YES AE13 SMA

- YES AF14 Header

125MHz typ. YES C14

B14 Not installed by default. 2.5V Diff Osc.

may be purchased separately.

Table 6 – Available GCLK Sources

There are clocks on the board which are included as reference for the Video DAC and Codec. These are 25.175MHz and 24.576MHz,

respectively. These were not brought in on GCLK inputs and are connected to the FPGA via bus switches. JP20 must be present in

order to use these clocks.

•Single-ended, 25.175MHz Oscillator / Header_IO(24) – FPGA pin “W21”

•Single-ended, 24.576MHz Oscillator / Header_IO(36) – FPGA pin “AE24”

Freq GCLK Input FPGA pin# Notes

25.175MHz NO W21 Use W/VGA. Shared with Header.

24.576MHz NO AE24 Use W/Codec. Shared with Header

Table 7 – Available Non-GCLK Osc.

2.5 On Board Displays (2x20 LCD & 128x64 OLED)

2.5.1 2x20 Character LCD

Manufacturer: Optrex

Part #: DMC-20261NYJ-LY-BCE

Backlight En JP14

2x20 Character Display

14 13

R110 Contrast

A 2x20 Character LCD is included with the Spartan-3 Development board. The displays LED backlight may be enabled using JP14.

Contrast may be adjusted using potentiometer “R110”. The display interface is either four or eight-bits wide, although our demos use

the 8-bit option.

For detailed information, please see:

www.optrex.com/SiteImages/LitCentral/Dmcman_full.pdf

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LCD Pin # LCD Name FPGA pin#

RS# DISP_RS P8

D0 DISP_D0 AE21

D1 DISP_D1 AF21

D2 DISP_D2 AE20

D3 DISP_D3 AF20

D4 DISP_D4 AE19

D5 DISP_D5 AE18

D6 DISP_D6 AE17

D7 DISP_D7 AD14

EN# LCD_EN R8

Table 8 – 2x20 Character LCD Pin-out

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128 Pixels

2.5.2 128x64 OSRAM Pictiva™ OLED Graphics Display

Manufacturer: OSRAM

Part #: OS128064PK16MY0A00

128x64 OLED

Graphics Display

The Spartan-3 Development board includes a 128x64 OSRAM Pictiva™ OLED(Organic Light Emitting Diode) graphics display. This is

a 4-bit per pixel (grayscale) single-color passive matrix display. The display has a contrast ratio of 100:1 and a 160° viewing angle.

The Pictiva displays are available in serial or parallel interface, although applications in this kit use the 8-bit parallel interface.

The parallel bus interface is compatible with 68-series and 80-series microcontrollers and is selectable at pin 4 of the ribbon cable (see

pinout below). This will affect the function of several other pins as noted in the table below. The Spartan-3 Dev board uses a resistor

jumper (JT5) to select the desired level of pin 4. By default the jumper is placed at pads 1-2 for a logic high enabling an 80-series

interface. This placement is subject to change based on future demo applications.

Display

Pin# Pin Name I/O Description FPGA

Pin#

1 CS# I Chip Select – Active Low AA4

2 RES# I Reset – Active Low AA6

3 BS1 I Interface Protocol Select.

LOW = 68-series

HIGH = 80-series

4 D/C# I Data / Command

HIGH = Bus contains data for DDRAM

LOW = Bus contains command

5 R/W# (WR#) I Read/Write in 68 series mode

Write strobe in 80-series mode Y7

6 E (RD#) I E clock in 68-series mode

Read strobe in 80-series mode Y10

7 D0 I/O Data 0 AE21

8 D1 I/O Data 1 AF21

9 D2 I/O Data 2 AE20

10 D3 I/O Data 3 AF20

11 D4 I/O Data 4 AE19

12 D5 I/O Data 5 AE18

13 D6 I/O Data 6 AE17

14 D7 I/O Data 7 AD14

15 VSSB I n/c -

16 VDD I Positive supply (2.4V – 3.5V) -

17 VCC(VLL) I OLED Drive power (12V – 16V) -

18 VSS I Ground -

Table 9 - OLED Display Pin-out

The OLED drive voltage (VLL) must be between 12V and 16V. However, it requires very little operating current. Typical ILL is 20-

24mA. So an on-board 12V supply could be used with little affect on the power budget. If there is no 12V supply on board, one may

design in a low-cost, low-power 12V source. The Spartan-3 Dev board uses a National Semiconductor LM2704 Micropower Step-up

DC/DC Converter. This small (SOT23) converter has an input range of 2.2V-7V and an adjustable output up to 20V.

For more display information visit www.osram-os.com or www.pictiva.com.

For power supply information please see www.national.com.

It should be noted that the 2x20 Character display and 128x64 graphics display share a common data bus. In designs where only one

of the displays is to be used, the other’s Enable (or CS) pin should be driven inactive using the FPGA. This will help avoid bus

contention. An alternative is to simply remove the unused display from the board. The following table illustrates the pins which are

common as well as the corresponding pin on the FPGA.

64 Pixels

4-Bits/Pixel Single Color Graphics Displa

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OLED Signal LCD Name FPGA pin#

DISP_CSB - AA4

DISP_RSTB - AA6

DISP_RS DISP_RS P8

DISP_RD_WRB - Y7

DISP_ECLK - Y10

DISP_D0 DISP_D0 AE21

DISP_D1 DISP_D1 AF21

DISP_D2 DISP_D2 AE20

DISP_D3 DISP_D3 AF20

DISP_D4 DISP_D4 AE19

DISP_D5 DISP_D5 AE18

DISP_D6 DISP_D6 AE17

DISP_D7 DISP_D7 AD14

- LCD_EN R8

Table 10 - OLED Display FPGA Pin-out

2.6 VGA (DB15 & Video DAC)

Manufacturer: Analog Devices

Part #: ADV7125KST140

The Spartan-3 Dev board provides a DB15 and Video DAC to drive an analog

RGB monitor. RGB data is output from the FPGA in a 24-bit parallel format (8 bits each Red/Green/Blue). This data, along with clock,

blanking and synchronization signals is provided to the ADV7125 triple video DAC for conversion to RS-343A/RS-170-compatible video

signals to drive an RGB monitor. Note that the ADV7125 can accept 10-bit R, G and B data but pin utilization of the FPGA limits this

data path to 24 instead of 30 bits. The eight R, G and B data bits are provided to the eight most-significant bits of the DAV7125 RGB

inputs with the two least-significant bits of R, G and B held at ground level.

Also provided by the FPGA to the ADV7125 are composite synchronization and blanking signals. Vertical and horizontal

synchronization signals are brought to pins 14 and 13 (respectively) of DB15 connector (P4) but are not required. The analog RGB

signals generated by the ADV7123 are connected to P4 to drive an analog RGB monitor via a doubly terminated 75-ohm coaxial cable.

The ADV7125 device internally encodes video synchronizing information onto the Green channel.

The 25.175MHz oscillator provides the required clocking for a 640 X 480 60Hz VGA monitor. This is determined as follows: horizontal

lines (pixels) * vertical lines * refresh rate. Due to required overhead (e.g., horizontal and vertical retrace, etc), the 640 X 480 display is

actually 800 X 525 (800 x 525 x 59.94 = 25.175e6). Note that while 60Hz is commonly used in discussion, the actual refresh rate is

59.94Hz. The oscillator may be replaced with a higher frequency oscillator to support higher resolution monitors; e.g., VGA (640 x 480)

@72 Hz requires 31.5MHz, SVGA (800 x 600) @ 72Hz requires 50.0MHz, XGA (1024 X 768) @ 75 Hz requires 78.75MHz, SXGA

(1280 X 1024) @ 75Hz requires 135.0MHz. The ADV7125KST140 140MHz device furnished on the board is sufficient for SXGA

resolution at 75Hz.

Pin 6

Pin 15 Pin 11

DB15 VGA Connector

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Signal *Header Equivalent

Net FPGA pin#

Red(0) HDR_IO(0) A19

Red(1) HDR_IO(1) A22

Red(2) HDR_IO(2) A20

Red(3) HDR_IO(3) A23

Red(4) HDR_IO(4) D19

Red(5) HDR_IO(5) A21

Red(6) HDR_IO(6) E19

Red(7) HDR_IO(7) B23

Green(0) HDR_IO(8) B22

Green(1) HDR_IO(9) C23

Green(2) HDR_IO(10) C22

Green(3) HDR_IO(11) B21

Green(4) HDR_IO(12) C21

Green(5) HDR_IO(13) E21

Green(6) HDR_IO(14) D21

Green(7) HDR_IO(15) F21

Blue(0) HDR_IO(16) E20

Blue(1) HDR_IO(17) B20

Blue(2) HDR_IO(18) F20

Blue(3) HDR_IO(19) D20

Blue(4) HDR_IO(20) F19

Blue(5) HDR_IO(21) B19

Blue(6) HDR_IO(22) G19

Blue(7) HDR_IO(23) C19

Video_clk HDR_IO(24) W21

Horiz_sync HDR_IO(25) W20

Vert_sync HDR_IO(26) Y21

Comp_sync HDR_IO(27) Y20

Blank HDR_IO(28) AC22

Table 11 – Video DAC - FPGA Pin-out

* Note: DAC signals are connected to the FPGA by way of a bus switch. This allows the re-use of header signals. If you wish to use

the 50-pin header J17, you may disable the bus switches using JP20.

Jumper Function Default

JP23 On – disables oscillator U28 OFF

JP20 On – enables bus switches ON

JT10 Resistor Jumper:

2-3 – Power save mode 1-2

Table 12 – Video DAC Jumpers

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2.7 Audio Codec

Manufacturer: Philips

Part #: UCB1400BE

A Philips UCB1400 stereo 20-bitAudio CODEC is used to provide stereo line- level and

monophonic microphone input and stereo line-level/headphone out functions for the Spartan-3 Development Board. 3.5mm audio jacks

provide input/output connectivity as follows:

J10: Stereo line-level out

J11: Stereo line-level in

J12: Mono microphone in

The FPGA communicates with the UCB1400 via an AC97 interface. The UCB operates in master mode; with the FPGA operating as

an AC97 controller device; in this mode the UCB1400 provides AC97 timing (Bit Clock). Details of the operation of the AC97 interface

are somewhat complex and beyond the scope of this document. Refer to the UCB1400 data sheet and the AC97 Specification Rev. 2.1

for further details.

A 24.576MHz clock is provided to the UCB1400. This clock is also connected to the FPGA and may be disabled by placing a shunt at

JP21.

2.7.1 Touch Panel Inputs

The UCB1400 includes a resistive touch panel controller which may be used to provide digitally encoded position data to the FPGA via

the AC97 interface. X and Y touch screen inputs are provided to the UCB1400 via test points TP7, TP8, TP9, and TP10. An interrupt

signal (IRQ_OUT) can be generated to the FPGA to indicate a touch panel entry was made.

2.7.2 General Purpose I/O & A/D Converter

The UCB1400 CODEC provides ten general-purpose I/O bits that may be set/read via the AC97 interface. Additionally, four analog

voltage inputs may be multiplexed into the UCB1400’s 10-bit A/D converter. The 10 GPIO bits are connected to Header J8 and the four

analog voltages are input via Header J9.

Signal *Header Equivalent

Net FPGA pin#

ac97_sdata_out HDR_IO(29) Y22

ac97_sdata_in HDR_IO(30) AD22

ac97_bit_clk HDR_IO(31) AB22

ac97_sync_out HDR_IO(32) AB23

ac97_reset_n HDR_IO(33) Y23

irq_out HDR_IO(34) AD23

adc_sync HDR_IO(35) AA23

clock_24_576M HDR_IO(36) AE24

Table 13 – Audio Codec - FPGA Pin-out

* Note: Codec signals are connected to the FPGA by way of a bus switch. This allows the re-use of header signals. If you wish to use

the 50-pin header J17, you may disable the bus switches using JP20.

2.7.3 Codec Jumpers

Jumper Function Default

JP21 On – disables oscillator U26 OFF

JP20 On – enables bus switches ON

JP22 On – Connects Reset to FPGA

Off – Forces Codec into reset ON

Table 14 – Audio Codec Jumpers

Audio Codec

Mic

Line

Out

Audio En

JP22

J10J11J12

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2.8 PS2 Keyboard & Mouse Ports

The Spartan-3 Dev Board includes two standard 6-pin Mini-Din (PS2)

connectors labeled JS1 and JS2. This two-wire interface will provide connection to PS2 Mice or Keyboards. Since this is a two wire

interface, only pins Data (pin-1) and Clk (pin-5) are connected to the FPGA. The following table provides the pinout for JS1 & JS2.

Pin Function *HDR Equivalent Net FPGA Pin#

JS1 – pin 1 Data HDR_IO(37) AA24

JS1 – pin 5 CLK HDR_IO(38) AF24

JS2 – pin 1 Data HDR_IO(39) AB25

JS2 – pin 5 CLK HDR_IO(40) AB26

* Note: PS2 signals are connected to the FPGA by way of a bus switch (JP20 ON). This allows the re-use of header signals. If you

wish to use the 50-pin header J17, you may disable the bus switches by removing JP20. Removing JP20 will disconnect the PS2

connectors from the FPGA.

PS2 Mouse/Keyboard protocol information may be found at:

http://panda.cs.ndsu.nodak.edu/~achapwes/PICmicro/PS2/ps2.htm

2.9 Dip & Push-Button Switches

An eight-position dipswitch (SPST) has been installed on the board and attached to the FPGA. These switches provide digital inputs to

user logic as needed. The signals are pulled low (0) by 10K ohm resistors when the switch is open and tied to 2.5V (1) when the switch

is closed.

Switch # Signal Name FPGA pin#

S1-1 SWITCH0 F1

S1-2 SWITCH1 F2

S1-3 SWITCH2 F3

S1-4 SWITCH3 G4

S1-5 SWITCH4 F4

S1-6 SWITCH5 G5

S1-7 SWITCH6 H6

S1-8 SWITCH7 H13

Table 15 - Dipswitch FPGA Pin-out

Two momentary closure push buttons have been installed on the board and attached to the FPGA. These buttons can be programmed

by the user and are ideal for logic reset and similar functions. Pull down resistors hold the signals low (0) until the switch closure pulls it

high (1).

Silkscreen Part # Signal Name FPGA pin#

SW2 SWITCH_PB1 H14

SW3 SWITCH_PB2 H15

Table 16 - Pushbutton FPGA Pin-out

CLK

DATA

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