Avnet PicoZed FMC V2 User manual

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v1.1
PicoZed
FMC Carrier Card
V2
PZCC-FMC-V2, Revision 1.1
Hardware User Guide
Version 1.1

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v1.1
Table of Contents
1Introduction .................................................................................................................... 3
1.1 Glossary ...............................................................................................................................3
1.2 Additional Documentation....................................................................................................3
1.3 PZCC-FMC-V2 Features: ........................................................................................................4
2Functional Description..................................................................................................... 8
2.1 Reset sources .......................................................................................................................8
2.2 User I/O – Switches and LEDs................................................................................................9
2.3 I2C Address space and registers ..........................................................................................11
2.4 Clocks.................................................................................................................................12
2.5 PCIe x1 Gen2 Interface........................................................................................................13
2.6FMC LPC Connector ............................................................................................................14
2.7 SFP+ Interface – P1 (7015/30 SOM only)..............................................................................17
2.8 PS/PL PMOD™ Interfaces – JA, JB, JZ & JPS1 ........................................................................18
2.9 JX1, JX2 and JX3 SOM Interface MicroHeaders.....................................................................19
2.10 Multi-Gigabit Transceivers (MGTs)...................................................................................22
2.11 USB UART – J1.................................................................................................................23
2.12 USB OTG Interface – J8 ....................................................................................................24
2.13 SOM 10/100/1000 Ethernet RJ45 – J9 ..............................................................................25
2.14 MAC ID – EEPROM...........................................................................................................26
2.15 MAC ID – UNI/O EEPROM (7Z015/30 only).......................................................................27
2.16 Real Time Clock – Maxim DS3231MZ................................................................................27
2.17 HDMI Interface – J10 .......................................................................................................29
2.18 microSD Card Interface....................................................................................................30
2.19 Fan Header – JP3 .............................................................................................................31
2.20 JTAG Configuration – J7 ...................................................................................................31
3Power ........................................................................................................................... 32
3.1 Power Input – J2/SW7 ........................................................................................................32
3.2 Molex to Non-ATX connection ............................................................................................33
3.3 Power Rails ........................................................................................................................33
3.4 2.5V LDO – U12...................................................................................................................33
3.5 JP1 – FPGA VBAT (VCCBATT) ...............................................................................................34
3.6 VADJ selection - JP5 ............................................................................................................34
3.7 Sequencing.........................................................................................................................35
3.8 Bypassing/Decoupling/Filtering ..........................................................................................36
3.9 PG Module Power Good LED ...............................................................................................36
4Jumpers, configuration and test points: ......................................................................... 37
4.1 FMC GA [1:0] jumper header...............................................................................................38
4.2 Clock Synthesizer test header..............................................................................................38
4.3 Power Supply monitor header – J12 ....................................................................................39
5Mechanical ................................................................................................................... 39
5.1 Diagram and Model ............................................................................................................39
5.2 Weight ...............................................................................................................................39
6Revision History ............................................................................................................ 40
Appendix A – additional information/test results................................................................. 41

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1 Introduction
The PicoZed FMC Carrier Card Version 2 (PZCC-FMC-V2) is a development board designed for
customers to easily evaluate the Avnet PicoZed System On Module (SOM) boards. This board
provides an I/O breakout platform for the PicoZed SOMs. The PZCC-FMC-V2 provides all
necessary SOM power, reset control and SoC I/O pin accessibility through the JX1, JX2, and JX3
MicroHeaders.
This document details the specific features, operation and configuration of the PZCC-FMC-V2
board.
Please visit http://picozed.org/product/picozed-fmc-carrier-card-v2 for the latest product information.
1.1 Glossary
Term Definition
MIO
Multiplexed Input Output – the dedicated I/O available on the PS
PL
Programmable Logic
POR
Power On Reset
PS
Processing System
SMPS
Switch Mode Power Supply
SOM
System On Module
SoC
System On Chip – Xilinx Zynq®-7000
Pmod
Peripheral Module
FMC
FPGA Mezzanine Card
LPC
Low Pin Count
Table 1 – Glossary of Acronyms
1.2 Additional Documentation
Specific Zynq pin connections are not called out in this document. These are available in either the
PicoZed FMC Carrier Card V2 Pinout Tables or Programmable Logic Master User Constraints
available on the PicoZed FMC Carrier Card V2 documentation page:
http://picozed.org/support/documentation/13076
Avnet PicoZed products information:
Additional information and documentation on Avnet’s PicoZed product line can be found at
www.picozed.org.
Xilinx Zynq information:
Additional information and documentation on Xilinx’s Zynq®-7000 All Programmable SoCs can be
found at www.xilinx.com/zynq.

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1.3 PZCC-FMC-V2 Features:
•Interfaces:
oFMC LPC (72 differential, 3 single ended)
oJTAG
•Single JTAG connector allows accesses to the Zynq and the FMC board through
automatic switching circuit.
o4 Digilent Pmod™ compatible interfaces:
•JPS1 connected to PS MIO
•JA & JB connected to Bank 13 PL (7Z015/20/30 only)
•JZ connected to Bank 13 PL (7Z015/30 only)
oMicro SD Card slot
oThree 100-pin JX MicroHeaders for SOM insertion
oSFP+ Interface (7Z015/30 only) – control signals connected to JSFP1 to JZ1 PMOD
using a jumper cable.
oHDMI 1080p Output
oPCIe x 1 Gen 2 Interface pairs
oSMA connector pairs:
•SMA-TX P/N
•SMA-RX P/N
o10/100/1000 Mb RJ45 Ethernet connector (connected to PicoZed SOM PHY)
oTransceivers for 7015/30:
•SFP+ Interface
•PCIe x1 Gen 2
•SMA
•FMC LPC
oI2C SW programmable clock synthesizer with I2C configuration EEPROM.
oI2C Synthesizer Test Header spaced at 0.100”.
oUSB UART - Micro USB connector & transceiver.
oUSB 2.0 OTG – USB Type A connector on the faceplate.
oMAC ID I2C EEPROM
oMAC ID UNI/O single wire EEPROM (SFP+ MAC ID – 7015/30 SOM only).
oI2C Real Time Clock (RTC)
oCR1025 Battery holder for RTC
o1 PS User Push Button
o5 PL User Push Buttons
o2 Configuration Push Buttons (CARRIER_RST_N, PG_MODULE_N)
o4 PL Red User LEDs
o2 PS Red User LEDs
o3 Status LEDs (VIN_HDR, FPGA DONE & PG_MODULE)
o1 100 mil header for FPGA_VBAT_TEST
o1 Voltage Monitor pads spaced at 0.100”
o1 VADJ User Selectable Header: 1.8V, 2.5V, 3.3V selection; defaults to 1.8V
o1 slide switch for main power

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•Power
oOn Board
•ADP2384 single channel SMPS IC:
•Generates the primary board 5V power supply.
- 5V @ 4 Amp capable.
•ADP5052 five channel SMPS IC:
•VADJ: 1.8V, 2.5V, 3.3V up to 4A (user selectable voltage)
•3.3V & VCCO_13 up to 4.0A
•1.0V_AVCC up to 1.2 A
•1.2V_AVTT up to 1.2 A
•1.8V LDO@ 200mA
oWall Adapter
•Primary 12V ≥5.0A, 2x3 connector
•NOTE: not an ATX compatible power supply.
Figure 1 – PZCC-FMC-V2 Block Diagram

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Figure 2 – PZCC-FMC-V2 Functional Block Diagram

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Figure 3 – PZCC-FMC-V2 Component Overview

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2 Functional Description
The PZCC-FMC-V2 Carrier is an expansion board for the PicoZed SOMs. The primary I/O
interface is via the LPC FMC connector. The board features additional MGT lanes for PCIe and
SFP+. The PZCC-FMC-V2 bridges Avnet’s PicoZed SOM products to common high speed
interfaces.
In addition to the LPC FMC connector, the PZCC-FMC-V2 also has 4 Digilent Pmod™ compatible
interfaces, a SFP+ connector, a Micro SD card, Dual function JTAG port (FMC & SOM), an HDMI
port, 2 USB ports (UART and OTG TYPE A 2.0), PCIe x1 Gen 2.0 edge connector and a SOM
driven Ethernet port.
The board includes user adjustable operational features to aid in product design and
development. Such features include software configurable MGT clock synthesizer SMA MGT
(TX/RX) data inputs and a user adjustable VADJ power plane.
The board’s HDMIO I2C bus, nets labeled: HDMIO_SCL/SDA is the board’s primary I2C bus and
can be considered the “board I2C bus”. More information can be found in section: 2.3.
2.1 Reset sources
System Power Reset: PG_MODULE_N - SW9
The PG_MODULE signal is an active high 2.75V signal. When high, it indicates both the carrier
and SOM power supplies are within their regulation tolerance parameters and functional. The
signal is held low until the power supplies have completed their successful sequencing routine.
Green LED D4 illuminates when this signal is high.
The user can force this pin low by depressing SW9, which will trigger a reboot of the Zynq
device. Depressing this button will not cause a hard power cycle, however the PS and PL on
the Zynq device will be reset to power on default settings and the selected boot process is
initiated based on the boot configuration setting of the SOM.
SOM
Net Name:
Carrier Net Name: JX2 Pin #:
PG_MODULE
PG_MODULE
11
Table 2 – PG_MODULE Connection
Processor Subsystem Reset: CARRIER_SRST_N - SW8
The SYS_RST# button provides an active low signal to net CARRIER_SRST_N which allows
the user to reset all of the PL logic on the SOM FPGA without disturbing the debug
environment. For example, the previous breakpoints set by the user remain valid after system
reset. Due to security concerns, system reset erases all memory content within the PS,
including the OCM. The PL is also reset in system reset. Upon de-assertion of this signal, the
SoC does not re-sample the boot mode strapping pins.
SOM
Net Name:
Carrier Net Name: JX1 Pin #:
CARRIER_SRST_N
CARRIER_SRST_N
6
Table 3 – CARRIER_SRST_N Connection

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2.2 User I/O – Switches and LEDs
User Push Buttons: SW1 – SW6: 7015/20/30 SOM
When a 7015/20/30 SOM is plugged in, the carrier provides 5 PL and 1 PS user GPIO push
buttons for the Zynq-7000 AP SoC (blue and green in the table below). When a 7010 SOM is
attached, only two switches are available - SW1 (PL_PB1) and SW6 (PS_PB1). These are
highlighted in the table as green.
Each signal has a pull down resistor and noise decoupling capacitor to help reduce switch
bounce. When depressed the button provides a logic high on the respective net. The switches
are placed in a North, South, East, West and Center position. This is to allow the customer to
better distinguish which button to press.
Below figure shows the locations of the user switches and the associated labeling. These
switches are located in the upper left corner of the PZCC-FMC-V2 board.
Figure 4 – Push Button Orientation
MIO Number Carrier
Net Name: Switch Name: JX
MicroHeader
Connection:
N/A
PL_PB1
SW1, North
JX1.19
N/A
PL_PB2
SW5, South
JX2.100
N/A
PL_PB3
SW3, East
JX2.95
N/A
PL_PB4
SW2, West
JX2.94
N/A
PL_PB5
SW4, Center
JX2.96
MIO51
PS_PB1
PS_PB
JX3.64
Table 4 – Push Button Connections

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User LEDs
The Carrier has 6 SOM driven user LEDs – 4 PL and 2 PS. LEDs listed in green are available
to the 7010 SOM. All LEDs (highlighted green and blue) are available to all other SOMs. A logic
high from the Zynq-7000 AP SoC I/O turns the LED on. LED’s are sourced from the PZCC-
FMC-V2’s 3.3V rail.
MIO Number Carrier
Net Name:
JX
MicroHeader
Connection:
N/A
PL_LED1
JX1.17
N/A
PL_LED2
JX2.97
N/A
PL_LED3
JX2.99
N/A
PL_LED4
JX2.93
MIO47
PS_LED1
JX3.40
MIO50
PS_LED2
JX3.66
Table 5 – User LED Connections

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2.3 I2C Address space and registers
The FMC-V2 carrier’s “board I2C” bus is the board’s HDMIO I2C bus. The net names on this bus
are HDMIO_SCL and HDMIO_SDA. This bus accesses the following devices at the following
I2C addresses:
IDT Config EEPROM Slave Address (EEPROM): 0xA0
-------------------------------------
| 1 | 0 | 1 | 0 | A2 | A1 | 0 | R/W |
-------------------------------------
MAC ID Slave Address (EEPROM): 0xA2
-------------------------------------
| 1 | 0 | 1 | 0 | A2 | A1 | 1 | R/W |
-------------------------------------
RTC Slave Address: 0xD0
-----------------------------------
| 1 | 1 | 0 | 1 | 0 | 0 | 0 | R/W |
-----------------------------------
HDMI Slave Addresses:
0x72 (Main Map slave address)
-----------------------------------
| 0 | 1 | 1 | 1 | 0 | 0 | 1 | R/W |
-----------------------------------
0x70 (Packet Memory Map slave address controlled by Main Map Register 0x45)
-----------------------------------
| 0 | 1 | 1 | 1 | 0 | 0 | 0 | R/W |
-----------------------------------
0x78 (CEC Map slave address controlled by Main Map Register 0xE1)
-----------------------------------
| 0 | 1 | 1 | 1 | 1 | 0 | 0 | R/W |
-----------------------------------
0x7C (Fixed I2C Map slave address controlled by Main Map Register 0xF9)
-----------------------------------
| 0 | 1 | 1 | 1 | 1 | 0 | 1 | R/W |
-----------------------------------
0x7E (CEC Map slave address controlled by Main Map Register 0xE1)
-----------------------------------
| 0 | 1 | 1 | 1 | 1 | 1 | 0 | R/W |
-----------------------------------
IDT-242 Slave Address:
0xF8 (Default OTP setting when using -006 IDT factory load)
-----------------------------------
| 1 | 1 | 1 | 1 | 1 | 0 | 0 | R/W |
-----------------------------------
0xD8 (When configured with Avnet factory default EEPROM config)
-----------------------------------
| 1 | 1 | 0 | 1 | 1 | 0 | 0 | R/W |
-----------------------------------

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2.4 Clocks
Clock synthesizer IC - U13
IDT-242 I2C ADDR: 0xD8
The FMC2 contains an IDT 8T49N242-006 I2C programmable clock synthesizer to offer
maximum clocking flexibility. Upon power up the part is configured via U14, a 24AA025T
EEPROM. A 38.888MHz crystal is used for the synthesizer’s input for optimum performance
and frequency selection. See the below figure for topology. There is also a non-populated
header (J14) available on the board. See section 4.2
The synthesizer is wired to provide 2 outputs – Q3 single ended and Q2 differential. Both Q2
and Q3 outputs are synthesized from one of three clock inputs: 38.888MHz, FMC_GBTCLK, or
PCIe_CLK. The choice of how U13 handles the input and output clocks is configured in U14.
1) Channel Q3 output – Single ended output from 1 MHz to 200 MHz on SOM Bank 13
MRCC pin (PL_CLK JX3.73).
2) Channel Q3 INV output: tied to test pad TP31.
3) Channel Q2 output is a differential output derived from either the FMC clock or the
PCIe clock and drives the SOMs MGT1 bank. The choice of which clock to use is
configured in U14, the configuration EEPROM.
4) The PCIe clock input is routed to the synthesizer and the JX3 connector in a multidrop
LVDS (M-LVDS) configuration for optimal performance.
•Synthesizer base default address: 0xD8
•Base address adjustable via JT1 and JT2.
For more information on the IDT 8T49N242 IC please refer to the IDT datasheet:
www.idt.com/>>8T49N242
Figure 5 – Clock Synthesizer topology

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SOM Net Name: Carrier Net Name: JX3 Pin:
RSVD_PCIE_REFCLK0_P
MGTREFCLK0_P
1
RSVD_PCIE_REFCLK0_N
MGTREFCLK0_N
3
RSVD_MGTREFCLK1_P
MGTREFCLK1_P
2
RSVD_MGTREFCLK1_N
MGTREFCLK1_N
4
BANK13_LVDS_7_P
PL_CLK
73
Table 6 – Clock synthesizer pin table
I2C Clock Configuration EEPROM – U14
EEPROM I2C ADDR: 0xA0
The clock configuration EEPROM is a Microchip 24AA025T-I/OT and is used to configure U13
when powered up.
•Base default address: 0xA0
•Base address adjustable set through JT3 and JT4.
•If desired, the user can change the timing of the synthesizer via IDT’s Timing
Commander Tool via the on board HDMIO I2C bus or by populating J14 and
connecting directly to the HDMIO I2C bus.
•For more information on how to custom program the clock, a reference design and
tutorials page can be accessed at the following location:
http://picozed.org/support/design/13076/106
•For more information on the Timing Commander tool:
(http://www.idt.com/products/clocks-timing/timing-commander-software-download-
resource-guide)
2.5 PCIe x1 Gen2 Interface
Note: The PCIe data interface is available when using a PicoZed 7015 or 7030 SOM.
•The PCIe x1 interface is not required for normal operation. However, it has been
provided to assist in the development of PCIe based SOM products if desired. When
inserted into a PCIe slot, 12V power from the host PCIe slot can be used for low power
applications (10 Watts or less per the PCIe specification Version 1.1). The PCIe interface
includes a 12V power circuit, control signals and a single data lane (differential TX and
RX) and one differential PCIe clock.
For PCIe applications needing more than 10 Watts, use the included ATX-to-6P Mini-Fit
adapter. Connect the 6P end of the adapter to J2. Connect the 4-pin ATX connector to
the ATX power supply. This will provide supplemental 12V power to the PZCC-FMC-V2.
Figure 6 – ATX-to-6P Mini-Fit Adapter for Supplemental 12V PCIe Power

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•The PRSNT signals are used to identify the lane width (x1) of the PCIe bus for the host
motherboard. The carrier ties the PRSNT1# and PRSNT2# signals together to accomplish
this. The host motherboard has pull-up and pull-down resistors on these signals so the
carrier does not require any other special configurations to enumerate as a single lane
PCIe device when plugged into a host PC.
•The differential PCIe reference clock (PCIe_REFCLK_P/N) is routed directly to the JX3
header for SOM connectivity.
•The PCI Express transmit lanes are AC coupled (DC blocking capacitors are included in
the signal path) on the development board as required by the PCI Express specification.
Table 7 – GTP Pin Locations for PCI Express
2.6 FMC LPC Connector
A single Low Pin Count (LPC) FMC connector is implemented on the carrier board to support
FMC plug-in modules. The block diagram shows the MicroHeader connections to the FMC LPC
connectors. See Figure 7 – FMC Connections for topology overview.
When and FMC board is plugged in, the FMC_PRSNT_N and FMC_PRSNT_VADJ_N signals
are driven low per the FMC specification. The FMC_PRSNT_N signal is used to switch the
JTAG signals so the FMC card can be accessed through the JTAG interface. When a FMC
card is not present, FMC_PRSNT_N is pulled high via R104 and the JTAG interface is isolated
to the SOM only. See section 2.20, JTAG Interface.
The FMC_PRSNT_VADJ_N signal can be used as an indicator to the SOM that an FMC device
has been attached. This signal is located per the table below:
SOM Net Name: Carrier Net Name: JX3 Pin:
JX1_LVDS_2_N
FMC_PRSNT_VADJ_N
25
Table 8 – CP2104 Connections
There are four mounting holes in the FMC card area to facilitate secure FMC module mounting
and match the FMC specification. There are also no components directly under the FMC
mounting area on the top side of the board per the FMC specification.
SOM Net Name: Carrier
Net Name: JX3 Connection:
PCIE_RX0P
PCIE_RX0P
8
PCIE_RX0N
PCIE_RX0N
10
PCIE_TX0P
PCIE_TX0P
13
PCIE_TX0N
PCIE_TX0N
15
PCIE_REFCLK_P
PCIE_REFCLK_P
1
PCIE_REFCLK_N
PCIE_REFCLK_N
3
PCIE_RST_N
PCIE_RST_N
86

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The following guidelines have been observed in the layout of the FMC interface:
CLK_#_M2C
–50 ohm single-ended impedance
–Less than 10mil skew in P/N pair
–Connected to MRCC (Multi-Region)
–No length matching to any other feature
LA bus
–50 ohm single-ended impedance
–Less than 10mil skew in P/N pair
–Less than 100mil length skew across all bits in a bus
–LA Bus 0:16 located in bank 34 (7010/20), Bank 35 (7015/30).
–LA Bus 17:33 located in bank 35 (7010/20), Bank 34 (7015/30).
–CC Pairs 0, 17 on MRCC pins
–CC Pairs 1, 18 on SRCC pins
To conserve SoC pins, GA[1:0] pins are connected to header J9 – see Section 4.1 for
address selection.
Layout Routing Guidelines
•The signals for each header follow FMC routing tolerances and guidelines. Each of
the P/N pairs have 50Ωsingle-ended impedance (100Ωdifferential) with less than 10
mil skew between all P/N pairs on each header.
•There is less than 200 mil length skew across all bits in a bus or byte group, including
DQ and DQS pins in each bank.

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LA[2:16]_<P|N>
VADJ
VREF_A_M2C
FMC LPC Connector
MicroHeader
JX1
FPGA
Diff IO
VCCIO
VADJ
GBTCLK0_M2C_<P|N>
DP0_M2C_<P|N>
DP0_C2M_<P|N>
GA[0:1]
SCL
SDA
TDI
JTAG
HDR
TMS
TCK
J7
TDO
3P3V AUX
3P3V
12P0V
PRSNT_L
PG_C2M
Jumpers
MRCC
LA[19:33]_<P|N>
VADJ
VREF_A_M2C
JX2
VCCIO
VADJ
LA17_<P|N>_CC
LA18_<P|N>_CC
CLK0_M2C_<P|N>
LA00_<P|N>_CC
LA01_<P|N>_CC
CLK1_M2C_<P|N>
Not Connected
Not Connected
Not Connected
Not Connected
MRCC
SRCC
MRCC
MRCC
SRCC
FPGA
Diff IO
FPGA
SE IO FPGA
SE IO
Not Connected
TDI
TDI
TDO
TDO U2
FPGA
FMC_PRSNT_N
Figure 7 – FMC Connections
Note: The FMC slot SDA, SCL, and FMC_PRSNT signals are 3.3V levels. For this reason, level
translation is implemented to follow the VADJ level.

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2.7 SFP+ Interface – P1 (7015/30 SOM only)
The SFP+ interface is available to the 7015/30 SOM. The non-transceiver portion of the SFP+
interface is routed out to a vertical 0.1” connector (JSFP1). The SFP+ interface can be used
without JSFP1 as long as the SFP+ doesn’t require control signals. If the SFP+ does require
control signals, a loopback cable must be installed into JSFP1 and attached to the JZ PL
PMOD connector. This cable is available from Digilent.
http://store.digilentinc.com/2x6-pin-cable/
•JP2 is used to enable or disable the SFP+ transmit laser. When the jumper is placed,
the laser is enabled. When the jumper is removed, the laser is disabled unless a low is
written to JSFP1 Pin 2.
•D13 is the LOS (Loss Of Signal) indicator. It is silkscreened as “LINK” on the board.
This yellow LED will illuminate when a valid SFP+ link is established and maintained. It
will extinguish if there is not a link.
•NOTE: The PS_PMOD interface on the PicoZed SOM is, by default, set to eMMC
mode. To select between the PS_PMOD interface and the eMMC interface, please see
the SOM’s User Guide: http://picozed.org/support/documentation/4736
Figure 8 – SFP+ Interface connections
Figure 9 – SFP+ Control connections
Layout Note:
Place JSFP1 within 3" of PMODs
for loopback purposes.

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2.8 PS/PL PMOD™ Interfaces – JA, JB, JZ & JPS1
The carrier has four Digilent Pmod™ right angle 0.1” female sockets (2x6). Three connectors
are for the SoC’s PL (JA, JB, JZ) and one for the SoC’s PS (JPS1). These connections include
eight GPIO. The JA, JB, and JZ PL Pmods are powered via VCCO_13 (3.3V).
•Pmod™ Connections based on board type:
oPicoZed 7010: JPS1 Pmod only
oPicoZed 7020: JPS1, JA, JB Pmods
oPicoZed 7015/30: JPS1, JA, JB, JZ Pmods
•JPS1 - PS Pmod is attached to bank 500 and can be used as a general Pmod
interface, Processor (PJTAG) access or other hardened MIO peripherals (SPI, GPIO,
CAN, I2C, UART, SD, QSPI, Trace, Watchdog). Note that these Pmod signals are
muxed to eMMC on the PicoZed SOM.
•NOTE: The PS_PMOD interface on the PicoZed SOM is, by default, disabled as the
mux on the SOM is, by default, set to eMMC mode. To select between the PS_PMOD
interface and the eMMC interface, please see the SOM’s User Guide:
http://picozed.org/support/documentation/4736
JA Pmod™SOM Net Name: Carrier
Net Name: JX1 Connection: JA PMOD Pin Number:
JA
BANK13_LVDS_0_P
JA0-1_P
87
1
BANK13_LVDS_0_N
JA0-1_N
89
2
BANK13_LVDS_1_P
JA2-3_P
88
3
BANK13_LVDS_1_N
JA2-3_N
90
4
BANK13_LVDS_2_P
JA4-5_P
91
7
BANK13_LVDS_2_N
JA4-5_N
93
8
BANK13_LVDS_3_P
JA6-7_P
92
9
BANK13_LVDS_3_N
JA6-7_N
94
10
JB Pmod™SOM Net Name: Carrier
Net Name: JX3 Connection: JB PMOD Pin Number:
JB
BANK13_LVDS_8_P
JB0-1_P
74
1
BANK13_LVDS_8_N
JB0-1_N
76
2
BANK13_LVDS_9_P
JB2-3_P
79
3
BANK13_LVDS_9_N
JB2-3_N
81
4
BANK13_LVDS_10_P
JB4-5_P
80
7
BANK13_LVDS_10_N
JB4-5_N
82
8
BANK13_LVDS_11_P
JB6-7_P
85
9
BANK13_LVDS_11_N
JB6-7_N
87
10
JZ Pmod™
SOM Net Name:
Carrier
Net Name:
JX3
Connection:
JZ PMOD Pin
Number:
JZ
BANK13_LVDS_14_P
JZ0-1_P
92
1
BANK13_LVDS_14_N
JZ0-1_N
94
2
BANK13_LVDS_13_P
JZ2-3_P
91
3
BANK13_LVDS_13_N
JZ2-3_N
93
4
BANK13_LVDS_16_P
JZ4-5_P
98
7
BANK13_LVDS_16_N
JZ4-5_N
100
8
BANK13_LVDS_15_P
JZ6-7_P
97
9
BANK13_LVDS_15_N
JZ6-7_N
99
10
Table 9 – PL PMOD Pin Assignments

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v1.1
PS
Pmod™
SOM Net
Name:
Carrier
Net Name:
JX2
Connection:
JPS1 PMOD Pin
Number:
JPS1
MIO13
PSPMOD_D0
2
1
MIO10
PSPMOD_D1
1
2
MIO11
PSPMOD_D2
6
3
MIO12
PSPMOD_D3
5
4
MIO0
PSPMOD_D4
7
7
MIO9
PSPMOD_D5
8
8
MIO14
PSPMOD_D6
3
9
MIO15
PSPMOD_D7
4
10
Table 10 – JPS1 PS PMOD Pin Assignments
2.9 JX1, JX2 and JX3 SOM Interface MicroHeaders
The PicoZed Carrier has three 100-pin MicroHeaders (FCI, 61083-101400LF) for connection to
the SOM. The stack height is 5mm for each of these connectors.
•The JX1 and JX2 connectors interface power control signals, SOM reset, JTAG, PL (FMC
data/control, PB), PS Pmod, Ethernet, and HDMI signals to the SOM target.
•The JX3 connector interfaces SOM Ethernet, PCIe TX/RX/CLKs, microSD Card, 1 Wire MAC ID,
RTC interrupt, USB OTG, PL I/O, USB UART, Gigabit transceivers data and clocks (MGT/GTX),
and the jumper cabled SFP+ to the JZ PMOD header.
•The connectors are FCI 0.8mm BergStak®, 100 Position, Dual Row, BTB Vertical plugs. These
have variable stack heights from 5mm to 16mm, making it easy to connect to a variety of carrier
or system boards.
•Each pin can carry 500mA of current. The 5mm stack height is used on the PZCC-FMC-V2, and
PicoZed SOMs support I/O speeds up to 8 Gbps as shown in the following FCI customer
presentation:
BergStak® 0.8mm Mezzanine Connectors
Customer Presentation
June 2014
http://portal.fciconnect.com/Comergent/fci/documentation/customerpresentation/bergstak_customerpresentation.pdf
•The fastest supported rate in the PicoZed family exists with the 7030 member, whose Zynq
device/package can achieve 6.6 Gbps. This is within the operating rate of the BergStak
connectors.
•The carrier card powers the PicoZed PL VCCIObanks. This gives the carrier card the flexibility to
control the I/O bank voltages. On the PZCC-FMC-V2, both VCCO_34 and VCCO_35 are
powered from a single supply.VCCO_13 is powered from 3.3V.
•One signal in a Bank 34 differential pair (JX1_LVDS_2_P on 7010/20, JX2_LVDS_2_P on
7015/30) is shared with PUDC_B which is pulled down via a 1KΩresistor to ground.

20
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v1.1
Table 11 – MicroHeader JX1 and JX2 Overview
MicroHeader #1 (JX1) MicroHeader #2 (JX2)
Signal Name
Source
Pins
Signal Name
Source
Pins
PL
JX1 I/Os, for
7010/20: PUDC
on JX1.17 (pulled
up to VCCO_34),
PL_LED, PL_PB,
FMC_PRSNT_N,
HDMI (x9),
HDMIO I2C, FMC
SDA/SCL
Zynq Bank 34
or
Zynq Bank 35
50
##
PL
JX2 I/Os for
7015/30: PUDC is
on JX2.23. HDMI
(x14), FMC (x36
Diff).
Zynq Bank 35
or
Zynq Bank 34
50
++
Bank 13 I/Os Zynq Bank 13 8
**
Bank 13 I/Os:
PL_PB (x4),
PL_LED (x3)
Zynq Bank 13 7
**
JTAG
TMS_0
Zynq Bank 0
4
PS
PS MIO:
PMOD/eMMC
(x8), PG_MODULE
Zynq Bank 500 9
TDI_0 Zynq Bank 0
TCK_0 Zynq Bank 0
CTRL
VCCIO_EN Module/Carrier 1
No Connect No Connect 1
TDO_0 Zynq Bank 0
PWR
VADJ_34/35
Carrier
3
VADJ_13
Carrier
1
VIN_HDR
Carrier
5
GND
Carrier
23
CTRL
FPGA_DONE Zynq Bank 0 1
Total
100
Carrier_SRST#
Carrier. Drives bank
501.
1
PWR_Enable
Carrier
1
Power
VIN_HDR Carrier 4
GND
Carrier
23
VADJ_34/35
Carrier
3
FPGA_VBATT Carrier 1
N.C.
No Connects No Connects 4
TOTAL
100
** PicoZed 7015/7020/7030
## PicoZed 7010/7020 Bank 34 and PicoZed 7015/7030 Bank 35
++ PicoZed 7010/7020 Bank 35 and PicoZed 7015/7030 Bank 34