Avnet zedboard Quick guide

ZedBoard
(Zynq™Evaluation and Development)
Configuration and Booting Guide
Version 1.1
August 2012

ZedBoard Booting and Configuration Guide ISE Design Suite 14.1
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TableofContents
Introduction......................................................................................................................... 2
Reference Design Requirements......................................................................................... 2
Software.......................................................................................................................... 2
Hardware......................................................................................................................... 2
Hardware Design Block Diagram....................................................................................... 3
Supplied Files...................................................................................................................... 4
First Things First................................................................................................................. 5
Setting Up the ZedBoard Development Board............................................................... 5
Extract the Zip File ......................................................................................................... 6
PC Setup.......................................................................................................................... 6
Installing the UART Driver and Virtual COM Port ................................................... 6
Installing a Serial Console on a Windows 7 Host....................................................... 6
JTAG Configuration Mode................................................................................................. 7
Application Download.................................................................................................... 7
GPIO Test Demo............................................................................................................. 9
SDK Software Tasks......................................................................................................... 10
Create the SDK Workspace.......................................................................................... 10
Create the Board Support Package ............................................................................... 14
Import the GPIO Test Software Application................................................................ 16
Running the GPIO Test Software Application ............................................................. 18
Create the First Stage Boot Loader............................................................................... 23
Create the Boot Image .................................................................................................. 24
Booting From the SD Card............................................................................................... 26
Prepare the SD Card...................................................................................................... 26
GPIO Test Demo........................................................................................................... 27
Booting From QSPI Flash................................................................................................. 28
Program the QSPI Flash................................................................................................ 28
GPIO Test Demo........................................................................................................... 36
Where to Get More Information....................................................................................... 37
ZedBoard Website ........................................................................................................ 37
Xilinx Website.............................................................................................................. 37
Revision History ............................................................................................................... 37

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Introduction
This document provides an introduction to the available configuration and processor boot
modes of the Avnet ZedBoard development board. The example design used in this
guide is a basic ZynqTM -7000 All Programmable SoC design implemented and tested on
the Avnet ZedBoard development board. For more information about this provided
design or to build it for yourself please consult the ZedBoard: Zynq-7000 EPP Concepts,
Tools, and Techniques hands-on guide found at www.zedboard.org/design. Using this
example design this guide will show you how to use the JTAG configuration mode of the
ZedBoard as well as how to boot the processor and configure the programmable logic of
the Zynq-7000 device using the SD card and QSPI boot modes. The tasks performed in
this guide follow a logical progression such that it is expected that users will start at the
beginning and work their way toward the end.
Reference Design Requirements
Software
The software requirements for this reference design are:
Linux, Windows XP, Windows 7
(www.xilinx.com/ise/ossupport/index.htm)
Xilinx ISE Design Suite 14.1, with PlanAhead and SDK
Hardware
The hardware setup for this reference design is:
Computer with 1.1 GB RAM and 1.1 GB virtual memory (recommended)
(www.xilinx.com/ise/products/memory.htm)
Avnet ZedBoard development board
USB-A to micro-B cables
oUART
oJTAG
Power supply (12V)

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Hardware Design Block Diagram
The hardware platform for this guide is based on the Processor System (PS) configuration
and Programmable Logic (PL) bitstream described in the ZedBoard: Zynq-7000 EPP
Concepts, Tools, and Techniques hands-on guide found at www.zedboard.org/design.
The following figure shows a high-level block diagram of the hardware design. The
design requires:
Z7020 Zynq-7000 AP SoC
512MB DDR3 SDRAM
256Mbit QSPI Flash
USB UART Bridge Serial Port
LEDs and push button switches
Timer
Figure 1 – Reference Design Block Diagram

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Supplied Files
The following directory structure is included with this reference design:
boot_image: Empty folder to use to create new BOOT.BIN boot image.
demo: Contains the script files, boot image, and application executables:
BOOT.BIN: Boot image of First Stage Boot Loader (FSBL), PL bistream, and
GPIO test application.
bootimage.bif: Boot image information text file.
cp_from_sdk.bat: Batch file to copy hardware bitstream and software
executables from the SDK workspace.
gpio_test_0.elf: The golden ARM executable for the GPIO test application.
load_bits.tcl: TCL script to load the PL bitstream via XMD.
make_bootbin.bat: Batch file to run the command to create the boot image file.
ps7_init.tcl: TCL script to initialize the ARM processor.
run_gpio_test.bat: Batch file to run the commands to load the PL bitstream of
the hardware design, initialize the processor, and download the GPIO test
application.
run_uboot.bat: Batch file to run the commands to initialize the processor and
download the u-boot application.
system.bit: The golden FPGA bitstream of the hardware design required to run
the GPIO test application.
u-boot_autoboot_disabled.elf: The golden ARM executable for the u-boot
application used to program the QSPI Flash.
xmd.ini: Command file used by XMD to configure the PL with the hardware
bitstream, initialize the processor, and download the software applications.
zynq_fsbl_0.elf: The golden ARM executable for the Zynq FSBL.
doc: Contains documentation for this design:
ZedBoard_boot_guide_IDS14_1_v1_1.pdf: This document.
pa: Contains the PlanAhead hardware project and SDK workspace files and folders.
SDK_sw: Contains the GPIO test software application source files.
boot_image_golden.zip: Contains pre-built BOOT.BIN boot image for this design.
demo_golden.zip: Contains the golden copies of the files in the demo folder.

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First Things First
Setting Up the ZedBoard Development Board
Refer to the following figure and perform the following steps to set up the board for
running the applications.
Figure 2 - ZedBoard Development Board
1. Verify a jumper is installed on JP6 to enable the processor to boot from the SD card.
2. Plug a USB cable into the PC and the JTAG micro-B USB connector (J17).
3. Plug a USB cable into the PC and the UART micro-B USB connector (J14).
4. Plug the 12V power supply into the barrel jack (J20). Do not turn the board on.
JTAG
J17
UART
J14
Power
SW8
Configuration
ModePins
MIO[0]
JP6
12V
J20

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Extract the Zip File
Since you are reading this guide you have probably already extracted the zip file
associated with this tutorial guide. Using Windows™ Explorer navigate to the folder
where the zip file was extracted (<installation> folder). Make sure there are NO
SPACES in this path. The Xilinx SDK, which is used later in this guide, does not
tolerate spaces in this file path.
PC Setup
Follow the figure below to connect the ZedBoard to the development host PC to establish
the USB connections for the UART and JTAG programming.
PC
Micro
USB-B
USB Cable (UART)
Zedboard Development Board
Zynq
Z7020
AP SOC
Micro
USB-B
USB Cable (JTAG)
Figure 3 – Board Connection Setup
Installing the UART Driver and Virtual COM Port
If the ZedBoard development board has not been connected to the host PC before, it may
be necessary to install the software driver for the virtual COM port. The driver
installation for the Cypress CY7C64225 USB-UART bridge is described in detail in the
CY7C64225 Setup Guide available at
http://www.zedboard.org/sites/default/files/CY7C64225_Setup_Guide_1_1.pdf.
Installing a Serial Console on a Windows 7 Host
Starting with Windows 7, Microsoft no longer includes the HyperTerminal terminal
emulator software. However, this example design requires use of terminal emulation
software for a serial console connection to the ZedBoard Development Board. A suitable
free and open-source replacement for HyperTerminal is TeraTerm. Download and install
instructions for TeraTerm can be found at http://en.sourceforge.jp/projects/ttssh2. As an
alternative the Terminal applet in the Xilinx SDK may also be used.

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JTAG Configuration Mode
You can load the FPGA and run the example software application without building the
design by using the demo scripts and the pre-built hardware bitstream and software
application elf files. You must have the Xilinx tools installed on your host, and have the
hardware set up and connected as per the previous steps.
Application Download
1. Verify the ZedBoard is powered off and that the configuration Mode jumpers are set
for JTAG mode (all pins shunted to GND) as in the figure below:
2. Slide the power switch (SW8) to the ON position. You will see the green ‘power
good’ LED (LD13) illuminate.
3. Navigate to Control Panel Device Manager Ports (COM & LPT) and identify
the COM port connected to the ZedBoard. Start a serial terminal session for the
identified COM port and set the serial port parameters to 115200 baud rate, no parity,
8bits, 1stop bit and no flow control.
4. Open a command window in the <installation>\demo folder and enter:
run_gpio_test.bat
This batch file sets the proper environment variables and creates the xmd.ini script of
commands to be used by the Xilinx Microprocessor Debugger (XMD) tool to
program the PL bitstream, initialize the processor, download the application code, and
begin execution on the system by performing the following commands automatically:
source load_bits.tcl
connect arm hw
source ps7_init.tcl
ps7_init
dow gpio_test_0.elf
run
exit

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5. The FPGA bitstream will be downloaded, followed by the executable file for the
software application. Do not close the command window.
6. When the executable has finished loading and is ready to run you should see the
following in your serial terminal window:

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GPIO Test Demo
The GPIO Test application running on the ZedBoard takes user input to select which
push-button switch is used to trigger the timer to turn the LED on and off.
1. Follow the screen prompts to select the push button input. One push button is routed
to the AXI GPIO peripheral (BTNU) and the other is routed to the CPU GPIO
(BTNR) through the EMIO interface between the PS and PL sections. Run the
application as many times as you wish and alternate which push button is selected.
Leave the terminal window open when you are done. We will reuse this terminal
session again later.

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SDK Software Tasks
This aspect of the design is performed inside a SDK workspace. As you may know, the
Xilinx SDK is the Integrated Design Environment (IDE) where all software related tasks
are performed for both Linux and standalone (bare metal) software application
development. Here we will import the pre-built GPIO test software application that is
described in the ZedBoard CTT guide and create the Zynq First Stage Boot Loader
(FSBL) that we will copy to the SD card and boot on the ZedBoard.
Create the SDK Workspace
1. Start in PlanAhead to generate an empty SDK workspace based on the pre-built
hardware platform described in the ZedBoard CTT guide. Navigate the Windows™
Start Menu or double click on the icon on your desktop to open PlanAhead
and select Open Project.

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2. Navigate to the <installation>\pa\project_1 folder and select the project_1.ppr
project file. Click OK to continue.

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3. The project will open and display the Flow Navigator and Project Manager view
with the Project Summary. Select File Export Export Hardware… from the
PlanAhead GUI.
4. Accept the defaults and check the box to Launch SDK. Click OK to continue.
PlanAhead will display the following window while the SDK workspace is created:

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5. The SDK will open with a new empty workspace with just the imported
system_hardware_platform similar to the window shown below.
6. Make note of the base address for the DDR3 SDRAM (ps7_ddr_0 - 0x00100000)
and the QSPI Flash (ps7_qspi_0 - 0xE000D000). We will need to know this when
we program the QSPI Flash later when we prepare to boot the ZedBoard in QSPI boot
mode.

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Create the Board Support Package
The first thing we need to create in our empty workspace is a Board Support Package
(BSP) on which individual projects can be built. Multiple BSPs and multiple application
projects can be held in a single SDK workspace. To begin, create a basic BSP that is
adequate for the GPIO test and FSBL applications we intend to run.
1. From the SDK main menu, select File New Xilinx Board Support Package.
2. Accept the defaults for the Project name, Hardware Platform, CPU, and OS.
Click Finish to continue.

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3. At this point the basic software platform to build general applications for this board
has been created. We do not need to add additional software libraries to the BSP or
change any settings, so click OK to continue and the software platform will
automatically compile link.

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Import the GPIO Test Software Application
The GPIO test application is described in the Appendix A of the ZedBoard CTT and is
pre-built for us to use here. Feel free to examine and become familiar with the source
code for this application. The next step is to import this application so we can build and
run it on the board.
1. Go to File Import General Existing Projects into Workspace

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2. Click Browse… and navigate to the <installation>\SDK_sw\gpio_test_0 folder.
Check the box to Copy projects into workspace and click Finish to continue. The
software application will automatically build and be added to the SDK workspace.
At this point the gpio_test_0 application is ready to run, but first we must setup the Xilinx
Microprocessor Debugger (XMD) options to download and run the software application.

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Running the GPIO Test Software Application
1. Turn off the ZedBoard if it is turned on. Verify the Configuration Mode jumpers are
set for JTAG mode (all pins shunted to GND) as in the figure below:
2. Slide the power switch (SW8) to the ON position. You will see the green ‘power
good’ LED (LD13) illuminate.
3. To prepare for running the gpio_test_0 software application later we will configure
the Zynq device with the PL bitstream that includes the AXI timer and GPIO
peripherals. In the SDK main menu, select Xilinx Tools Program FPGA or click
on the on the SDK toolbar:

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4. Since this is a Zynq hardware platform there is no BMM file or ELF file to initialize
in Block RAM, so accept the default for the system.bit file for the PL bitstream that
was exported from the PlanAhead hardware project earlier. Click Program to
continue:
You will see the following window while the PL bitstream is downloaded. Once this is
complete the blue ‘DONE’ LED (LD12) will illuminate.