Broadcom BCM1250 User manual

USER MANUAL
BCM1250/BCM1125/BCM1125H
1250_1125-UM100CB-R
16215 Alton Parkway •P.O. Box 57013 •Irvine, CA 92619-7013 • Phone: [phone] •Fax:[phone]/02
User Manual for the BCM1250, BCM1125, and
BCM1125H

REVISION HISTORY
Revision Date Change Description
1250-UM100-R 06/25/01 Initial release.
1250-UM101-R 01/02/02 New Sections:
Section : “Interrupts” on page 47
Section : “ZBbus Cycle Count and Compare” on page 58.
Section : “Reduced Cache Size” on page 94.
Section : “Cache Configuration Register” on page 99.
Section : “DDR FCRAMs” on page 123.
Section : “HyperTransport Read Restrictions” on page 200.
Section : “HyperTransport Bounce Space” on page 213.
Section : “HyperTransport Differences from Revision 1.03 Specification” on page 224.
Section : “HyperTransport Differences from Revision 0.17 Specification” on page 222.
Section : “HyperTransport Target Done Counter” on page 236.
Section : “TCP Checksum Checking” on page 283.
Section : “Flow Control In Encoded Packet FIFO Modes” on page 294.
Section : “Restrictions When Resetting the Interface” on page 301.
Section : “Burst Mode” on page 371.
Section : “Early Chip Select” on page 373.
Section : “Transport Protocol Reset” on page 406.
Section : “Extended Protocol” on page 408.
Section : “BSRMODE - Holding Boundary Scan Active” on page 435.
New Tables:
Table 15, Table 48, Table 126, Table 127, Table 138, Table 139, Table 157, Table 203,
Table 212 and Table 214.

User Manual BCM1250/BCM1125/BCM1125H
10/21/02
Broadcom Corporation
Document 1250_1125-UM100CB-R Page iii
1250_1125-
UM100CB-R
10/21/02 This list summarizes the major changes between 1250-UM101 and 1250_1125-
UM100. The 1250_1125-UM100CB version of this manual has change bars indicating
all changes between the older and newer versions.
•Section 1: Updates to describe BCM1125/H
•Section 2: Updates to describe BCM1125/H.
•Section 3: Additional Clarifications and BCM1125/H descriptions
•New section: Error Conditions
•Section 4: Additional Clarifications and BCM1125/H descriptions
•Expanded section: Bus Watcher
•New Section: Magic Decoder Ring for Using The Trace Buffer
•Section 5: Updates for BCM1125/H
•New register: Level 2 Cache Settings Register
•Section 6: Additional Clarifications and BCM1125/H descriptions
•New Section: Memory Access Sequencing
•New Section: Example CHannel and Chip Select Configurations
•Updated guidelines: Timing Parameter Guidelines
•Section 7: Additional Clarifications and BCM1125/H descriptions
•New Section: Unaligned Buffer Descriptor Format for Ethernet DMA
•New Section: CRC and Checksum Generators
•Section 8: Additional Clarifications and BCM1125/H descriptions
•Section 9: Additional Clarifications and BCM1125/H descriptions
•New Section: Prepended Header Frame Format
•New Functionality: Destination Address Filtering
•New Functionality: Receive DMA Channel Selection
•New Functionality: Flow Control
•Section 16: Cross reference links added from register to defining table
•Index: Expanded
Revision Date Change Description

Broadcom Corporation
P.O. Box 57013
16215 Alton Parkway
Irvine, CA 92619-7013
© 2002 by Broadcom Corporation
All rights reserved
Printed in the U.S.A.
Broadcom®and the pulse logo®are trademarks of Broadcom Corporation and/or its subsidiaries in the United States and
certain other countries. All other trademarks are the property of their respective owners.

User Manual BCM1250/BCM1125/BCM1125H
10/21/02
Broadcom Corporation
Document 1250_1125-UM100CB-R Page v
TABLE OF CONTENTS
Section 1: Introduction........................................................................................................1
The SiByte Broadband Processor Family.................................................................................................. 1
The BCM1250................................................................................................................................................ 2
The BCM1125 and BCM1125H .................................................................................................................... 3
Audience ....................................................................................................................................................... 3
Other Documentation .................................................................................................................................. 4
Terminology.................................................................................................................................................. 5
Section 2: Signal Overview.................................................................................................7
BCM1250 Signal Groups ............................................................................................................................. 7
BCM1125/H Signal Groups.......................................................................................................................... 8
Section 3: System Overview ...............................................................................................9
Introduction .................................................................................................................................................. 9
Internal Registers....................................................................................................................................... 11
Coherence................................................................................................................................................... 12
Ordering Rules and Device Drivers .......................................................................................................... 14
CPU Speculative Execution ...................................................................................................................... 16
Error Conditions......................................................................................................................................... 17
Cache Error Exceptions ........................................................................................................................ 17
Bus Error Exceptions ............................................................................................................................ 18
CPU to CPU Communication (BCM1250 Only) ........................................................................................ 19
External Interrupts ..................................................................................................................................... 19
Overview of the ZBbus Protocol............................................................................................................... 20
Arbitration.............................................................................................................................................. 21
Address Phase...................................................................................................................................... 22
Response Phase................................................................................................................................... 23
Data Phase ........................................................................................................................................... 24
Reset ........................................................................................................................................................... 26
Clocks ......................................................................................................................................................... 31
Memory Map ............................................................................................................................................... 34
Section 4: System Control and Debug Unit.....................................................................41
Introduction ................................................................................................................................................ 41

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System Control ...........................................................................................................................................41
Mailbox Registers .......................................................................................................................................46
Interrupts .....................................................................................................................................................47
HyperTransport Interrupts .....................................................................................................................48
The Full Interrupt Mapper ......................................................................................................................50
Timers..........................................................................................................................................................57
Watchdog Timers ..................................................................................................................................57
General Timers......................................................................................................................................58
Timer Special Cases .............................................................................................................................58
ZBbus Cycle Count and Compare.........................................................................................................58
Timer Registers ....................................................................................................................................59
System Performance Counters .................................................................................................................61
Bus Watcher................................................................................................................................................64
Address Trapping.......................................................................................................................................67
Trace Unit ....................................................................................................................................................70
Trigger Events .......................................................................................................................................70
Trigger Sequences ................................................................................................................................73
Using the Trace Buffer...........................................................................................................................76
Reading the Trace Buffer ......................................................................................................................79
Magic Decoder Ring For Using The Trace Buffer .................................................................................81
Connections to the Trace Logic.............................................................................................................83
Trace Example 1: All CPU0 Activity ......................................................................................................84
Trace Example 2: Network Packet Headers..........................................................................................85
Section 5: L2 Cache .......................................................................................................... 89
Introduction.................................................................................................................................................89
Normal Operation .......................................................................................................................................89
Using the L2 Cache as Memory.................................................................................................................91
Standard RAM.......................................................................................................................................92
Memory Locked in the L2 Cache...........................................................................................................92
Comments on Using the L2 as Memory ................................................................................................93
Reduced Cache Size.............................................................................................................................94
Cache Management Access ......................................................................................................................94
Standard Management Mode Accesses (both ECC_diag address bits zero) .......................................97
ECC Diagnostic Management Accesses (ECC_diag bits nonzero) ......................................................98

User Manual BCM1250/BCM1125/BCM1125H
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Broadcom Corporation
Document 1250_1125-UM100CB-R Page vii
Cache Configuration Register............................................................................................................... 99
Example Startup Code to clear the L2 Cache....................................................................................... 99
Registers................................................................................................................................................... 100
Section 6: DRAM ..............................................................................................................103
Introduction .............................................................................................................................................. 103
A Comment on the term Bank............................................................................................................. 103
Memory Controller Architecture ............................................................................................................. 104
Memory Access Sequencing .............................................................................................................. 107
Clock Ratios and Clocking Scheme ....................................................................................................... 107
Memory Configurations........................................................................................................................... 109
Mapping .............................................................................................................................................. 109
Channel Select.................................................................................................................................... 109
Chip Select.......................................................................................................................................... 110
Example Channel and Chip Select Configurations ............................................................................. 112
Row, Column and Bank Configuration................................................................................................ 117
Choosing Interleave Parameters ........................................................................................................ 120
Page Policy ......................................................................................................................................... 122
Supported DRAMs and DIMMs........................................................................................................... 123
DDR SDRAMS............................................................................................................................. 123
DDR FCRAMs ............................................................................................................................. 123
DIMMs ......................................................................................................................................... 124
Larger Memory Systems..................................................................................................................... 124
ECC............................................................................................................................................................ 125
SDRAM Timing ......................................................................................................................................... 125
SDRAM Refresh........................................................................................................................................ 126
SDRAM Initialization and Commands .................................................................................................... 126
I/O Control................................................................................................................................................. 128
Timing Parameter Guidelines ................................................................................................................. 131
Performance Monitoring Features.......................................................................................................... 134
ZBbus Monitoring .................................................................................................................................... 134
Configuration Registers .......................................................................................................................... 135
Section 7: DMA.................................................................................................................147
DMA Controllers....................................................................................................................................... 147
Data Buffers and Descriptors ................................................................................................................. 147

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Broadcom Corporation
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Unaligned Buffer Descriptor format for Ethernet DMA ........................................................................154
DMA Coherence and Cache Options ......................................................................................................155
DMA Configurations .................................................................................................................................156
Ethernet and Serial DMA Engines...........................................................................................................157
Descriptor Count Watermarks .............................................................................................................157
Completion Interrupts ..........................................................................................................................158
Explicit Descriptor Interrupts................................................................................................................158
ASIC Mode Transfers..........................................................................................................................159
Option and Flag Bits for Ethernet MACs ............................................................................................171
Control and Flag Bits for Synchronous Serial Interface.......................................................................174
Data Mover ................................................................................................................................................176
Data Mover Operation .........................................................................................................................176
CRC and Checksum Generators.........................................................................................................178
Checksum Generation..................................................................................................................178
CRC Generation...........................................................................................................................179
Computation Sizes and Bandwidth ..............................................................................................180
Examples......................................................................................................................................181
Data Mover Control Registers .............................................................................................................184
Data Mover Descriptors.......................................................................................................................187
Section 8: PCI Bus and HyperTransport Fabric ........................................................... 190
Introduction...............................................................................................................................................190
PCI and HyperTransport Address Range ...............................................................................................192
Memory Mapped Devices....................................................................................................................194
HyperTransport Expansion Space.......................................................................................................194
Configuration Space............................................................................................................................194
PCI I/O Space......................................................................................................................................195
The SouthBridge, VGA and Subtractive Decode.................................................................................195
HyperTransport End Of Interrupt (EOI) Signaling Space ....................................................................198
Legacy Interrupt Acknowledge (IACK) Space .....................................................................................199
PCI Full Access Space ........................................................................................................................199
Special HyperTransport Space............................................................................................................199
HyperTransport Read Restrictions ......................................................................................................200
Endian Policies .........................................................................................................................................201
Little Endian System: No Swaps .........................................................................................................201

User Manual BCM1250/BCM1125/BCM1125H
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Broadcom Corporation
Document 1250_1125-UM100CB-R Page ix
Big Endian System: Match Byte Lanes............................................................................................... 202
Big Endian System: Match Bit Lanes.................................................................................................. 203
Viewing Endian Policy as an Optimization.......................................................................................... 204
Accessing the SiByte from PCI Devices ................................................................................................ 205
Accessing the SiByte from HyperTransport Devices ........................................................................... 210
Force Isochronous Mode Address Range ................................................................................... 212
Accessing the SiByte from a SiByte on a Double Hosted Chain......................................................... 212
HyperTransport Bounce Space........................................................................................................... 213
Performance of the PCI and HyperTransport Interfaces ...................................................................... 213
Accesses from the SiByte to the PCI or HyperTransport .................................................................... 214
Accesses from the HyperTransport to the SiByte ............................................................................... 216
Accesses from the PCI to the SiByte .................................................................................................. 217
PCI Adaptive Retry ...................................................................................................................... 217
Peer-to-Peer Accesses ............................................................................................................................ 219
PCI Bus To HyperTransport Fabric..................................................................................................... 219
HyperTransport Fabric to PCI Bus...................................................................................................... 221
PCI Arbiter ................................................................................................................................................ 222
PCI Interrupts ........................................................................................................................................... 222
HyperTransport Differences from Revision 0.17 Specification ........................................................... 222
HyperTransport Differences from Revision 1.03 Specification............................................................ 224
Ordering Rules.................................................................................................................................... 231
Using the PCI in Device Mode................................................................................................................. 232
Configuration of PCI and HyperTransport ............................................................................................. 234
HyperTransport Target Done Counter ................................................................................................ 236
Systems That Do Not Use HyperTransport......................................................................................... 236
Configuration Header Descriptions ..................................................................................................... 236
PCI Configuration Header................................................................................................................... 236
HyperTransport Configuration Header................................................................................................ 245
System Reset Initialization of the HyperTransport Interface............................................................... 256
Configuration Flags in the SriCmd Register................................................................................. 257
Timing Registers: SriRxDen, SriTxDen, SriRxNum and SriTxNum ............................................. 257
Receive Pointer Margin Control in SriCmd Register.................................................................... 258
Transmit Pointer Initial Offset in the SriCmd Register ................................................................. 259
Error Control Register .................................................................................................................. 259
Transmit Control Register ............................................................................................................ 259

BCM1250/BCM1125/BCM1125H User Manual
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Broadcom Corporation
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Buffer Control: TxBufCountMax and DataBufAlloc.......................................................................260
HyperTransport Resets .......................................................................................................................260
Section 9: Ethernet MACs .............................................................................................. 264
Introduction...............................................................................................................................................264
Interface Overview....................................................................................................................................265
Protocol Engine and GMII/MII ..................................................................................................................267
Ethernet Frame Format .......................................................................................................................268
Prepended Header Frame Format ......................................................................................................270
Protocol Engine Configuration.............................................................................................................271
Interface to PHY ..................................................................................................................................271
Transmitter Operation ..............................................................................................................................272
Transmitter Configuration ....................................................................................................................272
Transmit Path ......................................................................................................................................274
Receiver Operation...................................................................................................................................275
Receiver Configuration........................................................................................................................275
Receive Path .......................................................................................................................................277
Destination Address Filtering...............................................................................................................278
Receive DMA Channel Selection ........................................................................................................281
Packet Type Identification ...................................................................................................................282
IPv4 Header Checksum.......................................................................................................................283
TCP Checksum Checking ...................................................................................................................283
Packets Dropped by the DMA Channel...............................................................................................283
Flow Control..............................................................................................................................................284
Interrupts ...................................................................................................................................................286
Standard Interrupt Signaling................................................................................................................286
Split Interrupt Signaling .......................................................................................................................286
Management Interface to PHY .................................................................................................................287
RMON Counters ........................................................................................................................................289
Packet FIFO Interfaces .............................................................................................................................292
Flow Control In Encoded Packet FIFO Modes ....................................................................................294
8-Bit Packet FIFO Operation ....................................................................................................................294
8-Bit GMII Style Packet FIFO ..............................................................................................................295
8-Bit Encoded Packet FIFO.................................................................................................................296
8-Bit SOP Flagged Packet FIFO .........................................................................................................297

User Manual BCM1250/BCM1125/BCM1125H
10/21/02
Broadcom Corporation
Document 1250_1125-UM100CB-R Page xi
8-Bit EOP Flagged Packet FIFO......................................................................................................... 298
16-Bit Packet FIFO Operation ................................................................................................................. 299
16-Bit GMII Style Packet FIFO............................................................................................................ 299
16-Bit Encoded Packet FIFO .............................................................................................................. 300
Restrictions When Resetting the Interface ............................................................................................ 301
MAC Registers.......................................................................................................................................... 302
Section 10: Serial Interfaces ...........................................................................................321
Introduction .............................................................................................................................................. 321
Asynchronous Mode................................................................................................................................322
Baud Rate Generators ............................................................................................................................. 322
Operation .................................................................................................................................................. 323
Interrupts .................................................................................................................................................. 325
Loopback .................................................................................................................................................. 326
DUART Registers ..................................................................................................................................... 327
Synchronous Mode.................................................................................................................................. 337
Functional Overview ........................................................................................................................... 337
Input Line Interface ............................................................................................................................. 340
Input Using an External Enable ................................................................................................... 340
Input Using the Internal Sequencer ............................................................................................. 341
Output Line Interface .......................................................................................................................... 342
Output Using an External Enable ................................................................................................ 342
Output Using the Internal Sequencer .......................................................................................... 343
Synchronous Serial Protocol Engine..................................................................................................... 344
Operation in HDLC Mode.................................................................................................................... 344
Framing Parameters .................................................................................................................... 345
HDLC Transmitter........................................................................................................................ 345
HDLC Receiver............................................................................................................................ 347
Operation in Transparent Mode .......................................................................................................... 349
Transmitter in Transparent Mode ................................................................................................ 350
Receiver in Transparent Mode ....................................................................................................350
Synchronous Interface Configuration.................................................................................................... 351
DMA Configuration.............................................................................................................................. 351
FIFO Configuration ............................................................................................................................. 351
Protocol Engine Configuration ............................................................................................................ 351

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Broadcom Corporation
Page xii Document 1250_1125-UM100CB-R
Line Interface Configuration ................................................................................................................352
Synchronous Serial Interrupts ................................................................................................................352
Synchronous Serial Loopback ................................................................................................................352
RMON Counters ........................................................................................................................................353
Synchronous Serial Register Summary .................................................................................................354
Section 11: Generic/Boot Bus........................................................................................ 362
Introduction...............................................................................................................................................362
Overview....................................................................................................................................................362
Configuring a Chip Select Region...........................................................................................................363
Address Range....................................................................................................................................363
Cacheable Access Blocking ................................................................................................................364
Generic Bus Parity...............................................................................................................................364
Bus Width ............................................................................................................................................365
Generic Bus Timing .............................................................................................................................365
Fixed Cycle Read Access....................................................................................................................367
Fixed Cycle Write Access....................................................................................................................368
Acknowledgement Read Access .........................................................................................................369
Acknowledgement Write Access .........................................................................................................370
Burst Mode ..........................................................................................................................................371
Early Chip Select.................................................................................................................................373
Boot ROM Support ...................................................................................................................................373
Generic Bus Errors...................................................................................................................................374
Drive Strength Control .............................................................................................................................374
Generic Bus Registers ............................................................................................................................375
Section 12: PCMCIA Control Interface .......................................................................... 384
Introduction...............................................................................................................................................384
Connecting a PCMCIA Slot ......................................................................................................................384
Direct Connection of a Memory Only Card..........................................................................................385
Other PCMCIA Signals........................................................................................................................389
Using The PCMCIA Card ..........................................................................................................................390
Example PCMCIA Timings..................................................................................................................391
Using the Power Outputs.....................................................................................................................393

User Manual BCM1250/BCM1125/BCM1125H
10/21/02
Broadcom Corporation
Document 1250_1125-UM100CB-R Page xiii
Section 13: GPIO..............................................................................................................397
Introduction .............................................................................................................................................. 397
The GPIO Pins .......................................................................................................................................... 397
GPIO Registers ......................................................................................................................................... 399
Other Pins That Can Be Used ................................................................................................................. 401
Serial Ports ......................................................................................................................................... 401
PCI ...................................................................................................................................................... 401
MACs .................................................................................................................................................. 401
PCMCIA Power Control Pins .............................................................................................................. 401
Section 14: Serial Configuration Interface ....................................................................404
Introduction .............................................................................................................................................. 404
SMBus Overview ...................................................................................................................................... 404
Transport Protocol .............................................................................................................................. 404
Transport Protocol Reset .................................................................................................................... 406
SMBus Protocol .................................................................................................................................. 406
Extended Protocol............................................................................................................................... 408
Programming Model ................................................................................................................................410
Using SMBus Protocols ...................................................................................................................... 410
Using Extended Protocols................................................................................................................... 412
Direct Access ........................................................................................................................................... 413
Booting Using an SMBus EEPROM........................................................................................................ 413
Switching from SMBus Mode.............................................................................................................. 414
SMBus Registers...................................................................................................................................... 416
Section 15: JTAG and Debug..........................................................................................422
Introduction .............................................................................................................................................. 422
TAP Controller.......................................................................................................................................... 422
BYPASS Instruction ..................................................................................................................... 425
IDCODE Instruction ..................................................................................................................... 425
WAFERID Instruction................................................................................................................... 425
IMPCODE Instruction .................................................................................................................. 426
ADDRESS Instruction.................................................................................................................. 426
DATA Instruction.......................................................................................................................... 426
CONTROL Instruction.................................................................................................................. 426

BCM1250/BCM1125/BCM1125H User Manual
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Broadcom Corporation
Page xiv Document 1250_1125-UM100CB-R
EJTAGALL Instruction..................................................................................................................426
EJTAGBOOT Instruction ..............................................................................................................426
NORMALBOOT Instruction ..........................................................................................................427
SCAN Instructions (0x26 - 0x38)..................................................................................................427
SYSCTRL Instruction ...................................................................................................................427
TRACE Instruction........................................................................................................................430
PERF Instruction ..........................................................................................................................430
TRACECTRL and TRACECURCNT Instructions .........................................................................431
PROCESSMON Instruction..........................................................................................................432
Boundary Scan Register......................................................................................................................432
BSRMODE - Holding Boundary Scan Active.......................................................................................435
Processor and Probe Access ..................................................................................................................436
Processor Accesses to the JTAG Space.............................................................................................438
Probe Accesses to the ZBbus .............................................................................................................438
Address Register .................................................................................................................................439
Data Register.......................................................................................................................................439
EJTAG Control Register ......................................................................................................................440
Differences from EJTAG 2.5 (Feb. 22, 2000) Specification ...................................................................442
Section 16: Reference..................................................................................................... 446
Internal Register Addresses by Function...............................................................................................446
BCM1250/BCM1125/H Internal Registers Ordered by Address............................................................464

User Manual BCM1250/BCM1125/BCM1125H
10/21/02
Broadcom Corporation
Document 1250_1125-UM100CB-R Page xv
LIST OF FIGURES
Figure 1: BCM1250 Block Diagram .................................................................................................................... 2
Figure 2: BCM1125/H Block Diagram ................................................................................................................ 3
Figure 3: BCM1250 Signals................................................................................................................................ 7
Figure 4: BCM1125/H Signals ............................................................................................................................ 8
Figure 5: Logical Block Diagram of BCM1250 and BCM1125/H ........................................................................9
Figure 6: Internal Control and Status Register Alignment ................................................................................ 11
Figure 7: Decision Tree for Memory Space Address Accesses .......................................................................26
Figure 8: Clock Distribution Overview .............................................................................................................. 33
Figure 9: Memory Map ..................................................................................................................................... 35
Figure 10: Per-CPU Interrupt Mapper (replicated for each CPU; x = 0 or 1).................................................... 51
Figure 11: Connections to Trace Logic............................................................................................................. 83
Figure 12: Level 2 Cache Way Disable Access Address ................................................................................. 91
Figure 13: Cache Management Address.......................................................................................................... 95
Figure 14: Memory Controller Block Diagram ................................................................................................ 105
Figure 15: Chip Select Options....................................................................................................................... 110
Figure 16: Example Single Channel 128MB................................................................................................... 112
Figure 17: Example 1GB with two chip selects on one channel.....................................................................113
Figure 18: Example 1GB with two chip selects interleaved on one channel .................................................. 114
Figure 19: Example 1GB with two chip selects interleaved across both channels......................................... 115
Figure 20: Example 2GB with two chip selects interleaved on one channel .................................................. 116
Figure 21: Timing Relationships Set by DLLs ................................................................................................ 130
Figure 22: Nominal Windows at 133MHz for First Edge of DQS for Various Settings of [tCrD, tCrDh, tFIFO] ....
131
Figure 23: DMA Buffer.................................................................................................................................... 148
Figure 24: DMA Descriptor ............................................................................................................................. 149
Figure 25: Packet Spanning Three Buffers .................................................................................................... 150
Figure 26: DMA Descriptor Ring..................................................................................................................... 151
Figure 27: DMA Descriptor Chain................................................................................................................... 153
Figure 28: Standard and Unaligned Buffer DMA Descriptors......................................................................... 154
Figure 29: Packet Reception Flow using DMA ASIC Mode............................................................................159
Figure 30: ASIC Mode Address Generation ................................................................................................... 160
Figure 31: Sending the Whole Packet in ASIC Mode..................................................................................... 161
Figure 32: Sending a Packet Header in ASIC Mode ...................................................................................... 162

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Figure 33: Example 1 - TCP checksum a packet............................................................................................181
Figure 34: Example 2 - Preparing an iSCSI packet ........................................................................................182
Figure 35: Example 3 - Fragmenting an iSCSI packet....................................................................................183
Figure 36: PCI and HyperTransport Organization ..........................................................................................191
Figure 37: Address Ranges for CPU Access to PCI and HyperTransport......................................................193
Figure 38: Little Endian System ......................................................................................................................201
Figure 39: Match Byte Lane Endian Policy .....................................................................................................202
Figure 40: Match Bit Lane Endian Policy ........................................................................................................203
Figure 41: PCI BAR0 Address Mapping Table ...............................................................................................206
Figure 42: Default Host Mode Memory Map from PCI Bus Master.................................................................209
Figure 43: Memory Map From HyperTransport Device...................................................................................210
Figure 44: Buffers Used for Accesses from the ZBbus to PCI and HyperTransport.......................................214
Figure 45: Buffers Used for DMA Accesses from the PCI and HyperTransport .............................................216
Figure 46: PCI Adaptive Retry Parameters.....................................................................................................218
Figure 47: Buffers Used for PCI to HyperTransport Peer-to-Peer Accesses ..................................................220
Figure 48: Buffers Used for HyperTransport to PCI Peer-to-Peer Accesses..................................................221
Figure 49: Configuration Space Address ........................................................................................................234
Figure 50: HyperTransport Interface Clocks and FIFOs .................................................................................256
Figure 51: Ethernet Interface Block Diagram ..................................................................................................265
Figure 52: Ethernet Frame Format .................................................................................................................268
Figure 53: Prepended Header Format ............................................................................................................270
Figure 54: Transmit FIFO Thresholds.............................................................................................................272
Figure 55: Receive FIFO Thresholds ..............................................................................................................275
Figure 56: Receive Address Filter...................................................................................................................278
Figure 57: Receive Channel Selection............................................................................................................281
Figure 58: Selecting the Channel Offset .........................................................................................................281
Figure 59: MDIO Flows ...................................................................................................................................288
Figure 60: 8-bit Packet FIFO GMII Style .........................................................................................................295
Figure 61: 8-Bit Packet FIFO Encoded Style ..................................................................................................296
Figure 62: 8-Bit Packet FIFO SOP Style ........................................................................................................297
Figure 63: 8-Bit Packet FIFO EOP Style ........................................................................................................298
Figure 64: 16-Bit GMII Style Packet FIFO ......................................................................................................299
Figure 65: 16-Bit Encoded Packet FIFO ........................................................................................................300
Figure 66: UART Interrupt Generation ............................................................................................................325
Figure 67: Synchronous Interface Block Diagram ..........................................................................................338

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Document 1250_1125-UM100CB-R Page xvii
Figure 68: Example Reception Using RIN as Active High Enable (sampling on the falling clock edge) ........ 340
Figure 69: Example Reception Using RIN as Active High Sync (sampling on the falling clock edge) ........... 342
Figure 70: Example Transmission Using TIN as Active High Enable (Driving/Sampling on Rising Clock Edge).
343
Figure 71: Example Transmission Using TIN as Active High Sync (transition/sampling on rising clock edge) ....
344
Figure 72: Frame Address Matching .............................................................................................................. 347
Figure 73: Synchronous Serial Loopback Connections.................................................................................. 352
Figure 74: Fixed Cycle Read Access ............................................................................................................. 367
Figure 75: Fixed Cycle Write Access.............................................................................................................. 368
Figure 76: Acknowledge Read Access........................................................................................................... 369
Figure 77: Acknowledge Write Access ........................................................................................................... 370
Figure 78: Generic Bus Burst Read................................................................................................................ 371
Figure 79: Generic Bus Burst Write................................................................................................................ 371
Figure 80: Example PCMCIA Slot Connection ............................................................................................... 385
Figure 81: Example Flash Card Timing Diagram ........................................................................................... 392
Figure 82: Single GPIO Pin Diagram.............................................................................................................. 397
Figure 83: SMBus Signaling Start, Data Transfer and Stop ........................................................................... 405
Figure 84: JTAG TAP State Machine ............................................................................................................. 423
Figure 85: JTAG Boundary Scan Register Block ........................................................................................... 433
Figure 86: JTAG HyperTransport Output Boundary Scan Block .................................................................... 434
Figure 87: JTAG HyperTransport Input Boundary Scan Block....................................................................... 435
Figure 88: Example JTAG Probe Flowchart ................................................................................................... 437

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User Manual BCM1250/BCM1125/BCM1125H
10/21/02
Broadcom Corporation
Document 1250_1125-UM100CB-R Page xix
LIST OF TABLES
Table 1: ZBbus Agent IDs ............................................................................................................................... 20
Table 2: ZBbus Signals ................................................................................................................................... 20
Table 3: ZBbus Commands............................................................................................................................. 22
Table 4: ZBbus Level 1 Cache Attributes ........................................................................................................ 23
Table 5: ZBbus Byte Lane Assignments ......................................................................................................... 24
Table 6: ZBbus Data Status Codes ................................................................................................................ 24
Table 7: Operation of Different Reset Sources................................................................................................ 27
Table 8: Static Configuration Options.............................................................................................................. 27
Table 9: Core and HyperTransport Clock Settings.......................................................................................... 31
Table 10: Overview of BCM1250 Physical Address Map ................................................................................ 34
Table 11: Address Map Details ....................................................................................................................... 36
Table 12: System Identification and Revision Register ................................................................................... 42
Table 13: Part Revisions ................................................................................................................................. 42
Table 14: Manufacturing Information Register ................................................................................................ 43
Table 15: System Configuration Register........................................................................................................ 43
Table 16: Scratch Register .............................................................................................................................. 45
Table 17: Mailbox Registers ............................................................................................................................ 46
Table 18: Interrupt Mappings........................................................................................................................... 47
Table 19: Interrupt Message Format for Writes to interrupt_ldt_set Register.................................................. 49
Table 20: Delivery of HyperTransport Interrupts ............................................................................................. 49
Table 21: Interrupt Registers ........................................................................................................................... 52
Table 22: Interrupt Sources ............................................................................................................................. 52
Table 23: Watchdog Timer Initial Count Registers .......................................................................................... 59
Table 24: Watchdog Timer Current Count Registers ...................................................................................... 59
Table 25: Watchdog Timer Configuration Registers........................................................................................ 59
Table 26: General Timer Initial Count Registers ............................................................................................. 60
Table 27: General Timer Current Count Registers.......................................................................................... 60
Table 28: General Timer Configuration Registers ........................................................................................... 60
Table 29: ZBbus Count Register ..................................................................................................................... 61
Table 30: ZBbus Count Compare Registers.................................................................................................... 61
Table 31: System Performance Counter Configuration Registers...................................................................61
Table 32: System Performance Counters ....................................................................................................... 62

BCM1250/BCM1125/BCM1125H User Manual
10/21/02
Broadcom Corporation
Page xx Document 1250_1125-UM100CB-R
Table 33: System Performance Counter Sources ...........................................................................................62
Table 34: Bus Watcher Counters.....................................................................................................................64
Table 35: Bus Watcher Error Status Register..................................................................................................65
Table 36: Bus Watcher Error Status Debug Register ......................................................................................65
Table 37: Bus Watcher Error Data Registers...................................................................................................65
Table 38: Bus Watcher L2 ECC Counter Register...........................................................................................66
Table 39: Bus Watcher Memory and I/O Error Counter Register.....................................................................66
Table 40: Address Trap Trigger Index Register...............................................................................................68
Table 41: Address Trap Trigger Debug Register .............................................................................................68
Table 42: Address Trap Trigger Address Register ..........................................................................................68
Table 43: Address Trap Range Top Address Registers ..................................................................................68
Table 44: Address Trap Range Base Address Registers ................................................................................69
Table 45: Address Trap Configuration Registers .............................................................................................69
Table 46: Trace Event Register .......................................................................................................................72
Table 47: Trace Sequence Control Registers..................................................................................................74
Table 48: Trace Control Register.....................................................................................................................76
Table 49: Trace Buffer Address/Control Bundle ..............................................................................................77
Table 50: Trace Entry Format and Read Order ...............................................................................................79
Table 51: Decode of some TIDs for system revision PERIPH_REV3..............................................................81
Table 52: Encoded Byte Enables for CPU Transactions .................................................................................82
Table 53: Addresses for Memory Banks..........................................................................................................92
Table 54: Management Address......................................................................................................................95
Table 55: ECC Diagnostic Operations .............................................................................................................98
Table 56: Level 2 Cache Tag Register ..........................................................................................................100
Table 57: Level 2 Cache Settings Register....................................................................................................100
Table 58: Clock Speed...................................................................................................................................107
Table 59: Percent Deltas from Popular DIMM Frequencies...........................................................................108
Table 60: Mapping Physical Address To Memory Controller Address...........................................................109
Table 61: Address Bits Used by a Memory Channel .....................................................................................117
Table 62: Example for 128 MByte CS Region with 4K Rows, 1K Columns...................................................118
Table 63: Example for 128 MByte CS Region with 4K Rows, 1K Columns, 64 Byte Interleave....................118
Table 64: Example for 128 MByte CS Region with 4K Rows, 1K Columns, 128 Byte Interleave..................119
Table 65: Example for 256 MByte Region with 4K Rows, 1K Columns, two CS, and 128 Byte Interleave ...119
Table 66: Example for 512 MByte Region with 4K Rows, 1K Columns, four CS, and 128 Byte Interleave...119
Table 67: Example for 128 MByte + 64 MB + 64 MB Mixed_CS Mode .........................................................120