Changhong Electric PT4206 User manual

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PDP TELEVISION
SERVICE MANUAL
MODEL NO. PT4206
Please read this manual carefully before service.

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CONTENTS
Part:PP06 Chassis Features and Circuit………
Part:Introduction on Circuit Functions of PT4206 ……
Part:Analysis on Signal Process of PT4206………
Part:Typical Defectives and Repair of PT4206…………
Annex: 1Main Assembly Drawing&of PT4206
2Wire Connecting Drawing of PT4206
Part:PP06 Chassis Features and CBU Contents

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1.1PP06 Chassis Technical Specifications
1.1.1 PT4206 Panel Datas
PT4206 is the most typical model using PP06 chassis; therefore we take PT4206 as an example.
PDP Panel Resolution 852×3(RGB)×480
Colors 16,777,216
Dot Pitch 1.095mm(H)×1.110mm(V)
Brightness High brightness
Contrast High contrast
Lifespan of Panel 20000 Hours
Viewing Angle U/D160 / L/R160
Response Time 933mmH×533mm(V)
Remarks: Brightness and contrast may vary because of different panels being used.
PT4206 mainly uses SAMSUNG SDI panel model S42SD-YD04 or S42SD-YD05 
1.1.2 Specification Sheet
1.2Main Features
1.2.1 Terminals
RF Input 1Rear
S Terminal Input 1Rear
Recommended Input Format 640ЎБ
480/60Hz
800ЎБ 600/60Hz
Unsupportable Input Format
Indication Yes
Color Temp. Adjust. Yes
Quick Plug-In & Use Yes
PC
Picture Location Adjust. Yes
HD Signal
ЈЁ
YPbPrЈ© Compatible with 480PЎў
576PЎў 720P Ўў 1080i
HD Signal
ЈЁ
DVIЈ© Compatible with 480PЎў
576PЎў 720P Ў
ў
1080i and HDTV
Picture System PAL/NTSC/SECAM
Sound System D/KЎў
IЎў B/GЎў M
Digital Comb Filter Yes
3D Comb FilterЈЁ NTSCЈ©
Yes
Video
ЈЁ
Including
S-VideoЈ©
Movement Compensation Function Yes
Output Voltage 2ЎБ
5W
Audio Effect WOW
NICAM/IGR Yes
Video/YpbPr Audio Input Audio L/R
Audio
PC/DVI Audio Input Audio L/R
Input Voltage 220V~, 50Hz
Rating
Consumption
ЁQ
400W
Standby
Consumption
ЁQ
3W

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A/V Input RCA1Rear
YCbCr RCA1Rear
DTV YPbPr RCA1Rear
VGA/SVGA Input Hi-Density D-SUB 15 pin connector1Rear
DVI Input 1 Rear
A/V Output RCARear
Remarks: PT4206 is equipped with a service terminal, which service people can connect with
PC RS232 terminal to upgrade the software.
1.2.2 Working Condition Requirement:
Temperature 040
Humidity 2070
Working Condition Requirement
Altitude 02000m
1.2.3 Others
Tuning System FS Tuning236 Programs
NICAM Demodulation Yes
Audio Effect Process AV stereoSRS WOW5 Bands Equalizer
Picture Freeze TV/AV/S-VIDEO/YcbCr Only
On Screen Display Chinese/English, Menu Location movable by user.
Blue Background without Signal Yes
Power Saving When TV is connected with PC input, while there is no
signal from PC, after 60 seconds, TV will be automatically
off and enter into Power Saving Mode. Press any key on TV
or R/C, or there is signal from PC again, TV will be switched
on automatically.
Pixel Movement When this function is on, pictures will move on regularly to
protect the screen.
White Screen Display When this function is on, the screen will be completely white
to clear up slight shadowsplease see the instruction manual
for more details
Home/Commercial Mode Optional Users can choose between 15 minutes auto-off without signal
or 3 hours auto-off without operation please see the
instruction manual for more details
1.3CBU Content
1.3.1 PDP Inside Drawing:

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





r
ial No. Name
Front Cabinet
Filter Glass
Shelve Bar
PDP Panel Module
Down Cover Module etc.
Back Cabinet
Remarks: This drawing is for references only, please see the main assembly diagram
and wire-connecting diagram for details.
1.3.2 Circuit Content

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The main content of PP06 circuit include: Power Regulating Circuit, RF Circuit, VGA,
Analog Video, Digital Video Signal Processing Circuit, System Control Circuit, Button Control
Circuit. Reference drawing as below:
Part:Introduction on Circuit Functions of PT4206
2.1 Changhong PDP TV PT4206 main IC functions

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NO. NAME TYPE Function
1 N901 TDQ-6F7-FM2W Unify tuner
2 N601 MSP3410G-C12-100
Sound disposal
3 U705 TA2024 sound amplifier
4 U701 uPD64083GF-3BA NTSC 3D comb filter
5 N902 TEA6425D AV video switch
6 U1 VPC3230D-QA-B3 Digital video disposal
7 U6 MST9885 A/D converter
8 U11 SiI161BCT100 DVI signal disposal
9 U16 PW113-20Q Format transform and MCU
10 U17 AM29LV800BT-90 FLASH ROM
11 U22 DS90C383AMTD Difference transmit
12 U20 ST232CD RS-232 signal disposal
13 U7 24LC21A/SN E²PROMdisplay parameter information
14 U9/U13 SN74LVC126AD Suffer amplifier
15 U71 74LV32D Sync. face lifting enlarge
16 U8 24LC21A/SN E²PROMDVI parameter information
17 U19 24LC32A/SN E²PROMuser control information
18 U4 IS42S16400(A)-7T SDRAM
19 U5 PI5V330(Q) RGB/YpbPr switch
20 U3 PW1235 IP transform and picture improve
2.2Changhong PDP TV PT4206 main IC functions introduction
2.2.1 A/D converter MST9885 General
The MST9885 is a fully integrated analog interface for digitizing high-resolution RGB
graphics signals from PCs and workstations. With a sampling rate capability of up to 140 MHz,
it can accurately support display resolutions up to 1280x1024 (SXGA) at 75 Hz. The clamped
input circuits provide sufficient bandwidth to accurately digitize each pixel.
The MST9885B provides a high performance highly integrated solution to support the
digitization process, including the ADCs, a voltage reference, a PLL to generate the pixel
sampling clock from HSYNC, clamping
circuits, and programmable offset and gain circuits to provide brightness and contrast controls.
When the COAST signal is asserted, the PLL will maintain its output frequency when HSYNC
pulses are absent, such as during the VSYNC period in some systems.
A 32-step programmable phase adjustment control (0-360 deg) is provided for the pixel
sampling clock to adjust for the difference between the HSYNC edge and RGB pixel edge
timing.
The MST9885B can send output data through one 24-bit port at the pixel clock rate.
The MST9885B can also support R, G, B to Y, U, V conversion.
The MST9885B has internal programmable pattern generator for testing.
The MST9885B can accept either standard TTL, CMOS levels or sawtooth vertical deflection
signals for VSYNC input.
MST9885 Pin Function Descriptions
Pin(s) name Function
7077 RED0RED7 Red output data
29 GREEN0 Green output data

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GREEN7
1219 BLUE0BLUE7 Blue output data
67 DATACK Output data clock
66 HSOUT HSYNC output
65 SOGOUT Sync-on- Green Slicer output
64 VSOUT VSYNC output
37 MIDSCV Internal mid-scale voltage bypass
58 REFBYP Internal reference bypass
31 VSYNC Vertical SYNC input
30 HSYNC Horizontal SYNC input
43 BAIN Blue analog input
49 SOGIN Sync-on- Green analog input
48 GAIN Green analog input
54 RAIN Red analog input
29 COAST Hold PLL frequency and do not track HSYNC
38 CLAMP External clamp input(we connect it to ground 
55 A0 Serial interface address pin
56 SCL I2C busclock
57 SDA I2C busdata
33 FILT PLL connect to external filter
262739
424546
515259
62
AVDD Analog power
112223
697879 V33 Digital output power
3435 PVDD PLL power
1102021
242528
323640
414447
505360
616368
80
GND ground
MST9885 Block Diagram

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2.2.2VPC3230 General
VPC3230 Pin Function Descriptions
Pin No. Pin Name Short Description
13 R1G1B1IN RGB Analog Component Input 1
46 R2G2B2IN RGB Analog Component Input 2
76430
111225
356577
465168
80
GND GND
8 NC NC
9 VSUPCAP Supply Voltage, Digital Decoupling Circuitry
102936
4552 V33 Supply Voltage, Digital Circuitry
596976 AVCC Analog Voltage
13 SCL I2C Bus Clock
14 SDA I2C Bus Data
15 RESQ Reset Input
16 TEST Test Pin
17 VGAV VGAV Input
18 YCOEQ Y/C Output Enable Input
1923 FFIE NC
24 CLK20 Main Clock Output
27 LLC2 Clock Output
28 LLC1 NC
3134
3740 Y0Y7 YUV signal output (Digital ITU-R656 format)
4144
4750 C0C7 Digital chromatic signal output
53 INTLC Interlace scan control output (0-odd,1-even)
54 AVO Active Video Output
55 FSY/HC NC
56 MSY/HS Horizontal Sync Pulse output
57 VS Vertical Sync Pulse
58 FPDAT NC
60 CLK5 5 MHz Clock Output
61 NC NC
62 XTAL1 20.25M Analog Crystal Input
63 XTAL2 20.25M Analog Crystal Output
66 VRT Reference Voltage Top, Analog
67 I2CSEL I2C Bus Address Select
70 VOUT Analog Video Output
71 CIN Chroma /Analog Video 5 Input
72 VIN1 Video 1Analog Input
73 VIN2 Video 2Analog Input
74 VIN3 Video 3Analog Input
78 VREF Reference Voltage Top
79 FB1IN Fast Blank Input
VPC3230 Block Diagram

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2.2.3PW113 General
The PW113 integrates an industry-leading scaler, an advanced OSD engine, a flexible input
port system, system memory, and a powerful 80186-based horizontal and vertical image scaler
swith intelligent Auto Image Optimization circuitryThe Image Processor supports NTSC or PAL
video data with a 4:3 aspect ratio and 16:9 aspect ratio sources, such as DVD or HDTV. Video
Input formats can be in either YUV4:4:4 (24 bit) or YUV4:2:2 (16 bit) input modesThe PW113
uses an integrated PLL to synchronize the display interface timing to the input timingAn
integrated OSD controller supports sophisticated bit-mapped based OSDs The OSD controller
supports transparent, translucent, and fade-in/ fade-out functions.
Pin Function Descriptions
Pin(s) name Function
Video Port Pin Descriptions
71 VCLK VPort Pixel Clock input
74 VVS VPort Vertical Sync input
75 VHS VPort Horizontal Sync input
69 VFIELD VGPort Field Input
70 VPEN VPort Pixel Enable
4756 YUV0YUV7 VGPort ITUR656 Pixel Data.I/O port
We use 47 MUTE mute control 48 PW1230E
PW1235output enable49 VGASEL VGA/YpbPr select50
S1 sound system control51 DVIPD DVI interface standby
54 STANDBY power standby control56 RST1 peripheral
IC reset
Graphics Port Pin Descriptions
31 GCLK GPort Pixel Clock input
32 GVS GPort Vertical Sync input
33 GHSSOG GPort Horizontal Sync/GPort Sync- on-Green input
34 GPEN GPort Pixel Enable input

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35 GFBK GPort PLL Feedback / Line Advance Input
2027 GRE0GRE7 GPort Red Pixel Data input
10151819 GGE0 
GGE7 GPort Green Pixel Data input
29 GBE0GBE7 GPort Blue Pixel Data input
Display/Graphics Port Pin Descriptions
129136 DGR0DGR7 DGPort Red Pixel Data(odd outputs)
119122
125128 DGG0DGG7 DGPort Green Pixel Data(odd outputs)
111118 DGB0DGB7 DGPort Blue Pixel Data(odd outputs)
Display Port Pin Descriptions
106 DCLK DPort Pixel Clock output
108 DVS DPort Vertical Sync output
109 DHS DPort Horizontal Sync output
110 DEN DPort Pixel Enable output
96103 DR0DR7 DPort Red Pixel Data(even outputs)
8895 DR0DR7 DPort Green Pixel Data(even outputs)
7683 DB0DB7 DPort Blue Pixel Data(even outputs)
Microprocessor Interface Pin Descriptions
194 WR Write Enable low indicates a write to external RAM or other
devices
195 RD Read Enable low indicates a read to external RAM or other
devices
196 ROMOE ROM Output Enable low output indi cates a read from
external ROM.
197 ROMWE ROM Write Enable low indicates a write to external ROM.
198 CS0 Chip select signal
199 CS1 Chip select signal
193 NMI Non-maskable Interrupt
164173
184187
192
A1A19 Microprocessor address bus output bits
148163 D0D15 Microprocessor 16-bit bidirectional data bus
Peripheral Interface Pin Descriptions
207 PORTA0 DISPEN signal output(PDP display control)
206 PORTA1 READY signal inputPDP display ready
205 PORTA2 SDA
204 PORTA3 SCL
203 PORTA4 IR receive signal input
201 PORTA6 DVI digital interface select control
203 PORTA4 IR receive signal input
575860
64 PORTB0  PORTB7 Key control input
39 PORTC0 MA-EN enable control
40 PORTC1 480ISEL 480I anti-copy control
41 PORTC2 RST-1235 PW1235 reset
42 PORTC3 DIGSEL DVI digital interface select
43 PORTC4 LVDSON LVDS enable control
44 PORTC5 S0 sound system control
4546 PORTC6 
PORTC7 LED control
67 RXD Serial Receive Data
68 TXD Serial Transmit Data
Miscellaneous Pin Descriptions
142 TEST Test mode enable
139 RESET Bidirectional reset pin

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169 XI Crystal input
170 XO Crystal output
Power and Ground Pin Descriptions
16376584137185 VDD1 1.8V digital core power.
17386685138186 VSS Digital core ground
29527286104123140
171208 VDDQ3 3.3V digital I/O power.
130537387105124
141172 VSSQ Digital I/O ground.
165 VDDPA2 1.8V analog clock generator power.
166 VSSPA2 Clock generator analog ground.
167 VDDPA1 1.8V analog clock generator power.
168 VSSPA1 Clock generator analog ground.
PW113 Block Diagram
2.2.4PW1235 General
PW1235 supports standard digital video signal incorporates deinterlacing

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scaling .the PW1235 is able to effectively deinterlace video input by creating motion vectors that
follow frame-to-frame movement, and provide clear, progressive output in both analog and digital
formats. The PW1235 integrates input interfaceMEMORY control circuitpicture improve
output interface circuitI2C bus interface and so onall the function are controlled by I2C bus
Pin Function Descriptions
Pin(s) Name Function
Video Port Pin Descriptions
27 PVVS Primary Video (PV) Port vertical sync input.
28 PVHS Port horizontal sync input
25 PVCLK Port pixel clock input
26 CREF Video input clock reference
12 SVVS Port (ITU-R BT656 format) vertical sync input
11 SVHS Port (ITU-R BT656 format) horizontal sync input
13 SVCLK Port (ITU-R BT656 format) pixel clock input
30333538 VR0VR7 Video port red data input
15182023 VG0VG7 Video port green data input
1469 VB0VB7 Video port blue data input
Digital/Graphics (DG) Port Pins
68 DGCLK Digital/Graphics (DG) port pixel clock
67 DGVS Digital/Graphics (DG) port vertical sync.
66 DGHS Digital/Graphics (DG) port horizontal sync
91929495
97100 DGR0  DGR7 Digital/Graphics (DG) port red data
81848689 DGG0 
DGG7 Digital/Graphics (DG) port green data.
7073,7576
7879 DGB0  DGB7 Digital/Graphics (DG) port blue data
Analog Display Port Pin Descriptions
156 ADR Analog display port red (V/Pr) data
153 ADG Analog display port green (Y/Y) data
150 ADB Analog display port blue (U/Pb) data
161 VREFIN Reference voltage input.
162 VREFOUT Reference voltage output.
159 RSET Full-Scale adjust resistor
160 COMP Compensation pin
Digital Display Output Port Pin Descriptions
102 DCLK Digital display output port pixel clock
103 DVS Digital display output port vertical sync
104 DHS Digital display output port horizontal sync.
108 DENR Display pixel enable red/Vertical blanking period
(VBLANK)
106 DENG Display pixel enable green
107 DENB Display pixel enable blue/Horizontal blanking period
(HBLANK)
145 DEN Digital display output port output enable
132 133 
135 136 
138 139 
141142
DR0DR7 Digital display output port red data
121 122 
124 125 
127130
DG0DG7 Digital display output port green data.
110 111 
113 114 
DB0DB7 Digital display output port blue data.

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116119
Memory Pin Descriptions
229 MCLK SDRAM clock
223 MCLKFB SDRAM clock feedback
225 MRAS SDRAM row address strobe
226 MCAS SDRAM column address strobe
227 MWE SDRAM write enable
213210207204
203206209211
214217215220
221218
MA0 
MA13 SDRAM address bus
255252248245
242239236232
231234238241
244247250254
MD0 
MD15 SDRAM data bus
Host Interface Pin Descriptions
47 2WDAT SDA
45 2WCLK SCL
43 2WA1 Programmable two-wire serial bus address bit 1
44 2WA2 Programmable two-wire serial bus address bit 2
178179181186 MCUD0 
MCUD7 MCU data bus
168170172
174176177 PORTB1 MCU address bus
190 MCUCS Chip select
191 MCUWR MCUR/W signal
192 MCUCMD MCU command signal
188 MCURDY MCU Ready signal
Miscellaneous Pin Descriptions
56 TEST Test mode
144 TESTCLK Used for testing, can be used to supply display clock
55 RESETn Hardware asynchronous reset.
40 XTALI Crystal oscillator input
41 XTALO Crystal oscillator output
146 CGMS CGMS Enable
201 MVE Macrovision write protected enable
62, 63, 194,195 NC
System Power Pin Descriptions
5, 34, 93, 123,140,
175,205, 235 VDD Digital core power (2.5V).
19, 49, 77, 112,
134, 187, 219, 251 VSS Digital core ground.
14, 29, 42, 54, 64,
69, 80, 90, 101,
109, 120, 131, 143,
165, 180, 200, 208,
216, 224, 230, 237,
243, 249, 256
PVDD Digital I/O power (3.3V).
10, 24, 39, 46, 57,
65, 74, 85, 96, 105,
115, 126, 137, 147,
171, 189, 193, 202,
212, 222, 228, 233,
240, 246, 253
PVSS Ground.
60 MPAVDD Memory PLL analog power 2.5V.

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61 MPAVSS Memory PLL analog ground.
58 MPDVDD Memory PLL guard ring / digital power 2.5V.
59 MPDVSS Memory PLL guard ring / digital ground.
197 DPAVDD Display PLL analog power 2.5V.
196 DPAVSS Display PLL analog ground.
199 DPDVDD Display PLL digital power 2.5V.
198 DPDVSS Display PLL digital ground.
157 AVD33R Analog power (+3.3V) for R (V/Pr) channel.
154 AVD33G Analog power (+3.3V) for G (Y/Y) channel.
151 AVD33B Analog power (+3.3V) for B (U/Pb) channel.
158 AVS33R Analog ground for R (V/Pr) channel.
155 AVS33G Analog ground for G (Y/Y) channel.
152 AVS33B Analog ground for B (U/Pb) channel.
163 ADAVDD Analog power supply (+2.5V) for the analog display port.
164 ADAVSS Analog ground for the analog display port.
149 ADDVDD Digital power supply (+2.5V) for the analog display port.
148 ADDVSS Digital ground for the analog display port.
166 ADGVDD Guard ring power for the analog display port.
167 ADGVSS Guard ring ground for the analog display port.

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PW1235 Block Diagram 

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2.2.5TA2024 general:
The TA2024 is a 10W/ch continuous average two-channel Class-T Digital Audio Power
Amplifier IC using Tripath’s proprietary Digital Power Processing™ technology. Class-T
amplifiers offer both the audio fidelity of Class-AB and the power efficiency of Class-D
amplifiers.
Pin Function Descriptions
Pin(s) Name Function
2, 3 DCAP2, DCAP1 Charge pump switching pins
4, 9 V5D, V5A Digital 5VDC, Analog 5VDC
5, 8, 17 AGND1, AGND2, AGND3 Analog Ground
6 REF Internal reference voltage
7 OVERLOADB A logic low output indicates the input signal
has overloaded the amplifier
1014 OAOUT1, OAOUT2 Input stage output pins.
11, 15 INV1, INV2 Single-ended inputs
12 MUTE Mute control
16 BIASCAP Input stage bias voltage
18 SLEEP Sleep mode control
19 FAULT A logic high output indicates thermal
overload
20, 35 PGND2, PGND1 Power Grounds (high current)
22 DGND Digital Ground
24, 27; 31, 28 OUTP2 & OUTM2; OUTP1
& OUTM1 Bridged outputs
25, 26, 29, 30 VDD2, VDD2 VDD1,
VDD1 Supply pins for high current H-bridges,
nominally 12VDC.
13, 21, 23, 32, 34 NC Not connected
33 VDDA Analog 12VDC
36 CPUMP Charge pump output
1 5VGEN Regulated 5VDC source used to supply
power to the input section (pins 4 and 9).

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TA2024 Block Diagram
2.2.6DS90CF383A General
The DS90C383A/DS90CF383A transmitter converts 28 bits of CMOS/TTL data into four
LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is
transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit
clock 28 bits of input data are sampled and transmitted. At a transmit clock frequency of 65
MHz, 24 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME,
DRDY) are transmitted at a rate of 455 Mbps per LVDS data channel. Using a 65 MHz clock,
the data throughput is 227 Mbytes/
sec. The DS90C383A transmitter can be programmed for Rising edge strobe or Falling edge
strobe through a dedicated pin. The DS90CF383A is fixed as a Falling edge strobe transmitter.
Pin Function Descriptions
Pin(s) Name Function
1,9,17,26,34
44 VCC Power supply
5,13,21,29,53
33,35,36,43,49 GND Ground
2,3,50,51,52
54,55,56 DRE0DRE7 8bit red data input
4,6,7,11,12,14
8,10 DGE0DGE7 8bit green data input
15,19,20,22
23,24,8,16 DBE0DBE7 8bit blue data input

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27 HSYNC Horizontal Sync input
28 VSYNC Vertical Sync input
30 DE pixel display enable
31 TXCLK IN pixel display clock input
32 PWRDWN LVDS control
37,38,41,42
45,46,47,48 TXOUT+ TXOUT- 4 channels LVDS data signal output
39,40 TXCLKOUT+
TXCLKOUT- 1 channel LVDS clock signal output
DS90CF383 Block Diagram
2.2.7DVI Digital Receiver SiI161B
General
The Sil161B receiver uses Panel Link Digital technology to support high-resolution
displays up to UXGA. The Sil161B receiver supports up to true color panels (24 bit/pixel,
16.7M colors) in 1 or 2 pixels/clock mode. In addition, the receiver data output is time
staggered to reduce ground bounce that affects EMI. All Panel Link products are
designed on a scaleable CMOS architecture. This ensures support for future
performance requirements while maintaining the same logical interface. With this
scalable architecture, system designers can be assured that the interface will be fixed
through a number of technology and performance generations.

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Pin Function Descriptions
Pin(s) Name Function
90 RX0+ TMDS Low Voltage Differential Signal input data pairs
91 RX0- TMDS Low Voltage Differential Signal input data pairs
85 RX1+ TMDS Low Voltage Differential Signal input data pairs
86 RX1- TMDS Low Voltage Differential Signal input data pairs
80 RX2+ TMDS Low Voltage Differential Signal input data pairs
81 RX2- TMDS Low Voltage Differential Signal input data pairs
93 RXC+ TMDS Low Voltage Differential Signal input clock pair.
94 RXC- TMDS Low Voltage Differential Signal input clock pair.
4956 QO0QO7 8bit odd-pixel Blue output
5966 QO8QO15 8bit even-pixel Green output
6975,77 QO16QO23 8bit odd-pixel Red output
1017 QE0QE7 8bit even -pixel Blue output
2027 QE8QE15 8bit even -pixel Green output
3037 QE16QE23 8bit even -pixel Red output
99 RESERVED Must be tied HIGH for normal operation.
100 OCK_INV ODCK Polarity. A LOW level selects normal ODCK
output. A HIGH level selects inverted ODCK output.
1 HS_DJTR This pin enables/disable the HSYNC dejitter function.
To enable the HSYNC function this pin should be tied
high. To
2 PD Power Down (active LOW). A HIGH level indicates
normal operation. A LOW level indicates power down
mode.
3 ST Output Drive. A HIGH level selects HIGH output drive
strength. A LOW level selects LOW output drive
strength.
4 PIXS Pixel Select. A LOW level indicates one pixel (up to
24-bits) per clock mode using QE[23:0]. A HIGH level
indicates two pixels (up to 48-bits) per clock mode
using QE [23:0] for first pixel and QO[23:0] for second
pixel.
7 STAG_OUT
Staggered Output. A HIGH level selects normal
simultaneous outputs on all odd and even data lines.
A LOW level selects staggered output drive.
8 SCDT Sync Detect. A HIGH level is outputted when DE is
actively toggling indicating that the link is alive. A
LOW level is outputted when DE is inactive, indicating
the link is down.
9 PDO Output Driver Power Down (active LOW). A HIGH
level indicates normal operation. A LOW level puts all
the output drivers only (except SCDT and CTL1) into
a high impedance (tri-state) mode.
44 ODCK Output Data Clock. This output can be inverted using
the OCK_INV pin.
46 DE Output Data Enable.
47 VSYNC Vertical Sync input control signal.
48 HSYNC Horizontal Sync input control signal.
18,29,43,57,78 OVCC Output VCC
19,28,45,58,76 OGND Output GND
6,38,67 CVCC Digital Core VCC,
5,39,68 GND Digital Core GND.
82,84,88,95 DAVCC Analog VCC