CogniMem CM1K User manual

CM1K hardware
User’s Manual
Version 2.5.0
Revised 03/20/2013

CM1K Hardware User’s Manual 2
CM1K is a product of CogniMem Technologies, Inc.
Pertaining Patents
The CM1K integrated circuit uses the following patents:
Descriptions
US patent number
Issued date
Improved neuron circuit architecture
US5717832
02-10-1998
Circuit for pre charging a free neuron circuit
US5701397
12-23,-1997
Daisy-Chain circuit for serial connection of neuron circuits
US5710869
01-20-1998
Circuit for searching/sorting data in neural networks
US5740326
04-14-1998
Limitation of Liability
CogniMem Technologies, Inc. (CTI) assumes no liability whatsoever and disclaims any express, implied or statutory
warranty relating to the product described in this manual and accompanying materials (“Product”) including, but
not limited to, the implied warranty of merchantability, fitness for a particular purpose, or non-infringement. In no
event shall CTI be liable for any direct, indirect, consequential, punitive, special or incidental damages (including,
without limitation, damages for loss of profits, business interruption, or loss of information) arising out of the use
or inability to use the Product, even if CTI has been advised of the possibility of such damages. CTI makes no
representations or warranties with respect to the accuracy or completeness of the contents of this document and
reserves the right to make changes to specifications and product descriptions at any time without notice.
This Product is not designed, manufactured or intended by CTI for incorporation into products intended for use or
resale in equipment in hazardous, dangerous to life or potentially life-threatening environments, such as in the
operation of nuclear facilities, aircraft navigation or communication systems or direct life support machines, in
which the failure of products could lead directly to death, personal injury or severe physical or environmental
damage (“High Risk Activities”). The inclusion of the Product as critical component in High-Risk Activities implies
that the manufacturer assumes all risk of such use and in doing so agrees to fully indemnify CTI for any damages
resulting from such application.
Trademarks and Copyrights
This manual is copyrighted and published by CogniMem Technologies, Inc. All rights reserved. No parts of this
work may be reproduced in any form or by any means - graphic, electronic, or mechanical, including photocopying,
recording, taping, or information storage and retrieval systems - without the written permission of the publisher.
Products that are referred to in this document may be either trademarks and/or registered trademarks of the
respective owners. The publisher and the author make no claim to these trademarks.
Contact Information
HUwww.cognimem.comU

CM1K Hardware User’s Manual 3
1Table of Contents
1Table of Contents...................................................................................................................................................3
2Architecture of the CM1K ......................................................................................................................................6
2.1 Top Control logic ..........................................................................................................................................6
2.2 Cluster of Neurons .......................................................................................................................................7
2.3 Recognition stage (optional usage)..............................................................................................................7
2.4 I2C slave controller (optional usage)............................................................................................................7
3The neural network ...............................................................................................................................................8
3.1 A chain of identical neurons.........................................................................................................................8
3.1.1 Parallel access to the neurons .................................................................................................................8
3.1.2 Sequential access to the neurons ............................................................................................................8
3.2 The neuron parallel bus ...............................................................................................................................9
3.2.1 Command and control lines.....................................................................................................................9
3.2.2 Timings.....................................................................................................................................................9
3.3 The control registers ..................................................................................................................................11
3.3.1 Operation modes: Normal versus Save and Restore .............................................................................11
3.3.2 Register descriptions .............................................................................................................................11
3.3.3 Neuron behavior per instruction ...........................................................................................................15
3.3.4 Commands changing the RTL neuron in chain.......................................................................................16
3.4 Test Registers .............................................................................................................................................17
3.4.1 Description.............................................................................................................................................17
3.4.2 Usage .....................................................................................................................................................17
3.5 Programming sequences............................................................................................................................18
3.5.1 Vector broadcasting...............................................................................................................................18
3.5.2 Learn a vector ........................................................................................................................................19
3.5.3 Recognize a vector .................................................................................................................................21
3.5.4 Reading the number of committed neurons .........................................................................................24
3.5.5 Reading the contents of the neurons ....................................................................................................25
3.5.6 Reading the contents of a single specific neuron ..................................................................................26
3.5.7 Loading the contents of the neurons.....................................................................................................27
3.5.8 Typical operation latency.......................................................................................................................28
4The optional recognition stage ............................................................................................................................29
4.1 Control registers.........................................................................................................................................30
4.1.1 Recognition Status Register ...................................................................................................................30
4.1.2 Recognition output registers .................................................................................................................30
4.1.3 Video input registers..............................................................................................................................31
4.2 Programming sequences............................................................................................................................32
4.2.1 Size the region of interest......................................................................................................................32
4.2.2 Move the region of interest...................................................................................................................32
4.2.3 Recognize the region of interest............................................................................................................32
4.3 Timing constraints......................................................................................................................................33
5The optional I2C slave controller .........................................................................................................................34
5.1 Write sequence ..........................................................................................................................................34
5.2 Read sequence ...........................................................................................................................................35
5.3 Summary and Timing constraints...............................................................................................................35
5.4 I2C transmission codes...............................................................................................................................37
5.4.1 Bus Idle State .........................................................................................................................................37
5.4.2 Start Bit ..................................................................................................................................................37
5.4.3 Stop Bit...................................................................................................................................................37
5.4.4 Acknowledge Bit ....................................................................................................................................37
5.4.5 No-Acknowledge Bit ..............................................................................................................................37
6CM1K buses and control lines..............................................................................................................................38
6.1 Clocks, power-up and reset........................................................................................................................39

CM1K Hardware User’s Manual 4
6.1.1 G_Reset, global reset .............................................................................................................................39
6.1.2 G_CLK, system clock ..............................................................................................................................39
6.1.3 CS_, power saving control line...............................................................................................................39
6.2 Neural network BiDir lines (parallel bus) ...................................................................................................39
6.2.1 DS...........................................................................................................................................................40
6.2.2 RW_ .......................................................................................................................................................40
6.2.3 REG[4:0] .................................................................................................................................................40
6.2.4 DATA[15:0].............................................................................................................................................40
6.2.5 ID_..........................................................................................................................................................40
6.2.6 UNC_ ......................................................................................................................................................40
6.3 UNeural network input lines.........................................................................................................................41
6.3.1 S_CHIP....................................................................................................................................................41
6.3.2 DCI..........................................................................................................................................................41
6.4 Neural network output lines ......................................................................................................................41
6.4.1 DCO ........................................................................................................................................................41
6.4.2 RDY.........................................................................................................................................................41
6.5 Digital Input Bus .........................................................................................................................................42
6.5.1 RECO_EN................................................................................................................................................42
6.5.2 VI_EN .....................................................................................................................................................42
6.5.3 V_Clk, sensor Clock ................................................................................................................................42
6.5.4 V_FV.......................................................................................................................................................42
6.5.5 V_LV .......................................................................................................................................................42
6.5.6 V_DATA ..................................................................................................................................................43
6.6 Recognition stage output lines...................................................................................................................43
6.6.1 B_BSY .....................................................................................................................................................43
6.6.2 DIST_VAL................................................................................................................................................43
6.6.3 CAT_VAL.................................................................................................................................................43
6.7 UI2C serial bus ..............................................................................................................................................43
6.7.1 I2C_EN....................................................................................................................................................43
6.7.2 I2C_CLK ..................................................................................................................................................43
6.7.3 I2C_DATA ...............................................................................................................................................43
7Timing considerations..........................................................................................................................................44
7.1 Registers Access Latency............................................................................................................................44
7.1.1 Commands executing in multiple cycles (LCOMP, CAT and DIST) .........................................................44
7.1.2 Multiple read/write to the COMP register ............................................................................................45
7.2 Typical Timings Constraints........................................................................................................................45
7.2.1 Learn a vector ........................................................................................................................................45
7.2.2 Recognize a vector .................................................................................................................................46
7.2.3 Recognizing a vector received through the digital video bus ................................................................46
8Designing hardware with CM1K ..........................................................................................................................48
8.1 Single chip configuration............................................................................................................................48
8.1.1 Interface through the parallel bus (a)....................................................................................................48
8.1.2 Interface through serial bus (b) .............................................................................................................48
8.1.3 CM1K configuration lines.......................................................................................................................48
8.2 Multiple chip configurations ......................................................................................................................49
8.2.1 Control through parallel bus (a).............................................................................................................49
8.2.2 Control through serial bus (b)................................................................................................................49
8.2.3 UControl through parallel bus and separate recognition stages (c) ........................................................49
8.2.4 CM1K configuration lines.......................................................................................................................50
9Physical specifications .........................................................................................................................................51
9.1 Pinout.........................................................................................................................................................51
9.2 Mechanical specifications ..........................................................................................................................54
9.3 Electrical Specifications..............................................................................................................................55
9.3.1 CS_, power saving control line...............................................................................................................55
9.3.2 UPull-up resistors and power saving tips ................................................................................................55

CM1K Hardware User’s Manual 5
10 FAQ .................................................................................................................................................................56
10.1 Hardware design ........................................................................................................................................56
10.2 Operation ...................................................................................................................................................56
11 Appendix A: Heard about ZISC before? ..........................................................................................................57
12 Appendix B: Errata..........................................................................................................................................58
12.1 05-11-2012, RNCOUNT limited to 16-bit value ..........................................................................................58
12.2 08-03-2011, NID incorrect if firing neurons with same distance and category .........................................58
12.3 07-03-2012, Erroneous ID_line and NSR value when more than 416 neurons committed.......................59
13 What is new in this manual ?..........................................................................................................................61
13.1.1 Revision 03-20-13..............................................................................................................................61
13.1.2 Revision 01-09-13..............................................................................................................................61
13.1.3 Revision 08-23-12..............................................................................................................................61
13.1.4 Revision 08-03-2012..........................................................................................................................61
13.2 Revision 07/03/2012 ..................................................................................................................................61
13.3 Revision from 02/17/2012 .........................................................................................................................61
13.4 Revision from 11/1/2011 ...........................................................................................................................61
13.5 Revision from 10/19/2011 .........................................................................................................................61
13.6 Revision from 10/13/2011 .........................................................................................................................61

CM1K Hardware User’s Manual 6
2Architecture of the CM1K
CM1K is a high-performance pattern recognition chip featuring a network of 1024 neurons operating in parallel.
Also, the chip embeds a recognition engine ready to classify a digital signal received directly from a sensor.
The CM1K is composed of the following modules
-Top control logic (NSR and RSR registers, Ready and Busy control signals)
-Clusters of 16 neurons
-Recognition stage (optional usage)
-I2C slave (optional usage)
2.1 Top Control logic
-Synchronize communication between the clusters of neurons, the recognition state machine and the I2C
slave.
-Inter-module communication is made though a bi-directional parallel bus of 25 wires: data strobe (DS),
read/write (RW_), 5-bit register (REG), 16-bit data (DATA), ready (RDY)
-Inter-neuron communication also uses two additional lines indicating the global status of the neural
network: identified recognition (ID), uncertain recognition (UNC).
-Communication with external control unit can be made through the same parallel bus or the serial i2C
bus.

CM1K Hardware User’s Manual 7
2.2 Cluster of Neurons
-16 identical neurons operating in parallel.
-All neurons have the same behavior and execute the instructions in parallel independent from the cluster
or even chip they belong to.
-No controller or supervisor
-Selection of one out of two classifiers: K-Nearest Neighbor (KNN) or Radial Basis Function (RBF)
-Recognition time is independent of the number of neurons in use
oRecognition status in 2 clock cycles after the broadcast of the last vector component
oDistance and Category readout in 36 clock cycles per firing neuron
-Automatic model generator built into the neurons
oLearn in 18 clock cycles after the broadcast of the last vector component
-Save and Restore of the contents of the neurons in 258 clock cycle per neuron
-Simple Register Transfer Level instruction set through of 15 registers
-Most operations execute in 1 clock cycle except for Write LCOMP, Write CAT, Read CAT and Read DIST
which can take up to 19 clock cycles.
-Daisy-chain connectivity between the neurons of multiple CM1K chips to build networks with thousands
of neurons .
2.3 Recognition stage (optional usage)
-Enabled physically with RECO_EN pin and activated programmatically via a control command
-Vectors received through the digital input bus are continuously recognized and the response can be
snooped directly from control lines or is readable through registers.
-Recognition is made in 37 clock cycles from the receipt of the last component of a vector.
-If the input signal is a video signal, the vector is extracted by the recognition stage from a user-defined
region of interest.
2.4 I2C slave controller (optional usage)
-Enabled physically with I2C_EN pin
-Receives the serial signal on the I2C_CLK and I2C-DATA lines and convert it into a combination of DS, RW_,
REG and DATA signals compatible with the parallel neuron bus.

CM1K Hardware User’s Manual 8
3The neural network
The CogniMem chip is a fully parallel silicon neural network: it is a chain of identical elements (i.e. neurons)
addressed in parallel and which have their own “genetic” material to learn and recall patterns without running a
single line of code and without reporting to any supervising unit. In addition, the neurons fully collaborate with
each other though a bi-directional and parallel neuron bus which is the key to accuracy, adaptivity and speed
performance. Indeed each neuron incorporates information from all the other neurons into its own learning logic
and into its response logic.
The neurons can learn and recognize input vectors autonomously and in parallel. If several neurons recognize a
pattern (i.e. “fire”), their responses can be retrieved automatically in increasing order of distance (equivalent to a
decreasing order of confidence). The information which can be read from a firing neuron includes its distance,
category and neuron identifier. If the response of several or all firing neurons is polled, this data can be
consolidated to make a more sophisticated decision weighing the cost of uncertainty or else. Note that if a “best-
match” response is sufficient for an application, the CM1K chip comes with a recognition stage which is optimized
to return this limited response 38 clock cycles after the receipt of a vector on the digital input bus of the chip.
This paragraph gives a brief overview of the neural network functionality. For a detailed description of the
neuron’s behavior and their interactions, please refer to the manual CogniMem Reference Guide.
3.1 A chain of identical neurons
A neuron can have three states in the chain: IDLE, Ready-To-Learn (RTL) or COMMITTED. It becomes committed as
soon as it learns a pattern and its category register is written with a value different from 0. Its Daisy-Chain-Out
(DCO) control line automatically rises, changing its status from Ready-To-Learn to Committed. The next neuron in
the chain becomes the Ready-To-Learn. It has its Daisy-Chain-In (DCI) high and Daisy-Chain-Out (DCO) low.
The transfer of the DCI-DCO from one neuron to the next is activated the same way whether the two consecutive
neurons belong to a same cluster or not, and even belong to a same chip or not.
3.1.1 Parallel access to the neurons
All the neurons decode and execute the commands received through the neuron bus in parallel. This is a key
enabler of the CM1K chip to deliver a recognition time independent of the number of committed neurons in the
chain.
3.1.2 Sequential access to the neurons
The CM1K has the ability to save and restore the contents of its committed neurons, which is a representation of
the knowledge they have built autonomously by learning examples. In order to read the knowledge stored in the
neurons or load a knowledge file to the neurons, a special operation mode called Save and Restore allows
accessing the neurons sequentially in the chain.

CM1K Hardware User’s Manual 9
3.2 The neuron parallel bus
The neurons receive and execute instructions simultaneously through a bi-directional parallel bus composed of 26
lines:
3.2.1 Command and control lines
DS Data strobe line
RW_ Read/Write line (default is Read with RW_=1)
REG 5 bit register address
DATA 16-bit register data
RDY Ready control line mixing the ready output signal of all the neurons in the chain and indicating that
the neurons are all ready to execute a new command
ID_ Control line mixing the ready output signal of all the neurons in the chain and indicating that neurons
have identified the last vector and that these neurons are all in agreement for its classification.
UNC_ Control line mixing the ready output signal of all the neurons in the chain and indicating that neurons
have identified the last vector but that these neurons are in disagreement with its classification. This
line is an in/out line because used as an input during the execution of certain Write register.
The neurons sample a new command on the positive edge of the system clock and pull down their RDY line for the
duration of its execution. Upon completion, the RDY line is pulled back up on the positive edge of the system clock.
A Write command (DS, RW_=0, REG, DATA) must be stable on the positive edge of the system clock and released
before the next positive edge of the system clock.
A Read command (DS, RW_=1, REG) must be stable on the positive edge of the system clock and released before
the next positive edge of the system clock. DATA is stable when the RDY control line is pulled high.
3.2.2 Timings
Depending on the REG address and also the status of the neurons on the chain, the Read and Write commands can
take between 1 and 19 clock cycles.
Write in one cycle
(REG 0x06 is the MINIF register)
Read in one clock cycle
(REG 0x04 is the CAT register, read in this case in SR
mode)

CM1K Hardware User’s Manual 10
Write in two cycles
(REG 0x02 is the LCOMP register)
Remark: When the DS signal is asserted the DATA bus must be the input value (i.e. 0x000b). It then is switched to a
tri-state mode (i.e. 0xFFFF). During the second and last cycle of the Write LCOMP the firing neurons output their
category value and DATA represents their resulting bit-per-bit AND combination (i.e. 0x0001). If this value is
different from the category of one of the firing neurons, the UNC_L line is pulled down (not the case illustrated in
the above diagram)
Read in sixteen cycles
(REG 0x03 is the DIST register)

CM1K Hardware User’s Manual 11
3.3 The control registers
3.3.1 Operation modes: Normal versus Save and Restore
The Save-and-Restore (SR) mode is used to save and restore the contents of the neurons in the least amount of
time. This feature is essential to transfer knowledge bases between hardware platforms, but also make backup
prior to training on additional examples.
Under the SR mode, the neurons become dummy memories limited to the execution of read register and write
register functions taking one system cycle each. The automatic model generator and search and sort algorithm are
disabled. The SR mode is set in bit 4 of the NSR register.
3.3.2 Register descriptions
The following table describes the 15 registers controlling the entire behavior of the neurons. For a detailed
description of the neuron’s behavior and their interactions, please refer to the manual CogniMem Technology
Reference Guide.
Description
Addr
8-bit
Normal
mode
SR
mode
Data 16-bit/
Default
NSR
Network Status Register
Bit[1:0], reserved
Bit[2], UNC (Uncertain, read-only)
Bit[3], ID status (Identified, read-only)
Bit[4], SR status (default=normal)
Bit[5], KNN classifier (default=RBF)
The ID and UNC bits are updated internally after
each Write Last Comp command. ID is high if all
firing neurons report the same category. UNC is
high if several neurons fire but disagree with the
category.
KNN is a recognition mode and should not be
active while learning (since any pattern would be
recognized whatever its distance from a neuron,
the learning would create a single neuron)
*see Erratum and work around at the end of this
manual.
0x0D
RW
W
0x0000
GCR
Global Control Register
Bit [6:0]= Global Context Register
Bit[7]= Norm , 0 for L1, 1 for Lsup
0x0B
RW
0x0001
MINIF
Minimum Influence Field
0x06
RW
RW
0x0002
MAXIF
Maximum Influence Field
0x07
RW
0x4000

CM1K Hardware User’s Manual 12
Description
Addr
8-bit
Normal
mode
SR
mode
Data 16-bit/
Default
NCR
Neuron Context Register
In normal mode
Bit[15:8]=0x00
Bit[7:0] = neuron identifier bit [23:16]
In SR mode:
Bit[15:8] = neuron identifier bit [23:16]
Bit[7]= neuron Norm , 0 for L1, 1 for Lsup
Bit [6:0]= Context value between 0 and 127
0x00
RW
0x0001
COMP
Component
Bit[15:8] = unused
Bit[7:0]= byte component of the vector to learn
or recognize. The component index can range
between 0 to 255 and is incremented
automatically after each Read or Write. It is reset
after a Write LCOMP (see next register)
If the neuron is committed and its NCR=GCR:
Update the distance
register using the new
distance between the component value and the
neuron’s memory value with same index (the
norm is defined by bit 7 of the GCR).
If the
component index is zero, the distance register is
reset prior to being updated.
If the neuron is the Ready-To-Learn:
Write the component value to the neuron’s
memory value with same index.
0x01
W
RW
0x0000
LCOMP
Last Component
Bit[15:8] = unused
Bit[7:0]= last byte component of the vector to
learn or recognize. The component index can
range between 0 to 255 and is reset after
execution of this command.
If the neuron is committed and its NCR=GCR:
At the last cycle of this operation, the ID_ and
UNC_ lines and NSR register are updated to
report the recognition status of the vector.
Furthermore, if the status is identified (ID_ line is
low), the “identified category” is available on the
DATA bus.
0x02
W
0x0000

CM1K Hardware User’s Manual 13
Description
Addr
8-bit
Normal
mode
SR
mode
Data 16-bit/
Default
INDEXCOMP
Component index
Set the memory index to an input value which
can range between 0 and 255.
Note that this command does not reset the
distance register.
0x03
W
W
0x0000
DIST
Distance register.
This register is updated by the neuron.
Can range between 0 and 65535 (0xFFFF)
A distance 0 means that the vector matches
exactly the model of a firing neuron. The higher
the distance, the farther the vecto
r from the
model.
A distance of
0xFFFF means that no neuron
recognizes the last input vector.
Must be read after writing CM_LCOMP and
before reading CM_CAT
0x03
R
R
0xFFFF
CAT
Category register
Bit 15 is read-only and reserved to indicate if the
neuron is degenerated or not
Bits [14:0] represent the category value assigned
to the pattern learned by the neuron. This value
can range between 0 and 32766 (0x7FFE)
Remark about Write CAT
-Writing a category of 0 does not commit
a new neuron, but may force existing
committed neurons to reduce their
influence fields.
Remark about Read CAT
-Reading a category of 0xFFFF means that
no neuron is firing and that the last
broadcasted vector is a novelty.
-
If category is greater than 32768, it
indicates that the neuron recognizes the
last broadcasted vector, but is
degenerated (bit15=1) so its response
might be considered with caution. The
value must be masked with 0x7FFF to
report the original value learned by the
neuron.
Must be read after the DIST register except if the
ID_ line is low and the NID register does not need
to be read after the CAT register.
0x04
RW
RW
0xFFFF

CM1K Hardware User’s Manual 14
Description
Addr
8-bit
Normal
mode
SR
mode
Data 16-bit/
Default
AIF
Active Influence Field
In normal mode, this register is updated by the
learning logic of the neuron.
0x05
RW
0x4000
NID
Neuron Identifier
This register can be read after the category
register.
*bit[23:16] of the neuron identifier are stored in
the unused upper byte of the NCR register.
It is the subject of an Erratum at the end of this
manual.
0x0A
R
R
0x0000*
POWERSAVE
Dummy register
This register can be written to ensure that the
DATA lines are in tri-
state and do not draw
current from the pull-up resistors.
0x0E
W
n/a
FORGET
Clear the neuron’s category register, resetting its
status to idle. The value written to this register is
discarded.
Note that the neuron’s memory is not cleared,
but its index is reset to point at the first
component and this component will be
overwritten by the next Write COMP.
0x0F
W
n/a
NCOUNT
Normal mode: Number of committed neurons. Is
equal to 0xFFFF if all neurons of the chain are
committed.
SR mode
: Index of the neuron pointed in the
chain. This index increments automatically after
each Read or Write CAT, and is reset to 0 after a
Write RESETCHAIN
0x0F
R
R
0x0000
(see Errata)
RESET
CHAIN
Points to the first neuron of the chain. The value
written to this register is discarded.
0x0C
W
n/a

CM1K Hardware User’s Manual 15
3.3.3 Neuron behavior per instruction
The following table describes how the content of a neuron is updated depending on its state in the chain of
neurons. The content is divided into three types of items: memory, registers and control lines.
Memory
Idle
Ready to Learn
Committed
Component 0
Takes the value of the 1st Write
COMP occurring after a Write
LCOMP.
Can only be changed by a reset or
restore operation.
Reset the distance register
The memory index is incremented
by 1 to point to the next
component.
The memory index is incremented
by 1 to point to the next
component.
Component 1
Takes the value of the next Write
Comp or Write LCOMP.
Can only be changed by a reset or
restore operation.
The memory index is incremented
by 1 after a Write Comp, or is
reset to 0 after a Write LCOMP.
The memory index is incremented
by 1 after a Write Comp, or is reset
to 0 after a Write LCOMP.
…
Component 255
Takes the value of the next Write
Comp or Write LCOMP. The
memory index is reset to 0.
Can only be changed by a reset or
restore operation.
Registers
Idle
Ready to Learn
Committed & nselect
Context
Takes the value of the
Write GCR.
Takes the value of the
Write GCR.
Current value is saved if
the neuron gets
committed after a Write
CAT.
Can only be changed by a
reset or restore
operation.
Minimum Influence Field
Takes the value of the
Write MINIF.
Takes the value of the
Write GCR.
Maximum Influence Field
Takes the value of Write
MAXIF.
Takes the value of the
Write GCR.
Distance
The difference between
the pointed Component
and the input value is
accumulated after each
Write Comp or Write
LCOMP.
Category
Value is written if no
committed neuron fires
and has its own category
equal to value.
The neuron status
switches from RTL to
Committed.
Active Influence Field
Inherits the smallest
distance value of the
firing neurons

CM1K Hardware User’s Manual 16
3.3.4 Commands changing the RTL neuron in chain
Memory cell index change
Normal mode
Save and Restore mode
Write COMP
Index + 1
Index + 1
Write LCOMP
Index =0
Write INDEXCOMP
Index=k
Index=k
Write TESTCOMP
Index + 1
Write NSR
Index=0
Index=0
Write CAT
Index=0
Read CAT
Index=0

CM1K Hardware User’s Manual 17
3.4 Test Registers
The following registers are used solely for the purpose of testing the memory of all the neurons in a minimum
number of clock cycles. TESTCOMP allows filling the memory of all the neurons in a chain in 256 cycles (i.e. one per
component). TESTCAT allows committing all the neurons in a chain in one cycle.
3.4.1 Description
Description
Addr
8-bit
Normal
mode
SR
mode
Data 16-bit
/Default
TESTCOMP
Test Component
Write the pointed component of all neurons
with the input value. Useful for test routines.
0x08
n/a
W
0x0000
TESTCAT
Test Category
Write the same category to all the neurons.
Useful for test routines.
Writing the value 0 to this register is equivalent
to writing the FORGET register except that it
does not reset the neuron count.
0x09
n/a
W
0x0000
3.4.2 Usage
The Write TESTCOMP and Write TESTCAT commands are used in the test benches written to test the CM1K HDL
design.
A typical usage example is the counting of the number of neurons in a chain of CM1K
Part 1: Commit all the neurons in 2 cycles
-Write NSR 0x10 Set the SR mode
-Write TESTCAT Value Commit all the neurons with a same category value
Part2: Read the category of the neurons until end of chain is reached
-Write RESETCHAIN Point to the 1st neuron in chain
-Ncount=0
-Do Loop
oRead CAT, cat
oNcount++
-Until cat=0xFFFF (Ncount-1) is the number of neurons in the chain
-Write NSR 0x00 Cancel the SR mode

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3.5 Programming sequences
This paragraph describes the typical programming sequences to use the neurons in standard mode and save and
restore mode.
-Broadcast a vector to all the neurons (whether to learn or recognize it)
-Recognize the last broadcasted vector
-Learn the last broadcasted vector
-Save the content of all the neurons
-Read the content of a specific neuron
-Load the content of the neurons
3.5.1 Vector broadcasting
The memory of the neurons is 256 bytes long so the vectors to learn or recognize can be composed of up to 256
components of 8-bit value.
1) Write Context (optional)
If the new vector must be associated to a context different than the current value of the Global Context or
if the distance norm coded in bit 7 of the context must be changed
2) Up to 255 Write Component
Write all the components of the input vector but the last one in the Ready-To-Learn.
For all the committed neurons with a context equal to the Global Context, their distance register is
updated after each Write Component according to the Norm in use.
3) 1 Write Last Component
For all the committed neurons with a context value equal to the Global Context register, their distance
register is updated and represents the distance between the input vector and the prototype stored in

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their memory. If the distance of a neuron is less than its influence field, the neuron “fires” meaning that it
is ready to respond to further inquiries such as a Read DIST or Read CAT commands.
Also at the end of the Write Last Component, the entire neural network has been able to evaluate if the
vector is recognized or not, and with uncertainty or not. Recognition exists is at least one neuron fires.
Uncertainty exists if at least two of the firing neurons have a different category register.
3.5.2 Learn a vector
All the neurons have their internal learning logic and teaching a vector is as simple as broadcasting its components
and then writing its category value. Optionally, the PowerSave register can be written to set the data lines in tri-
state mode so they do not draw current.
If this combined information (vector and category) represents novelty to the existing neurons, the Ready-To-Learn
neuron becomes committed. It stores the instructed category in its category register. Its influence field is set to
the smallest distance register of the committed neurons belonging to the same context, or the Minimum Influence
Field whichever is greater, or the Maximum influence field whichever is smaller.
The next neuron in the chain turns from idle to RTL (ready-to-learn).
If there are neurons which recognized the vector with a category other than the instructed category, they
automatically reduce their influence field to prevent such erroneous recognition in the future.

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Remark #1: If the network is full, a learning operation will have no effect. You can detect that all the neurons of
the network are already committed by executing the Read NCOUNT command which will then return the value
0xFFFF.
Remark #2: If an application requires to change learning settings such as the Minimum and Maximum Influence
Fields, this must be done prior to the broadcast of the vector to learn.
Remark #3: If the AIF of a neuron reaches the Minimum Influence Field, the bit 15 of its category register is set to
1. The neuron is said “degenerated”. It still reacts to input patterns as any other committed neuron but the bit 15
of its category indicates that the neuron was prevented from shrinking its AIF to a smaller value during training and
its response should be weighted differently than the response of another firing neuron which is not degenerated.
Example
Let’s take the example of an input vector equal to a series going from 00 to 99. This vector has a length of 100
components. Its first 99 components are written in sequence to the CM_COMP register and its last and 100th
component is written to the CM_LCOMP register.
Broadcast the vector, learn as category 33 and read the number of committed neurons.
Sequence
For (i = 0; i<99, i++) Write CM_COMP, Vector(i);
Write CM_LCOMP, Vector(99)
Write CM_CAT, 33
Read CM_NCOUNT, ncount
Ncount will not be incremented if a committed neuron with a category register equal to 33 already recognizes
Vector. Note that this does not mean that the content of the neurons has not changed. Indeed, no new neuron has
been committed but existing committed neurons may have reduced their influence fields.