CogniMem CM1K User manual

CM1K hardware
User’s Manual
Version 2.5.0
Revised 03/20/2013

CM1K Hardware User’s Manual 2
CM1K is a product of CogniMem Technologies, Inc.
Pertaining Patents
The CM1K integrated circuit uses the following patents:
Descriptions
US patent number
Issued date
Improved neuron circuit architecture
US5717832
02-10-1998
Circuit for pre charging a free neuron circuit
US5701397
12-23,-1997
Daisy-Chain circuit for serial connection of neuron circuits
US5710869
01-20-1998
Circuit for searching/sorting data in neural networks
US5740326
04-14-1998
Limitation of Liability
CogniMem Technologies, Inc. (CTI) assumes no liability whatsoever and disclaims any express, implied or statutory
warranty relating to the product described in this manual and accompanying materials (“Product”) including, but
not limited to, the implied warranty of merchantability, fitness for a particular purpose, or non-infringement. In no
event shall CTI be liable for any direct, indirect, consequential, punitive, special or incidental damages (including,
without limitation, damages for loss of profits, business interruption, or loss of information) arising out of the use
or inability to use the Product, even if CTI has been advised of the possibility of such damages. CTI makes no
representations or warranties with respect to the accuracy or completeness of the contents of this document and
reserves the right to make changes to specifications and product descriptions at any time without notice.
This Product is not designed, manufactured or intended by CTI for incorporation into products intended for use or
resale in equipment in hazardous, dangerous to life or potentially life-threatening environments, such as in the
operation of nuclear facilities, aircraft navigation or communication systems or direct life support machines, in
which the failure of products could lead directly to death, personal injury or severe physical or environmental
damage (“High Risk Activities”). The inclusion of the Product as critical component in High-Risk Activities implies
that the manufacturer assumes all risk of such use and in doing so agrees to fully indemnify CTI for any damages
resulting from such application.
Trademarks and Copyrights
This manual is copyrighted and published by CogniMem Technologies, Inc. All rights reserved. No parts of this
work may be reproduced in any form or by any means - graphic, electronic, or mechanical, including photocopying,
recording, taping, or information storage and retrieval systems - without the written permission of the publisher.
Products that are referred to in this document may be either trademarks and/or registered trademarks of the
respective owners. The publisher and the author make no claim to these trademarks.
Contact Information
HUwww.cognimem.comU

CM1K Hardware User’s Manual 3
1Table of Contents
1Table of Contents...................................................................................................................................................3
2Architecture of the CM1K ......................................................................................................................................6
2.1 Top Control logic ..........................................................................................................................................6
2.2 Cluster of Neurons .......................................................................................................................................7
2.3 Recognition stage (optional usage)..............................................................................................................7
2.4 I2C slave controller (optional usage)............................................................................................................7
3The neural network ...............................................................................................................................................8
3.1 A chain of identical neurons.........................................................................................................................8
3.1.1 Parallel access to the neurons .................................................................................................................8
3.1.2 Sequential access to the neurons ............................................................................................................8
3.2 The neuron parallel bus ...............................................................................................................................9
3.2.1 Command and control lines.....................................................................................................................9
3.2.2 Timings.....................................................................................................................................................9
3.3 The control registers ..................................................................................................................................11
3.3.1 Operation modes: Normal versus Save and Restore .............................................................................11
3.3.2 Register descriptions .............................................................................................................................11
3.3.3 Neuron behavior per instruction ...........................................................................................................15
3.3.4 Commands changing the RTL neuron in chain.......................................................................................16
3.4 Test Registers .............................................................................................................................................17
3.4.1 Description.............................................................................................................................................17
3.4.2 Usage .....................................................................................................................................................17
3.5 Programming sequences............................................................................................................................18
3.5.1 Vector broadcasting...............................................................................................................................18
3.5.2 Learn a vector ........................................................................................................................................19
3.5.3 Recognize a vector .................................................................................................................................21
3.5.4 Reading the number of committed neurons .........................................................................................24
3.5.5 Reading the contents of the neurons ....................................................................................................25
3.5.6 Reading the contents of a single specific neuron ..................................................................................26
3.5.7 Loading the contents of the neurons.....................................................................................................27
3.5.8 Typical operation latency.......................................................................................................................28
4The optional recognition stage ............................................................................................................................29
4.1 Control registers.........................................................................................................................................30
4.1.1 Recognition Status Register ...................................................................................................................30
4.1.2 Recognition output registers .................................................................................................................30
4.1.3 Video input registers..............................................................................................................................31
4.2 Programming sequences............................................................................................................................32
4.2.1 Size the region of interest......................................................................................................................32
4.2.2 Move the region of interest...................................................................................................................32
4.2.3 Recognize the region of interest............................................................................................................32
4.3 Timing constraints......................................................................................................................................33
5The optional I2C slave controller .........................................................................................................................34
5.1 Write sequence ..........................................................................................................................................34
5.2 Read sequence ...........................................................................................................................................35
5.3 Summary and Timing constraints...............................................................................................................35
5.4 I2C transmission codes...............................................................................................................................37
5.4.1 Bus Idle State .........................................................................................................................................37
5.4.2 Start Bit ..................................................................................................................................................37
5.4.3 Stop Bit...................................................................................................................................................37
5.4.4 Acknowledge Bit ....................................................................................................................................37
5.4.5 No-Acknowledge Bit ..............................................................................................................................37
6CM1K buses and control lines..............................................................................................................................38
6.1 Clocks, power-up and reset........................................................................................................................39

CM1K Hardware User’s Manual 4
6.1.1 G_Reset, global reset .............................................................................................................................39
6.1.2 G_CLK, system clock ..............................................................................................................................39
6.1.3 CS_, power saving control line...............................................................................................................39
6.2 Neural network BiDir lines (parallel bus) ...................................................................................................39
6.2.1 DS...........................................................................................................................................................40
6.2.2 RW_ .......................................................................................................................................................40
6.2.3 REG[4:0] .................................................................................................................................................40
6.2.4 DATA[15:0].............................................................................................................................................40
6.2.5 ID_..........................................................................................................................................................40
6.2.6 UNC_ ......................................................................................................................................................40
6.3 UNeural network input lines.........................................................................................................................41
6.3.1 S_CHIP....................................................................................................................................................41
6.3.2 DCI..........................................................................................................................................................41
6.4 Neural network output lines ......................................................................................................................41
6.4.1 DCO ........................................................................................................................................................41
6.4.2 RDY.........................................................................................................................................................41
6.5 Digital Input Bus .........................................................................................................................................42
6.5.1 RECO_EN................................................................................................................................................42
6.5.2 VI_EN .....................................................................................................................................................42
6.5.3 V_Clk, sensor Clock ................................................................................................................................42
6.5.4 V_FV.......................................................................................................................................................42
6.5.5 V_LV .......................................................................................................................................................42
6.5.6 V_DATA ..................................................................................................................................................43
6.6 Recognition stage output lines...................................................................................................................43
6.6.1 B_BSY .....................................................................................................................................................43
6.6.2 DIST_VAL................................................................................................................................................43
6.6.3 CAT_VAL.................................................................................................................................................43
6.7 UI2C serial bus ..............................................................................................................................................43
6.7.1 I2C_EN....................................................................................................................................................43
6.7.2 I2C_CLK ..................................................................................................................................................43
6.7.3 I2C_DATA ...............................................................................................................................................43
7Timing considerations..........................................................................................................................................44
7.1 Registers Access Latency............................................................................................................................44
7.1.1 Commands executing in multiple cycles (LCOMP, CAT and DIST) .........................................................44
7.1.2 Multiple read/write to the COMP register ............................................................................................45
7.2 Typical Timings Constraints........................................................................................................................45
7.2.1 Learn a vector ........................................................................................................................................45
7.2.2 Recognize a vector .................................................................................................................................46
7.2.3 Recognizing a vector received through the digital video bus ................................................................46
8Designing hardware with CM1K ..........................................................................................................................48
8.1 Single chip configuration............................................................................................................................48
8.1.1 Interface through the parallel bus (a)....................................................................................................48
8.1.2 Interface through serial bus (b) .............................................................................................................48
8.1.3 CM1K configuration lines.......................................................................................................................48
8.2 Multiple chip configurations ......................................................................................................................49
8.2.1 Control through parallel bus (a).............................................................................................................49
8.2.2 Control through serial bus (b)................................................................................................................49
8.2.3 UControl through parallel bus and separate recognition stages (c) ........................................................49
8.2.4 CM1K configuration lines.......................................................................................................................50
9Physical specifications .........................................................................................................................................51
9.1 Pinout.........................................................................................................................................................51
9.2 Mechanical specifications ..........................................................................................................................54
9.3 Electrical Specifications..............................................................................................................................55
9.3.1 CS_, power saving control line...............................................................................................................55
9.3.2 UPull-up resistors and power saving tips ................................................................................................55

CM1K Hardware User’s Manual 5
10 FAQ .................................................................................................................................................................56
10.1 Hardware design ........................................................................................................................................56
10.2 Operation ...................................................................................................................................................56
11 Appendix A: Heard about ZISC before? ..........................................................................................................57
12 Appendix B: Errata..........................................................................................................................................58
12.1 05-11-2012, RNCOUNT limited to 16-bit value ..........................................................................................58
12.2 08-03-2011, NID incorrect if firing neurons with same distance and category .........................................58
12.3 07-03-2012, Erroneous ID_line and NSR value when more than 416 neurons committed.......................59
13 What is new in this manual ?..........................................................................................................................61
13.1.1 Revision 03-20-13..............................................................................................................................61
13.1.2 Revision 01-09-13..............................................................................................................................61
13.1.3 Revision 08-23-12..............................................................................................................................61
13.1.4 Revision 08-03-2012..........................................................................................................................61
13.2 Revision 07/03/2012 ..................................................................................................................................61
13.3 Revision from 02/17/2012 .........................................................................................................................61
13.4 Revision from 11/1/2011 ...........................................................................................................................61
13.5 Revision from 10/19/2011 .........................................................................................................................61
13.6 Revision from 10/13/2011 .........................................................................................................................61

CM1K Hardware User’s Manual 6
2Architecture of the CM1K
CM1K is a high-performance pattern recognition chip featuring a network of 1024 neurons operating in parallel.
Also, the chip embeds a recognition engine ready to classify a digital signal received directly from a sensor.
The CM1K is composed of the following modules
-Top control logic (NSR and RSR registers, Ready and Busy control signals)
-Clusters of 16 neurons
-Recognition stage (optional usage)
-I2C slave (optional usage)
2.1 Top Control logic
-Synchronize communication between the clusters of neurons, the recognition state machine and the I2C
slave.
-Inter-module communication is made though a bi-directional parallel bus of 25 wires: data strobe (DS),
read/write (RW_), 5-bit register (REG), 16-bit data (DATA), ready (RDY)
-Inter-neuron communication also uses two additional lines indicating the global status of the neural
network: identified recognition (ID), uncertain recognition (UNC).
-Communication with external control unit can be made through the same parallel bus or the serial i2C
bus.

CM1K Hardware User’s Manual 7
2.2 Cluster of Neurons
-16 identical neurons operating in parallel.
-All neurons have the same behavior and execute the instructions in parallel independent from the cluster
or even chip they belong to.
-No controller or supervisor
-Selection of one out of two classifiers: K-Nearest Neighbor (KNN) or Radial Basis Function (RBF)
-Recognition time is independent of the number of neurons in use
oRecognition status in 2 clock cycles after the broadcast of the last vector component
oDistance and Category readout in 36 clock cycles per firing neuron
-Automatic model generator built into the neurons
oLearn in 18 clock cycles after the broadcast of the last vector component
-Save and Restore of the contents of the neurons in 258 clock cycle per neuron
-Simple Register Transfer Level instruction set through of 15 registers
-Most operations execute in 1 clock cycle except for Write LCOMP, Write CAT, Read CAT and Read DIST
which can take up to 19 clock cycles.
-Daisy-chain connectivity between the neurons of multiple CM1K chips to build networks with thousands
of neurons .
2.3 Recognition stage (optional usage)
-Enabled physically with RECO_EN pin and activated programmatically via a control command
-Vectors received through the digital input bus are continuously recognized and the response can be
snooped directly from control lines or is readable through registers.
-Recognition is made in 37 clock cycles from the receipt of the last component of a vector.
-If the input signal is a video signal, the vector is extracted by the recognition stage from a user-defined
region of interest.
2.4 I2C slave controller (optional usage)
-Enabled physically with I2C_EN pin
-Receives the serial signal on the I2C_CLK and I2C-DATA lines and convert it into a combination of DS, RW_,
REG and DATA signals compatible with the parallel neuron bus.

CM1K Hardware User’s Manual 8
3The neural network
The CogniMem chip is a fully parallel silicon neural network: it is a chain of identical elements (i.e. neurons)
addressed in parallel and which have their own “genetic” material to learn and recall patterns without running a
single line of code and without reporting to any supervising unit. In addition, the neurons fully collaborate with
each other though a bi-directional and parallel neuron bus which is the key to accuracy, adaptivity and speed
performance. Indeed each neuron incorporates information from all the other neurons into its own learning logic
and into its response logic.
The neurons can learn and recognize input vectors autonomously and in parallel. If several neurons recognize a
pattern (i.e. “fire”), their responses can be retrieved automatically in increasing order of distance (equivalent to a
decreasing order of confidence). The information which can be read from a firing neuron includes its distance,
category and neuron identifier. If the response of several or all firing neurons is polled, this data can be
consolidated to make a more sophisticated decision weighing the cost of uncertainty or else. Note that if a “best-
match” response is sufficient for an application, the CM1K chip comes with a recognition stage which is optimized
to return this limited response 38 clock cycles after the receipt of a vector on the digital input bus of the chip.
This paragraph gives a brief overview of the neural network functionality. For a detailed description of the
neuron’s behavior and their interactions, please refer to the manual CogniMem Reference Guide.
3.1 A chain of identical neurons
A neuron can have three states in the chain: IDLE, Ready-To-Learn (RTL) or COMMITTED. It becomes committed as
soon as it learns a pattern and its category register is written with a value different from 0. Its Daisy-Chain-Out
(DCO) control line automatically rises, changing its status from Ready-To-Learn to Committed. The next neuron in
the chain becomes the Ready-To-Learn. It has its Daisy-Chain-In (DCI) high and Daisy-Chain-Out (DCO) low.
The transfer of the DCI-DCO from one neuron to the next is activated the same way whether the two consecutive
neurons belong to a same cluster or not, and even belong to a same chip or not.
3.1.1 Parallel access to the neurons
All the neurons decode and execute the commands received through the neuron bus in parallel. This is a key
enabler of the CM1K chip to deliver a recognition time independent of the number of committed neurons in the
chain.
3.1.2 Sequential access to the neurons
The CM1K has the ability to save and restore the contents of its committed neurons, which is a representation of
the knowledge they have built autonomously by learning examples. In order to read the knowledge stored in the
neurons or load a knowledge file to the neurons, a special operation mode called Save and Restore allows
accessing the neurons sequentially in the chain.

CM1K Hardware User’s Manual 9
3.2 The neuron parallel bus
The neurons receive and execute instructions simultaneously through a bi-directional parallel bus composed of 26
lines:
3.2.1 Command and control lines
DS Data strobe line
RW_ Read/Write line (default is Read with RW_=1)
REG 5 bit register address
DATA 16-bit register data
RDY Ready control line mixing the ready output signal of all the neurons in the chain and indicating that
the neurons are all ready to execute a new command
ID_ Control line mixing the ready output signal of all the neurons in the chain and indicating that neurons
have identified the last vector and that these neurons are all in agreement for its classification.
UNC_ Control line mixing the ready output signal of all the neurons in the chain and indicating that neurons
have identified the last vector but that these neurons are in disagreement with its classification. This
line is an in/out line because used as an input during the execution of certain Write register.
The neurons sample a new command on the positive edge of the system clock and pull down their RDY line for the
duration of its execution. Upon completion, the RDY line is pulled back up on the positive edge of the system clock.
A Write command (DS, RW_=0, REG, DATA) must be stable on the positive edge of the system clock and released
before the next positive edge of the system clock.
A Read command (DS, RW_=1, REG) must be stable on the positive edge of the system clock and released before
the next positive edge of the system clock. DATA is stable when the RDY control line is pulled high.
3.2.2 Timings
Depending on the REG address and also the status of the neurons on the chain, the Read and Write commands can
take between 1 and 19 clock cycles.
Write in one cycle
(REG 0x06 is the MINIF register)
Read in one clock cycle
(REG 0x04 is the CAT register, read in this case in SR
mode)

CM1K Hardware User’s Manual 10
Write in two cycles
(REG 0x02 is the LCOMP register)
Remark: When the DS signal is asserted the DATA bus must be the input value (i.e. 0x000b). It then is switched to a
tri-state mode (i.e. 0xFFFF). During the second and last cycle of the Write LCOMP the firing neurons output their
category value and DATA represents their resulting bit-per-bit AND combination (i.e. 0x0001). If this value is
different from the category of one of the firing neurons, the UNC_L line is pulled down (not the case illustrated in
the above diagram)
Read in sixteen cycles
(REG 0x03 is the DIST register)