Commodore A500 PLUS User manual

Produced By:
Commodore International Spare Parts GmbH
Braunschweig, West Germany
SERVICE MANUAL
•=»**•
A500 PLUS
INCLUDES A501 PLUS
RAM EXPANDER
OCTOBER, 1991 PN-400420-01
INTERNATIONAL EDITION
SERVICE POLICY AND PART NUMBER INFORMATION MAY VARY ACCORDING TO
COUNTRY. SOME PARTS MAY NOT BE AVAILABLE IN ALL COUNTRIES.
ri Commodore Business Machines, Inc.
1200 Wilson Drive, West Chester, Pennsylvania 19380 U.S.A.
Commodore makes no express or implied warranties with
regard to the information contained herein. The infor-
mation is made available solely on an as is basis, and the
entire risk as to completeness, reliability, and accuracy
is with the user. Commodore shall not be liable for any
damages in connection with the use of the information
contained herein. The listing of any available replacement
part herein does not constitute in any case arecommenda-
tion, warranty or guaranty as to quality or suitability of
such replacement part. Reproduction or use without ex-
press permission, of editorial or pictorial content, in any
matter is prohibited.
This manual contains copyrighted and proprietary information. No part
of this publication may be reproduced, stored in aretrieval system, or
transmitted in any form or by any means, electronic, mechanical, photo-
copying, recording or otherwise, without the prior written permission
of Commodore Electronics Limited.
Copyright ©1991 by Commodore Electronics Limited.
All rights reserved. Printed in U.S.A.
Reprinted with permission of North American Philips

A500 PLUS SERVICE MANUAL
TABLE OF CONTENTS
SECTION 1—SPECIFICATIONS
A500 PLUS SPECIFICATIONS M
A501 PLUS SPECIFICATIONS 12
SECTION 2—THEORY OF OPERATIONS
AMIGA 500 PLUS MEMORY MAP. 2-1
A500 PLUS BLOCK DIAGRAM 2"2
THEORY OF OPERATION 2"3
8375 AGNUS 2MEG 2"7
8373 DENISE HI RES 2"n
8364 PAULA 2"12
GARY •-2"13
SECTION 3—TROUBLESHOOTING
MAIN ASSEMBLY DIAGRAM 3-1
SECTION 4—PARTS
A500 PLUS PCB ASSEMBLY 312812 4-1
A500 PLUS SHIPPING ASSEMBLIES 4-2
A500 PLUS MAJOR ASSEMBLIES 4"3
A500 PLUS PCB COMPONENTS :4"4
A501 PLUS SHIPPING ASSEMBLIES 4-5
A501 PLUS MAJOR ASSEMBLIES 4-6
A501 PLUS PCB COMPONENTS 4-7
SECTION 5—SCHEMATICS
A500 PLUS SCHEMATIC #312813, REV. 15-1
A501 PLUS SCHEMATIC #363835, REV. 5-11

ASOO PLUS SERVICE MANUAL
A500 PLUS SPECIFICATIONS
INTRODUCTION
The A500 Plus is afeature enhanced version of the A500 personal computer.
FEATURES
CPU: 7.16 MHz 68000 NTSC; 7.09 MHz 68000 PAL
Memory: 1Megabyte standard expandable to 2MB with addition of A501 Plus
Kickstart ROM: 512K (V2.04)
Mass Storage Memory: Internal, 3.5 inch FDD mounted on the right side, the same as the A500.
Additional Features: Real Time Clock (on-board) with battery backup.
APPEARANCE
The A500 Plus appearance shall be the same as the A500. Anew logo plate has been added to distinguish "A500"
from "A500 Plus". The color is the same light beige as the current A500.
WHAT'S ADDED
1Meg on-board memory expandable to 2Meg.
8375 FAT AGNUS which supports 2Meg. of Chip RAM
On-board Real Time Clock
8373 ECS Denise
Full ECS support
V2.04inROM
CUSTOM CHIPS
The A500 Plus shall contain the same custom chip set as the A500, except for the 8375 2Meg. FAT AGNUS and 8373
ECS Denise.
SYSTEM I/O
EXTERNAL SYSTEM I/O
External floppy, Serial, Parallel, Mouse, Joystick, Stereo Audio Ports
These Ports remain unchanged from their A500 counterparts.
MEMORY MAP
The A500 Plus Memory Map is the same as the A500 Memory Map.
1-1

A500 PLUS SERVICE MANUAL
A501 PLUS SPECIFICATIONS
DESCRIPTION
The A501 Plus is amemory expansion board for the Amiga 500 Plus personal computer. It has 1MB of "chip" memory
and interfaces directly to the A500 Plus memory expansion slot. Unlike the A501, the A501 Plus doesn't have aReal
Time Clock (RTC), the A500 Plus has abuilt-in RTC.
The A501 can be used in either the A500 or A500 Plus personal computer, has 512K of memory and includes aReal
Time Clock. The A500 maps the A501 into pseudo-fast memory while the A500 Plus maps it into chip memory. In
addition, when used in an A500 Plus system, the internal (built-in) RTC is selected.
Both the A501 and A501 Plus uses the same printed circuit board (PCB). In the A501 Plus, the RTC and refresh
feature components are not loaded.
MEMORY TYPE
The A501 Plus shall use 256K x 4 120ns DRAMs.
PIN DESCRIPTIONS
PIN
PIN NAME
+5
GND
XDRD (0-15)
XDRA (0-8)
/EXTICK
/XCLKS
/XOE
/XCASL
/XCASU
/XRAS1
/XRAS0
/XWE
NC
XD (0-3)
XA (2-5)
/XCLKRD
/XCLKWR
+12V
NUMBER
1-2, 51-52
3-4, 21-22,
53-54
5-20
23-31
32
33
34
35
36
37,
38
39
40, 56
41-44
45-48
49
50
55
SIGNAL
DIRECTION
I
I/O
I
O
I/O
I
I
I
I
DESCRIPTION
+5Volts
Signal Ground
Memory Data Bus
Memory Address Bus
Active low. When this signal is asserted, it allows the A500 to
detect the presence of an A501. The A501 Plus does not use
this signal.
Active low. When this signal is asserted, the external RTC is
selected. This signal is not used in the A501 Plus.
Active low. When this signal is asserted, data can be read from
the expansion memory.
Active low. This signal strobes the column address into DRAMs
and corresponds to the low byte of the data word.
Active low. This signal strobes the column address into the
DRAMs and corresponds to the high byte of the data word.
Active low. This signal strobes the row address into the DRAMs
and corresponds to the upper 512K of the expansion RAM.
Active low. This signal strobes the row address into the DRAMs
and corresponds to the lower 512K of the expansion RAM.
Active low. When this signal is asserted, data is written into
the expansion memory.
Not connected.
RTC Data bus. These lines are not used in the A501 Plus.
RTC Address Bus. These lines are not used in the A501 Plus.
Active low. When this signal is asserted, data can be read from
the RTC. This signal is not used in the A501 Plus.
Active low. This signal strobes the data and address into the
RTC. This signal is not used in the A501 Plus.
+12 Volts. This is used on the A501 to charge the battery. This
line is not used on the A501 Plus.
1-2

A500 PLUS SERVICE MANUAL
A501 PLUS SPECIFICATIONS (Continued)
FACTORY DEFAULT JUMPER SETTINGS
JP1 JP2A JP2B JP3 JP9
A501 1-2 shorted 1-2 open 1-2 open 1-2 shorted 1-2 open
2-3 shorted 2-3 shorted 1-2 shorted
1-1 open
2-2 open
AS01 Plus 1-2 shorted 1-2 shorted 1-2 shorted 1-2 shorted 1-2 open
2-3 open 2-3 open 1-2 shorted
1-1 open
2-2 open
Jumper
JP1
JP2A, JP2B
JP3
JP9
DIMENSIONS
Length:
Width:
Function
When 1-2 are shorted, /EXTICK detection is enabled. This jumper has no effect on the A501 Plus,
because it does not use /EXTICK detection.
When 2-3 are shorted (1-2 open), it enables the refresh feature in the A501. Refresh components
Ul 1-U13 must be loaded in the A501 .The refresh feature is only required on the A501 to compen-
sate for refresh deficiencies in older revs of the A500.
Swaps upper and lower bank DRAMs. When 1-2 are shorted (1-1 and 2-2 open), /XRASO and
/XRAS1 selects the lower and upper banks respectively. Conversely, when 1-1 and 2-2 are shorted,
/XRASO selects the upper bank while /XRAS1 selects the lower bank RAMs.
Overwrites /XCLKS. When 1-2 are shorted, /XCLKS is permanently enabled and the A501 (exter-
nal) RTC is always selected. This jumper is normally open. Selection of internal or external RTC
is done by the A500 or A500 Plus via the /XCLKS line. RTC components U9, U11-U13, C9,
C11-C13, C911, C913, R911-R915, D11-D9123, BT9, TC9 and Y9 must be loaded in the A501.
5.5 in.
3.5 in.
POWER
+5VDC
+12VDC
@330 mA MAX for A501 Plus
@280 mA MAX for A501
@15 mA MAX for A501
Not Used on A501 Plus
ENVIRONMENT
Operating Temperature to +55°C
Humidity Up to 90% without condensation
1-3

^^mmmmmimi
AMIGA 500 PLUS MEMORY MAP
OVERLAY
A500 PLUS SERVICE MANUAL
RESET VECTORS
512K
EXPANSION
RAM
REAL
TIME CLOCK
(OPTIONAL)
DISPLAY
RAM
001
01
100
'NAAA/VNAAAA/
expansion
Kaaaaaa/vwa/1
EXPANSION
EXPANSION
lAAA/WA/VAA/Nl
8520
BFE000
BFD000
C0000
C7FFFF
00
04
08
DC0000
DEFFFF s////////,
CROSS =RESERVED
z
DFF0000
CHIPS
CONFIG
CART
ROM
20
40
80
A0
CO
DO
E0
E8
F0
F8
FC
512K
8MEG
2MEG
2MEG
1/2 MEG
1/2 MEG
1/2 MEG
512 K
2MEG
1/2 MEG
2-1

8375 AGNUS (Continued)
A500 PLUS SERVICE MANUAL
28MHZ
CCKO
7MHZ
CDAC*
Clock Relations
CLOCK RELATIONS (Refer to Figure above)
SYMBOL MIN MA
2.4.1 28MHz clock cycle t28MC 34.57 35.27
2.4.2 28MHz clock high t28MHi 12.0 22.9
2.4.3 28MHz clock low t28MLo 12.0 22.9
2.4.4 CCK clock cycle tcyc 260 290
2.4.5 CCK clock high tch 130 150
2.4.6 CCK clock low tcl 130 150
2.4.7 CCK-CCKQ clock separation tcq 65 75
2.4.8 7MHz clock cycle t7MC 130 150
2.4.9 7MHz clock high t7MHi 65 75
2.4.10 7MHz clock low t7MLo 65 75
2.4.11 7MHz-CDACQ clock separation t7MQ 30 40
2.4.12 CCK to 7MHz delay tc7M 15
2.4.13 CCKQ to 7MHz delay tq7M 15
2.4.14 Clock rise time tr 10
2.4.15 Clock fall time tf 10
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2-10

Vmmm
A500 PLUS SERVICE MANUAL
8373 DENISE HI RES
MAIN FUNCTIONS
•Display data buffer, encode display object to RGB colors.
•Bitplane &Sprite display. Parallel data from data bus is retained in six (6) Bitplaae and eight pairs of Sprite
data buffers.
•Bitplane Data loaded and serialized during display activity.
•Sprite Data loaded during display inactivity —individual serialization occurs when Sprite position Compare logic
detects equality between the Sync Counter and any Sprite Position Register.
•Six (6) lines of Bitplane &eight (8) pairs of serial data go to Priority control logic which selects only one (1) of the
Sprites or one (1) of the separate Bitmap images to produce the five (5) bit color select code at its output. This five
(5) bit code then selects one of the thirty-two (32) color registers to produce the twelve (12) bit RGB video output.
•The Bitplane and Sprite serial lines also go to the Collision Detect Logic, which detects real time coincidence between
them, and sets appropriate bits in the Collision Storage register. This register is read and cleared by the 68000.
•The four (4) "mouse counters" are controlled by the two (2) mouse-joystick connectors. These count the pulses
representing the horizontal and vertical motion of two (2) "mouse' 'controllers, and are read by the 68000.
CHIP ELEMENTS
32 Color Registers; Bitplane Priority and Control Registers; Color Select Decoder; Priority Control Logic; 16 Sprite Serial
Lines; Sprite Data Registers; Bit Plane Control Registers; Two (2) Mouse Connectors; Sprite Position Compare Logic;
Sprite Horizontal Control Registers; Bit Plane Serializer Collision Detect Logic; Collision Control Register; Collision
Storage Register; Buffer —Data Bus; Buffer —Register Address Decode; Bit Plane Data Registers Video: RGB; Sprite
Serialization.
IA
sz
ICOLLISION
DETECT
LOGIC
a
Q
(8x2
COLLISION
CONTROL
REGISTER
"TV
COLLISION
STORAGE
REGISTER
—
M
DB
HD1CO
RGA [n
D
v
BIT PLANE
SERIAL
BIT PLANE
0ATA REGISTER
(6)
A~~
A
8x2)
PRIORITY
CONTROL
LOGIC DCOLOR
SELECT
DECODE
32
COLOR
REGISTERS
SPRITE
SERIALIZE
SPRITE DATA
REGISTERS
(16) _
SPRITE
POSITION
COMPARE
LOGIC
A-
BIT PLANE
CONTROL
REGISTER
7\ CA
A
BIT PLANE
PRIORITY
&CONTROL
REGISTERS
7V*
H0RIZ
SYNC
COUNTER
£SPRITE
H0RIZ
POSITION
REGISTERS
ra
DATA BUS (16)
REGISTER ADDRESS DECODE
>-
CO o
cc
I—
CO
h-1
(12)
(4)
CO
O:
Denise Block Diagram
2-11

A500 PLUS SERVICE MANUAL
8364 PAULA
Paula is the Port, Audio and Uart chip. Its main function is the four audio channels. It also contains the I/O ports,
(Disk and Pots), Serial Port (Uart), and the Interrupt Control and Status Register.
DTOA CONVERTERS
The four audio channels each have aDMA pointer register, data register, period, (frequency), register and volume
register. Each channel has an on chip Dto A(digital to analog) converter on the output. The four channels are grouped
into aright and left audio output.
DISK CONTROL
The disk controller has registers for data read, data write and control. It also contains aPrecompensation Output
circuit, aData separator input circuit with adigital phase lock loop.
UART CONTROL
The serial port uart included in Paula contains Data registers, Control registers, Transmit, (TRN), and receive registers.
POT CONTROL
The four pot ports are general purpose I/O ports. They have counters for simple Ato D(digital to analog) conversion
of an external capacitor charging, which could also be used for analog joystick controllers.
INTERRUPT CONTROL
The audio, disk and uart controllers all set their own Interrupt Status register bits.
DMA REQUEST LOGIC
The audio and disk controllers also go to the DMA request logic, (remember: they are DMA users), causing the DMAL
signal to request DMA cycles from Agnus.
Left Right
Audio Audio
Output Output
Disk
Out In
UART
In Out
POT
Ports
DMAL
to Agnus DMA
Request
Logic
Interrupt
ID Code
to 68000
EXT.
Interrupt
Inputs
DB
f
<r
Int.
Control
Logic
Int.
Status
Registers
F03
CD
t
Dto A
Conv.
0& 1
Audio
Control
Counters
Data
Registers
~7V
Dto A
Conv.
2&3
Audio
Control
Counters
Data
Registers
Data
Sep
V
Pre
Comp
Disk
Control
Logic
Data
Registers
REC
AAAA
TRN
UART
Control
Logic
Data
Registers
±c ±c—ii—ii
Buffers
Latches
(Bi-Dir)
POT
Control
Counters
Data
Registers
Data Bus 16
RGA
o
0)
09
.Q
o
Register Address Decode 8
Paula Block Diagram
2-12

ASOO PLUS SERVICE MANUAL
GARY CUSTOM CONTROL CHIP
FEATURES
•Provides all bus control signals.
•Provides all address decoding.
•Generates the 68000 VPA signal.
•Handles some of the floppy circuitry.
•Provides keyboard reset interface.
GNDi -
vpa-
DEL"
DEB"
For signal descriptions,
k#312813, sheet 1of 10
KBRESET -
Vccl -
MTR"
DKWE -
DKWD-
LDS-
UDS
R/W-l
AS
BGACK -14
BLIT -15
1
2
3
4
5
6
7
8
9
10
11
12
13
SEL"
Vcc2"
16
17
18
19
20
21
22
CLKWR H23
GND2 -24
REGEN-
BLISS -
RAMEN -
ROMEN ~
CLKRD -
U5
GARY
48 -Vcc3
47 -MTRX
46 -MTRON
45 -DKWDB
44 -DKWEB
43 -DTACK
42 -HLT
41 -RST
40 -GND3
39 ^A23
38 -A22
37 -A21
36 -A20
35 -A19
34 -A18
33 -A17
32 -EXRAM
31 -XRDY
30 -OVL
29 -OVR
28 -CCK
27 -CCKQ
26 -CDAC
25 -LATCH
GARY BLOCK DIAGRAM
68000
Addresses 2_
(8)
Address Strobe (AS) —
UDS, LDS
Clocks
(C2, C3)
Override (OVR)
Overlay (OVL)
Processor read write
(PRW)
Expansion Board
Present (EXPEN)
DBR
XRDY
Override
(OVR)
>
Address
Decode
-*- RAM Enable (RAME)
-^ RGA Enable (RGAE)
Bus
Control
ROM Enable (ROME)
^Real time clock read
and write (RTCR, RTCW)
*- VPA
^CDR
*- CDW
+LATCH
Bidirectional
tri-state latch
control
*DTACK
-^ BLS
KReset
Keyboard Reset
Floppy Control
Logic
Reset
Control
+- Reset
+Halt
2-13

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A500 PLUS SERVICE MANUAL
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2-2

wmm
A500 PLUS SERVICE MANUAL
THEORY OF OPERATION
The AMIGA 500 Plus computer is ahigh-performance system with advanced graphics and audio features. The prin-
cipal hardware features consist of the 68000 microprocessor which runs at 7.2 MHz, 1MB RAM, expandable to 2MB,
and configurable to 8MB, 2parallel I/O chips, one control chip (GARY) and 3custom VLSI chips that provide the
unique capabilities for animation, graphics and sound.
68000 MICROPROCESSOR
The 68000 is the CPU of the system. All other resources are under software control via control data issued from it.
All 3custom chips have control registers that are written by the 68000.
The 68000 communicates with the rest of the computer via its address bus, data bus and control lines. Notice that
in the block diagram the 3custom chips do not reside directly on the 68000 buses. When the 68000 starts abus cycle
that is intended for the custom chips or the display RAM, the bus control chip detects whether or not the display
RAM buses are available. The control chip will not assert the acknowledge signal (/DTACK) back to the 68000 until
the display RAM buses are available. Once the 68000 receives /DTACK it completes the bus cycle. Connecting the
display RAM buses to the 68000 buses is discussed further in the section on bus control. Because the display RAM
is capable of approximately twice the bandwidth of the 68000, the 68000 is usually not delayed by waiting for the
display buses to become available.
The 68000 can fetch instructions from:
Display RAM
ROM
The 68000 can read and write data directly to:
Display RAM
Parallel I/O Chips
3Custom I.C.s
ROM
The 68000 transmits data and control to and from the peripherals via the parallel I/O and the 3custom chips.
7M is the processor clock to the 68000. CI, C3 and CDAC are used to clock the custom chips and determine the
timing of signals to the memory arrays.
ROM
The ROM contains the kernel and DOS routines; it is 128Kxl6.
PARALLEL I/O
The 2multipurpose 8520 I/O chips provide the following:
I/O to and from the parallel port connector
Control lines to and from the joystick/mouse ports
Acontrol line to the front panel LED
Internal control lines
Keyboard control lines, clock and data
Serial port control lines
Floppy disk interface control lines
Internal timers
These 2chips reside on the 68000 buses and are read and written by the 68000.
2-3

A500 PLUS SERVICE MANUAL
THEORY OF OPERATION (Continued)
CPU SIGNAL SUMMARY
SO S2 S4 S8 SO S2 S4 Sw Sw Sw Sw Sw Sw Sw Sw Sw Sw S8 SO S2 S4 Sw Sw Sw Sw Sw Sw S8 SO
CU( njTJiimnnjiJiimnjiJxiT^
A1-A23 y£2
AS \^
UDS ~\/V
3^:
j
/\
\r
*\ Normal Cycle \+ 68000 Peripheral Read Cycle
Machine Cycle
68000 Peripheral Write Cycle H
Signal Name
Address Bus
Data Bus
Address Strobe
Read/Write
Upper and Lower Data Strobes
Data Transfer Acknowledge
Bus Request
Bus Grant
Bus Grant Acknowledge
Interrupt Priority Level
Bus Error
Reset
Halt
Enable
Valid Memory Address
Valid Peripheral Address
Function Code Output
Clock
Power Input
Ground
*Open Drain
Mnemonic
A1-A23
D0-D15
AS
R/W
UDS, LDS
DTACK
BR
BG
BGACK
IPLO, IPL1, IPL2
BERR
RESET
HALT
E
VMA
VPA
FCO, FC1, FC2
CLK
Vcc
GND
Input/Output
Output
Input/Output
Output
Output
Output
Input
Input
Output
Input
Input
Input
Input/Output
Input/Output
Output
Output
Input
Output
Input
Input
Input
Active State
High
High
Low
Read-High
Write-Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
High
Low
Low
High
High
Three State
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No*
No*
No
Yes
No
Yes
No
AO is internal to 68000
2-4

^^
A500 PLUS SERVICE MANUAL
THEORY OF OPERATION (Continued)
CLOCKS GENERATOR
The entire computer board is run synchronously to the 3.57954Mhz color clock (CI). This is accomplished by generating
anumber of sub-multiple frequencies from our master 28.63636Mhz crystal oscillator. The following are the primary
clocks on the board:
Name Description
CI The 3.579545Mhz Color Clock
C2 CI shifted 45 degrees later
C3 CI shifted 90 degrees later
C4 CI shifted 135 degrees later
7M CI XORed with C3* (7.15909Mhz)
DAC 7M shifted 90 degrees later
7M is the processor clock for the 68000 microprocessor. C1-C4 and DAC are used to clock the custom chips and
for determining the timing of signals to the memory arrays.
The above frequencies are true for NTSC Amigas. APAL Amiga will operate slightly slower, with amain clock of
28.375 16Mhz. This is divided down to get 7M =7.09379Mhz and CI =3.546895Mhz. Aspecial circuit is required
to take five fourths of CI to derive the PAL colorburst frequency of 4.43361875Mhz.
The following clocks are available at the edge connector:
Name Pin Description
C3* 14 C3 inverted
CDAC 15 DAC equivalent
CI* 16 CI inverted
Note that 7M (the processor clock) is not available at the connector; it can be easily generated by:
C3* XNOR CI* =7M equivalent
If you need a14.3181 8Mhz synchronous clock, you can generate it by:
(7Mequiv) XOR (CDAC) =14M equivalent
14M
7M SyncdS2
-^139] is ",
CDAC L
C1_J 1str1
1
C2 L
r"i
CA
CI*
C3*
Amiga System Clocks
2-5

ASOO PLUS SERVICE MANUAL
THEORY OF OPERATION (Continued)
THE 3CUSTOM CHIPS
The 3custom chips provide very fast manipulation of graphics and audio data in the display RAM. All the major
functions in the chips are DMA driven; that is, streams of data are moved between the custom chips and display RAM
under DMA control. These streams of data are acted upon by the custom chips. Fat Agnus, custom chip #1, contains
25 dedicated purpose DMA counters.
The 3chips have control registers which are usually loaded by the 68000. However, Fat Agnus also has the capability
of loading control registers in the other 2custom chips. When Fat Agnus performs abus cycle, it outputs acode
on the Register Address Bus telling the other 2chips the nature of the bus cycle. This is necessary because many of
the bus cycles provide data to or from the other 2chips, thus they must cooperate appropriately.
In addition to manipulating data in the display RAM, the custom chips output streams of data to the video output
circuits and audio output circuits, and they move data to and from the floppy disks and serial port.
Note that the display RAM buses can be completely isolated from the 68000 buses by Fat Agnus and Data Bus drivers.
Thus, Fat Agnus can be performing abus cycle on the display buses simultaneously with the 68000 performing abus
cycle on its buses. This parallelism increases throughout.
BUS CONTROL, ADDRESS/DATA MUX, ADDRESS DRIVER
The bus control logic resides in the control chip (GARY) and Fat Agnus. They provide 3major functions, they:
Synchronize the 68000 to the current phase of CI
Arbitrate between the 68000 and Fat Agnus for the display buses
Generate DRAM timing for the video RAM bus drivers appropriate to the current cycle
Synchronizing the 68000 to CI is straightforward, since the 68000 is clocked by 7M which is twice the frequency and
synchronous to CI .If the 68000 starts abus cycle in the wrong phase of CI ,the bus control chip merely delays /DTACK
long enough so that the 68000 will complete the bus cycle in the desired phase relationship to CI. This phase relation-
ship is necessary because the custom chips and the display RAM are clocked by CI.
Arbitration is very simple. Fat Agnus tells the bus control prior to taking the display RAM buses by asserting an input
to the control chip (GARY) called /DBR. Whenever Fat Agnus has the display buses and the 68000 wants them, the
68000 is held off by not giving it /DTACK. In this state the 68000 has no effect on the display buses until the bus
controller enables the bus drivers.
Fat Agnus generates the DRAM timings and does all address multiplexing. If the 68000 is running avideo memory
cycle, its addresses are routed through Fat Agnus onto the multiplexed address lines. If the custom chips are running
amemory cycle the addresses are routed to the multiplexed address lines from internal address register.
DISPLAY RAM
The display RAM is a512K read/write memory that resides on the RAM address and RAM data buses. It is expandable
to 1M bytes by the addition of the RAM expansion module. It is implemented using standard 256K x1dynamic RAMs,
refreshed by Fat Agnus.
The display RAM is really used for much more than just holding graphics data. It also stores code and data for the 68000.
CUSTOM CONTROL CHIPS
The Amiga's animation, graphics and sound are produced by three custom chips. Fat Agnus (8375), High Res Denise
(8373) and Paula (8364). Afourth custom chip, Gary serves as the control chip. The following pages include feature
lists, and block diagrams for these chips.
2-6

mmm
A500 PLUS SERVICE MANUAL
8375 AGNUS 2MEG
GENERAL
This device is an address generator type IC. Its main function is as aRAM address generator and register address
encoder that shall produce all DMA addresses for 25 channels.
The block diagram for this device shows the DMA control and address bus logic. The output of each controller in-
dicates the number of DMA channels driving the Register Address Encoder and RAM Address Generator.
The RAM Address Generator contains an 20 bit pointer register for each of the 25 DMA channels and also it contains
pointer restart (backup) registers and jump registers for six (6) of the channels. Afull 20 bit adder carries out the
pointer increments and adds for jumps.
The priority control logic looks at the pipe-lined DMA request from each controller and stages the DMA cycles based
upon their programmed priority and sync counter time slot. Then it signals the processor to get off the bus by asserting
the DBR line. The following is abrief description of the device's major operational modes.
Acontrol register determines which 256 possible logic operations is to be performed as the source images are combined
and how far they are to be moved (Barrel shifted). In addition to the image combining and movement powers, the
Blitter can be programmed to do line drawing or area fill between lines.
RGA1-RGA8
n.a« A1 A8
AS
AGEH >
Butter
MUX
<2
<:!< (2D) SCD Register Address Decoder
28MHz >
CCK<-
CCKQ<"
7MHz<-
CDAC<"
7\
(w
RAM Address Generator
35 f>*> ft ft ft
CData Bus
Register Address Encoder
il
5IS
s!
I
IU2 I I I
1—** nI/s/4.
I
Sprite DMA
Control Logic
Sprite Vertical
Position Compare
KTSC 7PAL /\ S\
TV SYNC
LIGHT PEN
QATAtRDO R015)
Sync. Counters
and Light Pen
Registers
IOOtS
Sprite Vertical
Position and
Control
Registers
IEI
wwi
o—
'
u
m
Audio
DMA
Control
Logic
Audio
Control
Registers
JH
Bit
Plane
DMA
Control
Logic
Bit
Plane
Control
Registers
DATA BUS (16)
m
I
Disk and
Refresh
DMA
Control
Logic
Disk and
Refresh
Control
Registers
jh
I
BLITTER
DMA
Control
Logic ^>
BLITTER
Control
Registers
JU
Bit Map
Image
Manipulator
BLITTER
<T
Register Address Decoder
Agnus 8375 Block Diagram
BLITTER
The procedure for moving and combining bit mapped images in memory received the name Bit Blit from acomputer
instruction that did block transfers of data on bit boundaries. These routines became known as Bit Blitters or Blitters.
The Blitter DMA Controller is preloaded with the address and size of three (3) source images (A,B, and C) and one
(1) destination (D) in the dynamic RAM. These images can be as small as asingle character or as large as twice the
screen size. They can be full images or smaller windows of alarger image. The actual pixel resolution is controlled
by the BLTSIZE (BLTSIZH and BLTSIZV) registers which contain up to 15 bits for the image height (15 bits =
32K dots max.) and up to 11 bits for the image width (11 bits =2k words =32K pixels max.). After one word of
each source image is sequentially loaded into the source buffer (A, B, C) they are shifted and then combined together
in the logic unit to perform image movement overlay, masking, and replacements. The result is captured in the destination
buffer (D) and sent back to the RAM memory destination address. This operation is repeated until the complete image
has been processed. The unit has extensive pipelining to allow for shifter and logic unit propagation time, while the
next set of source words is being fetched.
2-7

ASOO PLUS SERVICE MANUAL
8375 AGNUS (Continued)
BITPLANE ADDRESSING
Some computer bitmap displays are organized so that the bitplanes for each pixel are all located within the same ad-
dress. This is called pixel addressing. If the entire data word of one address is used for asingle pixel with 8bit planes,
the data word will look like this, (numbers are bitplanes): 12345678
The data compression can be improved by packing more than one pixel into asingle address like this: 1234567812345678
or like this, if there are only 4bitplanes: 1234123412341234
The IC device, uses abitmap technique called Bitplane Addressing. This separates the bitplanes in memory. To create
a4plane (16 color) image, the bitplane display DMA channels fetch from 4separate areas of memory like this:
1111111111111111
2222222222222222
3333333333333333
These are held in buffer register and are used together as pixels, one bit at atime, by the display (left to right).
This technique allows reduced odd numbers of bitplanes (such as 3or 5) while maintaining packing efficiency and
speed. It also allows grouping bitplanes into 2 separate images, each with independent hardware high speed image
manipulation, line draw, and area fill.
DMA CHANNEL FUNCTIONS
Each channel has an 20 bit RAM address pointer that is placed on the MA memory address bus, and is used to select
the location of the DMA data transfer from anywhere in 1M words (2M bytes) of RAM.
An eight (8) bit destination address is simultaneously placed on the register address bus (RGA), sending the data to
the corresponding register.
In atypical DMA channel, almost all channels have DRAM as source and chip registers as destination.
The pointer must be preloaded and is automatically incremented each time adata transfer occurs.
Each controller utilizes one or more of these DMA channels for its own purposes. The following is abrief summary
of these controllers and the DMA channels they use.
A-Blitter (four (4) channels)
The Blitter uses four (4) DMA channels, Three source and one (1) destination as previously described.
Once the Blitter has been started, the four (4) DMA channels are synchronized and pipelined to automatically handle
the data transfers without further processor intervention. The images manipulated in memory, independent of the
display (bitplane DMA).
B-Bitplane (six (6) channels)
The bitplane controller continuously (during display) transfers display data from memory to display buffer registers.
There are six (6) DMA channels to handle the data from six (6) independent bit planes. The buffers convert this bitplane
data into pixel data for the display.
C-Copper (one (1) channel)
The Copper is aco-processor that uses one of the DMA channels to fetch its instructions. The DMA pointer is the
instruction counter and must be preloaded with the starting address of the Copper's instructions.
The Copper can move (write) data into chip registers. It can skip, jump, and wait (halt). These simple instructions
give great power and flexibility because of the following features.
When Copper is halted, it is off the data bus, using no bus cycles until the wait is over. The programmed wait value is
compared to a counter that keeps track of the TV beam position (beam counter) and when they are equal, the Copper
will resume fetching instructions.
It can cause interrupts, reload the color registers, start the Blitter or service the audio. It can modify almost any register
inside or outside the IC device, based on the TV screen coordinates given by the Beam Counter and the actual address
encoded on the RGA Bus.
2-8

A500 PLUS SERVICE MANUAL
8375 AGNUS (Continued)
DMA CHANNEL FUNCTIONS (Continued)
D-Audio (four (4) channels)
There are four (4) audio channels, all of which are located outside of the audio DMA Controller section of Agnus.
Each controller is independent and uses one DMA channel from the DMA Controller and fetches its data during a
dedicated timing slot within horizontal blanking. This is accomplished by acontroller asserting the DMAL input on
the DMA Controller.
E-Sprites (eight (8) channels)
There are eight (8) independent Sprite controllers, each with its own DMA channel and its own dedicated time slot
for DMA data transfer. Sprites are line buffered objects that can move very fast because their positions are controlled
hardware registers and comparators.
Each sprite has two (2) sixteen bit data registers that define a16 pixel wide Sprite with 4colors. Each has ahorizontal
position register, avertical start position register and avertical stop position register. This allows variable vertical
size sprites.
The Sprite DMA controller fetches image and position data automatically from anywhere in 2Megabytes of memory
depending on device pin configuration.
Sprites can be run automatically in DMA mode or they can be loaded and controlled by the microprocessor.
Each Sprite can be re-used vertically as often as desired. Horizontal re-using is also allowed with microprocessor control.
F-Disk (one (I) channel)
The disk controller, which is located outside of the DMA, uses asingle DMA channel from the device. The controller
uses the DMA time slot for data transfer and can read or write ablock of data up to 128K anywhere in 2Megabytes
of memory depending on device pin configuration.
G-Memory Refresh (one (I) channel)
The refresh controller uses asingle DMA channel with its own time slots. It places RAS addresses on the memory
address bus (MA) during these slots, in order to refresh the dynamic RAM. Memory is refreshed on every raster line.
During the DMA no data transfer actually takes place. The register address bus (RGA) is used to supply video syn-
chronizing codes. At this time RAS1* and RAS are low. CASU* and CASL* are inactive during this cycle.
RAM AND REGISTER ADDRESSING
The device generates RAM addresses from two sources, the processor or the device performing DMA cycles. The pro-
cessor accesses RAM whenever AS* and RAMEN* are both low. At this time, the device also multiplexes the pro-
cessor address (A1-A20) onto the MA bus. During row address time A9-A17 and A19 are placed onto MA0-MA8,
MA9, respectively; during column address time A1-A8, A18 and A20 are placed onto MA0-MA7, MA8 and MA9,
respectively. In the 1meg configuration, A19 is still used to determine the RAS line to be asserted. If A19 is low
RASO* is active and if high RAS1* is active. In the 2meg option RAS will always be active on aRAM access. The
IC will assert CASL* if LDS* is low or CASU* if UDS* is low.
When the device needs to do aDMA cycle, the device disables the processor from accessing RAM by asserting the
Data Bus Request Line (DBR*). At this time, the device multiplexes its generated RAM address onto the MA lines
and will activate RAS and the proper RASO* or RAS1* line unless it is arefresh cycle where all RAS lines are active.
During aDMA cycle, the IC device will also assert both CASU* and CASL*, unless it is arefresh cycle where they
both remain inactive.
The device also generates RGA addresses from either the processor or device DMAs, each of which is selected by
an internal multiplexer. This multiplexer allows the processor to perform aregister read/write access when AS* and
RGEN* are both low. The device then takes the low order byte of the processor address Al to A8 and reflects its
value on the RGA output bus RGA1 to RGA8. The device will reflect the status of PRW input on the RRW output
line, to indicate amemory read or write operation.
During adevice DMA cycle, the device prevents the processor from doing aregister access by asserting the DBR*
line. The device will then place the contents of its register address encoder onto the RGA bus.
2-9

ITEM NO. PART NO. DESCRIPTION
1312506-01 BOTTOM CASE
2332358-01 TOP SHIELD
3312504-02 TOP SHIELD
4332359-01 TOP SHIELD, 68000 LID
5312589-01 INSULATION SHEET
7312590-01 BOTTOM SHIELD
9312594-01 DISK DRIVE ASSEMBLY, CHINON
12 312812-01 PCB ASSEMBLY, A500 PLUS, REV. 8, PAL
13 312812-02 PCB ASSEMBLY, A500 PLUS, REV. 8, NTSC
15 327038-01 RF SHIELD EXPANSION
17 312502-01 KEYBOARD ASSEMBLY, US/CN
18 312502-02 KEYBOARD ASSEMBLY, GR/AU
19 312502-03 KEYBOARD ASSEMBLY, FR/BE
20 312502-05 KEYBOARD ASSEMBLY, SD/FN
21 312502-06 KEYBOARD ASSEMBLY, SP
22 312502-07 KEYBOARD ASSEMBLY, DN
23 312502-08 KEYBOARD ASSEMBLY, SEV
24 312502-09 KEYBOARD ASSEMBLY, NR
25 312502-04 KEYBOARD ASSEMBLY, IT
26 312502-12 KEYBOARD ASSEMBLY, UK/AL
27 312504-99 KEYBOARD ASSEMBLY, BLANK
32 390251-01 JACKPOST STANDOFF
36 390146-01 SCREW, TORQUE, #5 x5/16 LG. STEEL
40 906800-03 SCREW, METRIC, M3 x8.0 SELF TAPPING
41 252177-01 SPADE TERMINAL, MALE
42 905650-11 LOCK WASHER, EXTERNAL TOOTH
44 390146-02 SCREW, TORQUE, #5 x3/8 LG. STEEL
CONNECT TO CN13
CONNECT TO CN11
CONNECT TO CN12

A500 PLUS SERVICE MANUAL
QQQQQQQQQ
02 ONLY
MAIN ASSEMBLY DIAGRAM
FOR MOUNTING ITEM #9 (3 REQ'D.)
3-1