Commodore A500 PLUS User manual

Produced By:
Commodore International Spare Parts GmbH
Braunschweig, West Germany
SERVICE MANUAL
•=»**•
A500 PLUS
INCLUDES A501 PLUS
RAM EXPANDER
OCTOBER, 1991 PN-400420-01
INTERNATIONAL EDITION
SERVICE POLICY AND PART NUMBER INFORMATION MAY VARY ACCORDING TO
COUNTRY. SOME PARTS MAY NOT BE AVAILABLE IN ALL COUNTRIES.
ri Commodore Business Machines, Inc.
1200 Wilson Drive, West Chester, Pennsylvania 19380 U.S.A.
Commodore makes no express or implied warranties with
regard to the information contained herein. The infor-
mation is made available solely on an as is basis, and the
entire risk as to completeness, reliability, and accuracy
is with the user. Commodore shall not be liable for any
damages in connection with the use of the information
contained herein. The listing of any available replacement
part herein does not constitute in any case arecommenda-
tion, warranty or guaranty as to quality or suitability of
such replacement part. Reproduction or use without ex-
press permission, of editorial or pictorial content, in any
matter is prohibited.
This manual contains copyrighted and proprietary information. No part
of this publication may be reproduced, stored in aretrieval system, or
transmitted in any form or by any means, electronic, mechanical, photo-
copying, recording or otherwise, without the prior written permission
of Commodore Electronics Limited.
Copyright ©1991 by Commodore Electronics Limited.
All rights reserved. Printed in U.S.A.
Reprinted with permission of North American Philips

A500 PLUS SERVICE MANUAL
TABLE OF CONTENTS
SECTION 1—SPECIFICATIONS
A500 PLUS SPECIFICATIONS M
A501 PLUS SPECIFICATIONS 12
SECTION 2—THEORY OF OPERATIONS
AMIGA 500 PLUS MEMORY MAP. 2-1
A500 PLUS BLOCK DIAGRAM 2"2
THEORY OF OPERATION 2"3
8375 AGNUS 2MEG 2"7
8373 DENISE HI RES 2"n
8364 PAULA 2"12
GARY •-2"13
SECTION 3—TROUBLESHOOTING
MAIN ASSEMBLY DIAGRAM 3-1
SECTION 4—PARTS
A500 PLUS PCB ASSEMBLY 312812 4-1
A500 PLUS SHIPPING ASSEMBLIES 4-2
A500 PLUS MAJOR ASSEMBLIES 4"3
A500 PLUS PCB COMPONENTS :4"4
A501 PLUS SHIPPING ASSEMBLIES 4-5
A501 PLUS MAJOR ASSEMBLIES 4-6
A501 PLUS PCB COMPONENTS 4-7
SECTION 5—SCHEMATICS
A500 PLUS SCHEMATIC #312813, REV. 15-1
A501 PLUS SCHEMATIC #363835, REV. 5-11

ASOO PLUS SERVICE MANUAL
A500 PLUS SPECIFICATIONS
INTRODUCTION
The A500 Plus is afeature enhanced version of the A500 personal computer.
FEATURES
CPU: 7.16 MHz 68000 NTSC; 7.09 MHz 68000 PAL
Memory: 1Megabyte standard expandable to 2MB with addition of A501 Plus
Kickstart ROM: 512K (V2.04)
Mass Storage Memory: Internal, 3.5 inch FDD mounted on the right side, the same as the A500.
Additional Features: Real Time Clock (on-board) with battery backup.
APPEARANCE
The A500 Plus appearance shall be the same as the A500. Anew logo plate has been added to distinguish "A500"
from "A500 Plus". The color is the same light beige as the current A500.
WHAT'S ADDED
1Meg on-board memory expandable to 2Meg.
8375 FAT AGNUS which supports 2Meg. of Chip RAM
On-board Real Time Clock
8373 ECS Denise
Full ECS support
V2.04inROM
CUSTOM CHIPS
The A500 Plus shall contain the same custom chip set as the A500, except for the 8375 2Meg. FAT AGNUS and 8373
ECS Denise.
SYSTEM I/O
EXTERNAL SYSTEM I/O
External floppy, Serial, Parallel, Mouse, Joystick, Stereo Audio Ports
These Ports remain unchanged from their A500 counterparts.
MEMORY MAP
The A500 Plus Memory Map is the same as the A500 Memory Map.
1-1

A500 PLUS SERVICE MANUAL
A501 PLUS SPECIFICATIONS
DESCRIPTION
The A501 Plus is amemory expansion board for the Amiga 500 Plus personal computer. It has 1MB of "chip" memory
and interfaces directly to the A500 Plus memory expansion slot. Unlike the A501, the A501 Plus doesn't have aReal
Time Clock (RTC), the A500 Plus has abuilt-in RTC.
The A501 can be used in either the A500 or A500 Plus personal computer, has 512K of memory and includes aReal
Time Clock. The A500 maps the A501 into pseudo-fast memory while the A500 Plus maps it into chip memory. In
addition, when used in an A500 Plus system, the internal (built-in) RTC is selected.
Both the A501 and A501 Plus uses the same printed circuit board (PCB). In the A501 Plus, the RTC and refresh
feature components are not loaded.
MEMORY TYPE
The A501 Plus shall use 256K x 4 120ns DRAMs.
PIN DESCRIPTIONS
PIN
PIN NAME
+5
GND
XDRD (0-15)
XDRA (0-8)
/EXTICK
/XCLKS
/XOE
/XCASL
/XCASU
/XRAS1
/XRAS0
/XWE
NC
XD (0-3)
XA (2-5)
/XCLKRD
/XCLKWR
+12V
NUMBER
1-2, 51-52
3-4, 21-22,
53-54
5-20
23-31
32
33
34
35
36
37,
38
39
40, 56
41-44
45-48
49
50
55
SIGNAL
DIRECTION
I
I/O
I
O
I/O
I
I
I
I
DESCRIPTION
+5Volts
Signal Ground
Memory Data Bus
Memory Address Bus
Active low. When this signal is asserted, it allows the A500 to
detect the presence of an A501. The A501 Plus does not use
this signal.
Active low. When this signal is asserted, the external RTC is
selected. This signal is not used in the A501 Plus.
Active low. When this signal is asserted, data can be read from
the expansion memory.
Active low. This signal strobes the column address into DRAMs
and corresponds to the low byte of the data word.
Active low. This signal strobes the column address into the
DRAMs and corresponds to the high byte of the data word.
Active low. This signal strobes the row address into the DRAMs
and corresponds to the upper 512K of the expansion RAM.
Active low. This signal strobes the row address into the DRAMs
and corresponds to the lower 512K of the expansion RAM.
Active low. When this signal is asserted, data is written into
the expansion memory.
Not connected.
RTC Data bus. These lines are not used in the A501 Plus.
RTC Address Bus. These lines are not used in the A501 Plus.
Active low. When this signal is asserted, data can be read from
the RTC. This signal is not used in the A501 Plus.
Active low. This signal strobes the data and address into the
RTC. This signal is not used in the A501 Plus.
+12 Volts. This is used on the A501 to charge the battery. This
line is not used on the A501 Plus.
1-2

A500 PLUS SERVICE MANUAL
A501 PLUS SPECIFICATIONS (Continued)
FACTORY DEFAULT JUMPER SETTINGS
JP1 JP2A JP2B JP3 JP9
A501 1-2 shorted 1-2 open 1-2 open 1-2 shorted 1-2 open
2-3 shorted 2-3 shorted 1-2 shorted
1-1 open
2-2 open
AS01 Plus 1-2 shorted 1-2 shorted 1-2 shorted 1-2 shorted 1-2 open
2-3 open 2-3 open 1-2 shorted
1-1 open
2-2 open
Jumper
JP1
JP2A, JP2B
JP3
JP9
DIMENSIONS
Length:
Width:
Function
When 1-2 are shorted, /EXTICK detection is enabled. This jumper has no effect on the A501 Plus,
because it does not use /EXTICK detection.
When 2-3 are shorted (1-2 open), it enables the refresh feature in the A501. Refresh components
Ul 1-U13 must be loaded in the A501 .The refresh feature is only required on the A501 to compen-
sate for refresh deficiencies in older revs of the A500.
Swaps upper and lower bank DRAMs. When 1-2 are shorted (1-1 and 2-2 open), /XRASO and
/XRAS1 selects the lower and upper banks respectively. Conversely, when 1-1 and 2-2 are shorted,
/XRASO selects the upper bank while /XRAS1 selects the lower bank RAMs.
Overwrites /XCLKS. When 1-2 are shorted, /XCLKS is permanently enabled and the A501 (exter-
nal) RTC is always selected. This jumper is normally open. Selection of internal or external RTC
is done by the A500 or A500 Plus via the /XCLKS line. RTC components U9, U11-U13, C9,
C11-C13, C911, C913, R911-R915, D11-D9123, BT9, TC9 and Y9 must be loaded in the A501.
5.5 in.
3.5 in.
POWER
+5VDC
+12VDC
@330 mA MAX for A501 Plus
@280 mA MAX for A501
@15 mA MAX for A501
Not Used on A501 Plus
ENVIRONMENT
Operating Temperature to +55°C
Humidity Up to 90% without condensation
1-3

^^mmmmmimi
AMIGA 500 PLUS MEMORY MAP
OVERLAY
A500 PLUS SERVICE MANUAL
RESET VECTORS
512K
EXPANSION
RAM
REAL
TIME CLOCK
(OPTIONAL)
DISPLAY
RAM
001
01
100
'NAAA/VNAAAA/
expansion
Kaaaaaa/vwa/1
EXPANSION
EXPANSION
lAAA/WA/VAA/Nl
8520
BFE000
BFD000
C0000
C7FFFF
00
04
08
DC0000
DEFFFF s////////,
CROSS =RESERVED
z
DFF0000
CHIPS
CONFIG
CART
ROM
20
40
80
A0
CO
DO
E0
E8
F0
F8
FC
512K
8MEG
2MEG
2MEG
1/2 MEG
1/2 MEG
1/2 MEG
512 K
2MEG
1/2 MEG
2-1

8375 AGNUS (Continued)
A500 PLUS SERVICE MANUAL
28MHZ
CCKO
7MHZ
CDAC*
Clock Relations
CLOCK RELATIONS (Refer to Figure above)
SYMBOL MIN MA
2.4.1 28MHz clock cycle t28MC 34.57 35.27
2.4.2 28MHz clock high t28MHi 12.0 22.9
2.4.3 28MHz clock low t28MLo 12.0 22.9
2.4.4 CCK clock cycle tcyc 260 290
2.4.5 CCK clock high tch 130 150
2.4.6 CCK clock low tcl 130 150
2.4.7 CCK-CCKQ clock separation tcq 65 75
2.4.8 7MHz clock cycle t7MC 130 150
2.4.9 7MHz clock high t7MHi 65 75
2.4.10 7MHz clock low t7MLo 65 75
2.4.11 7MHz-CDACQ clock separation t7MQ 30 40
2.4.12 CCK to 7MHz delay tc7M 15
2.4.13 CCKQ to 7MHz delay tq7M 15
2.4.14 Clock rise time tr 10
2.4.15 Clock fall time tf 10
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2-10

Vmmm
A500 PLUS SERVICE MANUAL
8373 DENISE HI RES
MAIN FUNCTIONS
•Display data buffer, encode display object to RGB colors.
•Bitplane &Sprite display. Parallel data from data bus is retained in six (6) Bitplaae and eight pairs of Sprite
data buffers.
•Bitplane Data loaded and serialized during display activity.
•Sprite Data loaded during display inactivity —individual serialization occurs when Sprite position Compare logic
detects equality between the Sync Counter and any Sprite Position Register.
•Six (6) lines of Bitplane &eight (8) pairs of serial data go to Priority control logic which selects only one (1) of the
Sprites or one (1) of the separate Bitmap images to produce the five (5) bit color select code at its output. This five
(5) bit code then selects one of the thirty-two (32) color registers to produce the twelve (12) bit RGB video output.
•The Bitplane and Sprite serial lines also go to the Collision Detect Logic, which detects real time coincidence between
them, and sets appropriate bits in the Collision Storage register. This register is read and cleared by the 68000.
•The four (4) "mouse counters" are controlled by the two (2) mouse-joystick connectors. These count the pulses
representing the horizontal and vertical motion of two (2) "mouse' 'controllers, and are read by the 68000.
CHIP ELEMENTS
32 Color Registers; Bitplane Priority and Control Registers; Color Select Decoder; Priority Control Logic; 16 Sprite Serial
Lines; Sprite Data Registers; Bit Plane Control Registers; Two (2) Mouse Connectors; Sprite Position Compare Logic;
Sprite Horizontal Control Registers; Bit Plane Serializer Collision Detect Logic; Collision Control Register; Collision
Storage Register; Buffer —Data Bus; Buffer —Register Address Decode; Bit Plane Data Registers Video: RGB; Sprite
Serialization.
IA
sz
ICOLLISION
DETECT
LOGIC
a
Q
(8x2
COLLISION
CONTROL
REGISTER
"TV
COLLISION
STORAGE
REGISTER
—
M
DB
HD1CO
RGA [n
D
v
BIT PLANE
SERIAL
BIT PLANE
0ATA REGISTER
(6)
A~~
A
8x2)
PRIORITY
CONTROL
LOGIC DCOLOR
SELECT
DECODE
32
COLOR
REGISTERS
SPRITE
SERIALIZE
SPRITE DATA
REGISTERS
(16) _
SPRITE
POSITION
COMPARE
LOGIC
A-
BIT PLANE
CONTROL
REGISTER
7\ CA
A
BIT PLANE
PRIORITY
&CONTROL
REGISTERS
7V*
H0RIZ
SYNC
COUNTER
£SPRITE
H0RIZ
POSITION
REGISTERS
ra
DATA BUS (16)
REGISTER ADDRESS DECODE
>-
CO o
cc
I—
CO
h-1
(12)
(4)
CO
O:
Denise Block Diagram
2-11

A500 PLUS SERVICE MANUAL
8364 PAULA
Paula is the Port, Audio and Uart chip. Its main function is the four audio channels. It also contains the I/O ports,
(Disk and Pots), Serial Port (Uart), and the Interrupt Control and Status Register.
DTOA CONVERTERS
The four audio channels each have aDMA pointer register, data register, period, (frequency), register and volume
register. Each channel has an on chip Dto A(digital to analog) converter on the output. The four channels are grouped
into aright and left audio output.
DISK CONTROL
The disk controller has registers for data read, data write and control. It also contains aPrecompensation Output
circuit, aData separator input circuit with adigital phase lock loop.
UART CONTROL
The serial port uart included in Paula contains Data registers, Control registers, Transmit, (TRN), and receive registers.
POT CONTROL
The four pot ports are general purpose I/O ports. They have counters for simple Ato D(digital to analog) conversion
of an external capacitor charging, which could also be used for analog joystick controllers.
INTERRUPT CONTROL
The audio, disk and uart controllers all set their own Interrupt Status register bits.
DMA REQUEST LOGIC
The audio and disk controllers also go to the DMA request logic, (remember: they are DMA users), causing the DMAL
signal to request DMA cycles from Agnus.
Left Right
Audio Audio
Output Output
Disk
Out In
UART
In Out
POT
Ports
DMAL
to Agnus DMA
Request
Logic
Interrupt
ID Code
to 68000
EXT.
Interrupt
Inputs
DB
f
<r
Int.
Control
Logic
Int.
Status
Registers
F03
CD
t
Dto A
Conv.
0& 1
Audio
Control
Counters
Data
Registers
~7V
Dto A
Conv.
2&3
Audio
Control
Counters
Data
Registers
Data
Sep
V
Pre
Comp
Disk
Control
Logic
Data
Registers
REC
AAAA
TRN
UART
Control
Logic
Data
Registers
±c ±c—ii—ii
Buffers
Latches
(Bi-Dir)
POT
Control
Counters
Data
Registers
Data Bus 16
RGA
o
0)
09
.Q
o
Register Address Decode 8
Paula Block Diagram
2-12

ASOO PLUS SERVICE MANUAL
GARY CUSTOM CONTROL CHIP
FEATURES
•Provides all bus control signals.
•Provides all address decoding.
•Generates the 68000 VPA signal.
•Handles some of the floppy circuitry.
•Provides keyboard reset interface.
GNDi -
vpa-
DEL"
DEB"
For signal descriptions,
k#312813, sheet 1of 10
KBRESET -
Vccl -
MTR"
DKWE -
DKWD-
LDS-
UDS
R/W-l
AS
BGACK -14
BLIT -15
1
2
3
4
5
6
7
8
9
10
11
12
13
SEL"
Vcc2"
16
17
18
19
20
21
22
CLKWR H23
GND2 -24
REGEN-
BLISS -
RAMEN -
ROMEN ~
CLKRD -
U5
GARY
48 -Vcc3
47 -MTRX
46 -MTRON
45 -DKWDB
44 -DKWEB
43 -DTACK
42 -HLT
41 -RST
40 -GND3
39 ^A23
38 -A22
37 -A21
36 -A20
35 -A19
34 -A18
33 -A17
32 -EXRAM
31 -XRDY
30 -OVL
29 -OVR
28 -CCK
27 -CCKQ
26 -CDAC
25 -LATCH
GARY BLOCK DIAGRAM
68000
Addresses 2_
(8)
Address Strobe (AS) —
UDS, LDS
Clocks
(C2, C3)
Override (OVR)
Overlay (OVL)
Processor read write
(PRW)
Expansion Board
Present (EXPEN)
DBR
XRDY
Override
(OVR)
>
Address
Decode
-*- RAM Enable (RAME)
-^ RGA Enable (RGAE)
Bus
Control
ROM Enable (ROME)
^Real time clock read
and write (RTCR, RTCW)
*- VPA
^CDR
*- CDW
+LATCH
Bidirectional
tri-state latch
control
*DTACK
-^ BLS
KReset
Keyboard Reset
Floppy Control
Logic
Reset
Control
+- Reset
+Halt
2-13