Commodore MPS 1250 User manual

£-9T -OoH
iT
Commodore
MPS 1250
Supplement to 1200/P
Service Manual
10/88
Commodore

Parallel and Serial BIP
(SPECIFICATIONS FOR EUROPE)

PARALLEL AND SERIAL BIP
TABLE OF CONTENTS
1
.
Control Circuit Block Diagram o-]
2. Parallel Interface Specifications D-3
(1
)
Specifications ;D-3
(2) Pin, No. and signal name D-3
(3) Description about interface signals of CN12 D-4
3. Serial Interface Specifications D-6
(1
)
Specification D-6
(2) Pin No. and Signal name D-6
(3) Description about interface signals of CN13 '. .,.D-6
(4) Data transfer sequence ,D-8
4. Specification Setting DIP Switches D-10
5. Parts Lists
6. Circuit Diagrams
(1) Mounting Diagram
(2) Circuit Diagram
f^

STANDARD Parallel And Serial BIP {Basic Interface Pack)
1. Control Circuit Block Diagram
Host
Computer
(Cenironici like)
V
l/F Select
Circuit
)G
7T
Commodors
Clocked Serial
Connector
)/0 Connector
I
J.
ISerial Bus
IControl
jCircuit
I/O Connector
8MHz
^^
ALE
CPU
^mI
Address
Laich
II
v.
ROM 128k' U
RAM 8k
J
Driver Interface Bus
7^ Shift oTp
Register Switcfies
<o-
c-crb-
Power/Driver
P.C.B.
Block Diagram
Fig. 1
Ablock diagram tor the parallel and serial BIP is shown in Fig. 1. For interface, either Centronics
parallel or Commodore serial can be selected by the DIP switches on the Interface Board. Parallel
data of 8bits (*DATA1 to *DATA8) is input via the I/O connector. Strobe signal (*DSTB) is also
input together with the data.
.At input of the strobe signal, BUSY signal becomes HIGH and *DATA1 to*DATA8will be stored
inside. When CPU finishes processing the data, BUSY signal becomes LOW again and inputting of
data is enabled.
Serial data from the host-computer is input through TTL level and converted to parallel data in the
serial bus control circuit.
The CPU takes in the data when transferring of 1byte is completed.
Printing is started if the data input reaches one line or print start command code such as LF code,
CR code, etc. is received.
This unit is controlled by an 8-bit one-chip microcomputer. The clock of CPU is 8MHZ and in-
structions will be executed with aminimum unit of 1nS. The CPU has 36 I/O ports and they are
assigned to interface lines for host CPU and interface bus with Power/DriverPCB.
-D-1 -
^

In addition, the CPU has six independent timers and each of them is used to control printing timing,
stepping motor driving timing, print head current flowing time. etc.
As the memory, ROM of 128 kilobytes and RAM of 8kilobytes are provided as standard and the
lower 8bits of address bus are the ones which are generated by latching the multiplexed data bus
with ALE signal.
oConnection to Power/Driver. PCB will be done by the driver interface bus and this bus consists of
the following control lines.
•Clocked serial data bus
•Stepping motor voltage control line
•Operation panel control line
•Sensors input signal line"
•Master reset signal line
Phase data of stepping motor and printing data of print head are transmitted to Power/Driver
PCB at high speed via the above-mentioned clocked serial data bus. Moreover, the data of DIP
switches becomes serial data by means of a shift register and it is taken to CPU by the clocked
serial data bus.
-D2-
n

2. Parallel Interface Specifications
(1) Specifications
Data Transmitting Type
Synchronizing Method
Handshake
Logic Level
8bit Parallel
By externally supplied strobe
By "ACKor BUSY
TTL compatible
(2) Pin No. and signal name
•Parallel Specifications (CN1 2)
PIN No. RETURN
PIN No. Signal name PIN No. RETURN PIN No. Signal name
119 •DSTB 16 -V
2
3
4
5
6
7
8
9
20
21
22
23
24
25
26
27
•DATA!
•DATA2
•0ATA3
•DATA4
•DATA5
•DATA6
•DATA?
'DATA8
17 FRAME GND
18 +5 V
19-30 TWIST PAIR
GND
31 -•PRIME
10 28 •ACK 32 -•FAULT
n29 BUSY 33 -GND
12 30 PE 34 -NC
13 -SLECT 35 -•FUSE
(Note 1)
14 -•AFXT 36 -•SLCT IN
15 -NC
(Note 1)•FUSE is connected to +5 Vvia a3.3 KQ resistor.
-D-3 -
n

(3) Description about interface signals of CN12
•'DSTB: Synchronized pulse of parallel data. The pulse width of this signal must be more
than 0.5mS at the receiving end.
•*DATA1 to 'DATAS: The parallel 8-bit data sent from the host CPU. High level for a
logical 1and LOW level for alogical 0.
•*ACK: Data demanding signal sent from the printer to the host CPU. The pulse width is ap-
proximately 5tiS. This is astrobe sent out when the printer goes to READY state.
•BUSY: HIGH level Indicates a"printer busy" status to the host CPU. Data sent during
BUSY state may not be guaranteed. When this signal goes to LOW level, the printer
is in READY condition.
BUSY conditions are as follows:
a. During data receive time
b. OFF LINE
c. In an alarm condition
•PE; Goes to HIGH level when paper runs out. In paper out status, the printer is auto-
-matically set to OFF LINE. It cannot be reset to ON LINE status until new paper is
inserted.
•SLECT: Connected to +5V via a3.3 Kn resistor.
•'AFXT ('AUTO FEED XT): When this signal is set to LOW level, one line is automatical-
ly fed after printed by OR code.
•"PRIME (*INIT): Printer initializing signal. When this signals is set to LOW level, that indi-
cates the printer is in the same condition as power on. The contents of the print
buffer are cleared. The pulse width of this signal must be more than 50 fiS at the
receiving end.
•'FAULT (ERROR): When this signal is in LOW level, the printer is in one of the following
three conditions;
a. Paper Out
b. OFF LINE
c. Printer Error
Printer error conditions are as follows:
•Home position sensor cannot be detected by moving the print head at power on.
•During printing, collation of the current address and the home position sensor
did not match.
•"SLOT IN: When this signal is in LOW level, the printer is selected.
•SLCTIN oLS04
JP1
777-
Fig. 2
Since the signal 'SLOT IN has the circuitry shown in Fig. 2, caution should be paid
to the connection on the HOST side. Driving with TTC IC may cause damage.
-D-4-
r^

+5 V: Power supply of +5 V. This line must not be used at the HOST side. If used, the
printer may be damaged.
The timing chart for data-input is shown in Fig. 3..
SUSY
'ACK
Fig. 3. Timing Chart
-D-5-

3. Serial interface Specifications
(1) Specifications
Interface
Word Length
Sianal Level
Commodore Serial Bus (Clocked serial
8-bit fixed
TTL
(2) Pin No. and signal name
•Serial Specifications (CN13)
Fig. 2
Table 1
Pin No. Signal In/Out
1SERIAL "SRQ -
2GND -
3SERIAL ATN In
4SERIAL CLK In
5SERIAL DATA In/Out
6•RESET In
Note!: Pin No. 1SERIAL 'SRQ is not con-
nected to this unit.
Note 2: The signal marked with an asterisk *is
designated as Aciive-Low.
Note 3: The column "In/Out" refers to the
direction of signal flow as viewed from
the printer.
(3) Description about interface signals of CN13
SERIAL *RSQ (SERIAL Service Request): Interrupt request to the host computer. Not
used for this unit.
SERIAL ATN (SERIAL Attention): When this signal is in LOW level, the transferred data
is designated as device function (device address or secondary address command) and
when it is in HIGH level, the data is designated as anormal one.
SERIAL CLK: Aclock signal for data transfer. All the data are transferred with synchro-
nization of this clock.
Moreover, -prior to transferring data, this signal line becomes HIGH level to indicate
that the unit is ready for transmission.
-D-6-

SERIAL DATA: The data is transmitted onto this signal line with syhchronization of
SERIAL CLK. The data is established at the rise edge of SERIAL CLK. Moreover,
after data transfer, the receiving side sets this signal line to LOW level to indicate that
the data is received. This goes to HIGH level when- the data is taken in.
*RESET: When this signal becomes LOW level, master reset is performed on the printer.
-D-7 -