Compaq iPAQ Internet Device Use and care manual

Technical
Reference
Guide
For the
Compaq iPAQ Internet Device

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Technical Reference Guide
Compaq iPAQ Family of Internet Devices
First Edition - March 2000
i
NOTICE
The information in this document is subject to change without notice.
COMPAQ COMPUTER CORPORATION SHALL NOT BE LIABLE FOR TECHNICAL OR
EDITORIAL ERRORS OR OMISSIONS HEREIN; NOR FOR INCIDENTAL OR
CONSEQUENTIAL DAMAGES RESULTING FROM THE FURNISHING, PERFORMANCE,
OR USE OF THIS MATERIAL. IT IS THE RESPONSIBILITY OF MANUFACTURERS TO
ENSURE THAT DEVICES DESIGNED TO BE USED WITH COMPAQ PRODUCTS
COMPLY WITH FCC CLASS B EMISSIONS REQUIREMENTS.
This guide contains information protected by copyright. Except for use as a reference for the
described Compaq product, no part of this document may be photocopied or reproduced in any
form without prior written consent from Compaq Computer Corporation.
2000 Compaq Computer Corporation
All rights reserved.
Compaq and the Compaq logo are regiserted in the U.S. Patent and Trademark Office.
iPAQ is a trademark of Compaq Information Technologies Group, L.P.
Microsoft, Windows, Windows NT, and other names of Microsoft products referenced herein are trademarks or registered
trademarks of Microsoft Corporation.
Intel and Pentium are registered trademarks of Intel Corporation. Celeron and MMX are trademarks of Intel Corporation.
Product names mentioned in this document may be trademarks and/or registered trademarks of other companies.
For more information regarding specifications and Compaq-specific parts please contact Compaq
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Technical Reference Guide
For the
Compaq iPAQ Internet Device
First Edition – March 2000
Document Number 127M-0300A-WWEN

Technical Reference Guide
Compaq iPAQ Family of Internet Devices
First Edition –- March 2000
ii

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Compaq iPAQ Family of Internet Devices
First Edition - March 2000
iii
TABLE OF CONTENTS
CHAPTER 1 INTRODUCTION.............................................................................................................
1.1 ABOUT THIS GUIDE ........................................................................................................... 1-1
1.1.1 USING THIS GUIDE ..................................................................................................... 1-1
1.1.2 ADDITIONAL INFORMATION SOURCES.................................................................. 1-1
MODEL NUMBERING CONVENTION........................................................................................... 1-1
1.3 NOTATIONAL CONVENTIONS.......................................................................................... 1-2
1.3.1 VALUES........................................................................................................................ 1-2
1.3.2 RANGES........................................................................................................................ 1-2
1.3.3 SIGNAL LABELS.......................................................................................................... 1-2
1.3.4 REGISTER NOTATION AND USAGE ......................................................................... 1-2
1.3.5 BIT NOTATION ............................................................................................................ 1-2
1.4 COMMON ACRONYMS AND ABBREVIATIONS .............................................................. 1-3
CHAPTER 2 SYSTEM OVERVIEW.....................................................................................................
2.1 INTRODUCTION.................................................................................................................. 2-1
2.2 FEATURES AND OPTIONS ................................................................................................. 2-2
2.2.1 STANDARD FEATURES .............................................................................................. 2-2
2.2.2 OPTIONS....................................................................................................................... 2-3
2.3 MECHANICAL DESIGN ...................................................................................................... 2-4
2.3.1 CABINET LAYOUTS.................................................................................................... 2-4
2.3.2 CHASSIS LAYOUT....................................................................................................... 2-6
2.3.3 SYSTEM BOARD LAYOUTS ....................................................................................... 2-7
2.4 SYSTEM ARCHITECTURE.................................................................................................. 2-8
2.4.1 PROCESSORS ............................................................................................................. 2-10
2.4.2 CHIPSET ..................................................................................................................... 2-12
2.4.3 SUPPORT COMPONENTS.......................................................................................... 2-13
2.4.4 SYSTEM MEMORY.................................................................................................... 2-13
2.4.5 MASS STORAGE ........................................................................................................ 2-14
2.4.6 SERIAL AND PARALLEL INTERFACES .................................................................. 2-14
2.4.7 UNIVERSAL SERIAL BUS INTERFACE ................................................................... 2-14
2.4.8 GRAPHICS SUBSYSTEM........................................................................................... 2-14
2.4.9 AUDIO SUBSYSTEM ................................................................................................. 2-15
2.5 SPECIFICATIONS .............................................................................................................. 2-15
CHAPTER 3 PROCESSOR/MEMORY SUBSYSTEM ........................................................................
3.1 INTRODUCTION.................................................................................................................. 3-1
3.2 PROCESSOR......................................................................................................................... 3-2
3.2.1 CELERON PROCESSOR............................................................................................... 3-2
3.2.2 PENTIUM III PROCESSOR........................................................................................... 3-3
3.2.3 PROCESSOR UPGRADING .......................................................................................... 3-4
3.3 MEMORY SUBSYSTEM ...................................................................................................... 3-5
3.4 SUBSYSTEM CONFIGURATION ........................................................................................ 3-8

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Compaq iPAQ Family of Internet Devices
First Edition –- March 2000
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CHAPTER 4 SYSTEM SUPPORT.........................................................................................................
4.1 INTRODUCTION.................................................................................................................. 4-1
4.2 PCI BUS OVERVIEW........................................................................................................... 4-2
4.2.1 PCI BUS TRANSACTIONS........................................................................................... 4-3
4.2.2 PCI INTERRUPT MAPPING ......................................................................................... 4-6
4.2.3 PCI POWER MANAGEMENT SUPPORT..................................................................... 4-6
4.2.4 PCI SUB-BUSSES.......................................................................................................... 4-6
4.2.5 PCI CONFIGURATION................................................................................................. 4-7
4.3 AGP BUS OVERVIEW ......................................................................................................... 4-8
4.3.1 BUS TRANSACTIONS.................................................................................................. 4-8
4.3.2 AGP CONFIGURATION ............................................................................................. 4-11
4.4 INTERRUPTS ..................................................................................................................... 4-12
4.4.1 MASKABLE INTERRUPTS ........................................................................................ 4-12
4.4.2 NON-MASKABLE INTERRUPTS............................................................................... 4-14
4.5 INTERVAL TIMER............................................................................................................. 4-16
4.6 SYSTEM CLOCK DISTRIBUTION .................................................................................... 4-16
4.7 REAL-TIME CLOCK AND CONFIGURATION MEMORY............................................... 4-17
4.7.1 CMOS ARCHIVE ........................................................................................................ 4-18
4.7.2 STANDARD CMOS LOCATIONS .............................................................................. 4-18
4.7.3 CMOS FEATURE BITS............................................................................................... 4-26
4.8 SYSTEM MANAGEMENT................................................................................................. 4-27
4.8.1 SECURITY FUNCTIONS ............................................................................................ 4-27
4.8.2 POWER MANAGEMENT ........................................................................................... 4-28
4.8.3 THERMAL SENSING AND COOLING ...................................................................... 4-28
4.9 SYSTEM I/O MAP .............................................................................................................. 4-29
CHAPTER 5 INPUT/OUTPUT INTERFACES.....................................................................................
5.1 INTRODUCTION.................................................................................................................. 5-1
5.2 ENHANCED IDE INTERFACE ............................................................................................ 5-1
5.2.1 IDE PROGRAMMING................................................................................................... 5-1
5.2.2 IDE CONNECTOR ........................................................................................................ 5-3
5.3 DISKETTE DRIVE INTERFACE.......................................................................................... 5-4
5.4 SERIAL INTERFACE ........................................................................................................... 5-5
5.4.1 RS-232 INTERFACE ..................................................................................................... 5-5
5.4.2 SERIAL TEST INTERFACE ........................................................................................ 5-6
5.4.3 SERIAL INTERFACE PROGRAMMING ...................................................................... 5-6
5.5 PARALLEL INTERFACE ..................................................................................................... 5-8
5.5.1 STANDARD PARALLEL PORT MODE ....................................................................... 5-8
5.5.2 ENHANCED PARALLEL PORT MODE....................................................................... 5-9
5.5.3 EXTENDED CAPABILITIES PORT MODE ................................................................. 5-9
5.5.4 PARALLEL INTERFACE PROGRAMMING.............................................................. 5-10
5.5.5 PARALLEL INTERFACE CONNECTOR ................................................................... 5-14
5.6 KEYBOARD/POINTING DEVICE INTERFACE ............................................................... 5-15
5.6.1 KEYBOARD INTERFACE OPERATION ................................................................... 5-15
5.6.2 POINTING DEVICE INTERFACE OPERATION ....................................................... 5-17
5.6.3 KEYBOARD/POINTING DEVICE INTERFACE PROGRAMMING ......................... 5-17
5.6.4 KEYBOARD/POINTING DEVICE INTERFACE CONNECTOR................................ 5-21

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Compaq iPAQ Family of Internet Devices
First Edition - March 2000
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5.7 UNIVERSAL SERIAL BUS INTERFACE........................................................................... 5-22
5.7.1 USB DATA FORMATS ............................................................................................... 5-22
5.7.2 USB PROGRAMMING................................................................................................ 5-24
5.7.3 USB CONNECTOR ..................................................................................................... 5-25
5.7.4 USB CABLE DATA..................................................................................................... 5-25
5.8 AUDIO SUBSYSTEM......................................................................................................... 5-26
5.8.1 FUNCTIONAL ANALYSIS ......................................................................................... 5-26
5.8.2 AC97 AUDIO CONTROLLER..................................................................................... 5-28
5.8.3 AC97 LINK BUS ......................................................................................................... 5-28
5.8.4 AUDIO CODEC........................................................................................................... 5-29
5.8.5 AUDIO PROGRAMMING........................................................................................... 5-30
5.8.6 AUDIO SPECIFICATIONS ......................................................................................... 5-31
5.9 NETWORK INTERFACE CONTROLLER.......................................................................... 5-32
5.9.1 WAKE ON LAN .......................................................................................................... 5-33
5.9.2 ALERT ON LAN ......................................................................................................... 5-33
5.9.3 POWER MANAGEMENT SUPPORT.......................................................................... 5-34
5.9.4 NIC PROGRAMMING................................................................................................. 5-35
CHAPTER 6 GRAPHICS SUBSYSTEM...............................................................................................
6.1 INTRODUCTION.................................................................................................................. 6-1
6.2 FUNCTIONAL DESCRIPTION............................................................................................. 6-2
6.2.1 FEATURE SUMMARY ................................................................................................. 6-3
6.3 DISPLAY MODES ................................................................................................................6-4
6.4 UPGRADING ........................................................................................................................ 6-4
6.5 PROGRAMMING..................................................................................................................6-5
6.5.1 CONFIGURATION........................................................................................................ 6-5
6.5.2 CONTROL..................................................................................................................... 6-5
6.6 MONITOR POWER MANAGEMENT CONTROL ............................................................... 6-6
6.7 MONITOR CONNECTOR .................................................................................................... 6-6
CHAPTER 7 POWER SUPPLY AND DISTRIBUTION.......................................................................
7.1 INTRODUCTION.................................................................................................................. 7-1
7.2 POWER SUPPLY ASSEMBLY/CONTROL .......................................................................... 7-1
7.2.1 POWER SUPPLY ASSEMBLY...................................................................................... 7-2
7.2.2 POWER CONTROL....................................................................................................... 7-3
7.3 POWER DISTRIBUTION...................................................................................................... 7-4
7.3.1 3.3/5/12 VDC DISTRIBUTION...................................................................................... 7-4
7.3.2 LOW VOLTAGE DISTRIBUTION................................................................................ 7-4
7.4 SIGNAL DISTRIBUTION ..................................................................................................... 7-5

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Compaq iPAQ Family of Internet Devices
First Edition –- March 2000
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CHAPTER 8 BIOS ROM .......................................................................................................................
8.1 INTRODUCTION.................................................................................................................. 8-1
8.2 DESKTOP MANAGEMENT SUPPORT ............................................................................... 8-2
8.2.1 SYSTEM ID................................................................................................................... 8-4
8.2.2 SYSTEM INFORMATION TABLE ............................................................................... 8-4
8.2.3 EDID RETRIEVE .......................................................................................................... 8-5
8.2.4 DRIVE FAULT PREDICTION....................................................................................... 8-5
8.2.5 SYSTEM MAP RETRIEVAL......................................................................................... 8-6
8.2.6 FLASH ROM FUNCTIONS ........................................................................................... 8-7
8.2.7 POWER BUTTON FUNCTIONS ................................................................................... 8-7
8.2.8 ACCESSING CMOS...................................................................................................... 8-8
8.2.9 ACCESSING CMOS FEATURE BITS........................................................................... 8-8
8.2.10 SECURITY FUNCTIONS ............................................................................................ 8-10
8.3 MEMORY DETECTION AND CONFIGURATION............................................................ 8-11
8.4 PNP SUPPORT.................................................................................................................... 8-12
8.4.1 SMBIOS....................................................................................................................... 8-13
8.5 POWER MANAGEMENT FUNCTIONS ............................................................................ 8-14
8.5.1 INDEPENDENT PM SUPPORT .................................................................................. 8-14
8.5.2 ACPI SUPPORT........................................................................................................... 8-15
8.5.3 APM 1.2 SUPPORT ..................................................................................................... 8-15
8.6 USB LEGACY SUPPORT ................................................................................................... 8-17
8.7 BIOS UPGRADING............................................................................................................. 8-18
APPENDIX A ERROR MESSAGES AND CODES...............................................................................
A.1 INTRODUCTION.................................................................................................................A-1
A.2 POWER-ON MESSAGES..................................................................................................... A-1
A.3 BEEP/KEYBOARD LED CODES ........................................................................................ A-1
A.4 POWER-ON SELF TEST (POST) MESSAGES.................................................................... A-2
A.5 PROCESSOR ERROR MESSAGES (1XX-XX) ...................................................................... A-3
A.6 MEMORY ERROR MESSAGES (2XX-XX)........................................................................... A-4
A.7 KEYBOARD ERROR MESSAGES (30X-XX) ....................................................................... A-4
A.8 PRINTER ERROR MESSAGES (4XX-XX) ............................................................................ A-5
A.9 VIDEO (GRAPHICS) ERROR MESSAGES (5XX-XX) .......................................................... A-5
A.10 DISKETTE DRIVE ERROR MESSAGES (6XX-XX) ......................................................... A-6
A.11 SERIAL INTERFACE ERROR MESSAGES (11XX-XX) ................................................... A-6
A.12 MODEM COMMUNICATIONS ERROR MESSAGES (12XX-XX).................................... A-7
A.13 SYSTEM STATUS ERROR MESSAGES (16XX-XX) ........................................................ A-8
A.14 HARD DRIVE ERROR MESSAGES (17XX-XX) ............................................................... A-8
A.15 HARD DRIVE ERROR MESSAGES (19XX-XX) ............................................................... A-9
A.16 VIDEO (GRAPHICS) ERROR MESSAGES (24XX-XX) .................................................... A-9
A.17 AUDIO ERROR MESSAGES (3206-XX)......................................................................... A-10
A.18 DVD/CD-ROM ERROR MESSAGES (33XX-XX)............................................................ A-10
A.19 NETWORK INTERFACE ERROR MESSAGES (60XX-XX) ........................................... A-10
A.20 SCSI INTERFACE ERROR MESSAGES (65XX-XX, 66XX-XX, 67XX-XX) ....................... A-11
A.21 POINTING DEVICE INTERFACE ERROR MESSAGES (8601-XX).............................. A-11
A.22 CEMM PRIVILEDGED OPS ERROR MESSAGES........................................................ A-12
A.23 CEMM EXCEPTION ERROR MESSAGES ................................................................... A-12

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Compaq iPAQ Family of Internet Devices
First Edition - March 2000
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APPENDIX B ASCII CHARACTER SET .............................................................................................
B.1 INTRODUCTION..................................................................................................................B-1
APPENDIX C KEYBOARD ...................................................................................................................
C.1 INTRODUCTION..................................................................................................................C-1
C.2 KEYSTROKE PROCESSING................................................................................................C-2
C.2.1 PS/2-TYPE KEYBOARD TRANSMISSIONS................................................................C-3
C.2.2 USB-TYPE KEYBOARD TRANSMISSIONS................................................................C-4
C.2.3 KEYBOARD LAYOUTS ...............................................................................................C-5
C.2.4 KEYS.............................................................................................................................C-8
C.2.5 KEYBOARD COMMANDS.........................................................................................C-11
C.2.6 SCAN CODES .............................................................................................................C-11
C.3 CONNECTORS ...................................................................................................................C-15

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Compaq iPAQ Family of Internet Devices
First Edition –- March 2000
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LIST OF FIGURES
FIGURE 2–1. COMPAQ IPAQ INTERNET DEVICE WITH MONITOR............................................................. 2-1
FIGURE 2–2. COMPAQ IPAQ INTERNET DEVICE, FRONT VIEW................................................................ 2-4
FIGURE 2–3. COMPAQ IPAQ INTERNET DEVICE, REAR VIEWS................................................................ 2-5
FIGURE 2–4. COMPAQ IPAQ INTERNET DEVICE CHASSIS LAYOUT, RIDE SIDE VIEW................................ 2-6
FIGURE 2–5. COMPAQ IPAQ SYSTEM BOARD LAYOUTS ......................................................................... 2-7
FIGURE 2–6. COMPAQ IPAQ ARCHITECTURE, BLOCK DIAGRAM .............................................................. 2-9
FIGURE 2–7. PROCESSOR ASSEMBLY AND MOUNTING .......................................................................... 2-11
FIGURE 3–1. PROCESSOR/MEMORY SUBSYSTEM ARCHITECTURE ............................................................ 3-1
FIGURE 3–2. CELERON PROCESSOR INTERNAL ARCHITECTURE ............................................................... 3-2
FIGURE 3–3. PENTIUM III PROCESSOR INTERNAL ARCHITECTURE........................................................... 3-3
FIGURE 3–4. SYSTEM MEMORY MAP..................................................................................................... 3-7
FIGURE 4-1. PCI BUS DEVICES AND FUNCTIONS ..................................................................................... 4-2
FIGURE 4-2. TYPE 0 CONFIGURATION CYCLE......................................................................................... 4-4
FIGURE 4-3. PCI CONFIGURATION SPACE MAP ...................................................................................... 4-5
FIGURE 4-4. AGP 1X DATA TRANSFER (PEAK TRANSFER RATE: 266 MB/S)........................................... 4-9
FIGURE 4-5. AGP 2X DATA TRANSFER (PEAK TRANSFER RATE: 532 MB/S)......................................... 4-10
FIGURE 4-6. MASKABLE INTERRUPT PROCESSING, BLOCK DIAGRAM..................................................... 4-12
FIGURE 4-7. CONFIGURATION MEMORY MAP....................................................................................... 4-17
FIGURE 5-1. 40-PIN PRIMARY IDE CONNECTOR (ON SYSTEM BOARD)...................................................... 5-3
FIGURE 5-2. 50-PIN SECONDARY IDE CONNECTOR (ON SYSTEM AND DAUGHTER BOARDS). ...................... 5-4
FIGURE 5-3. SERIAL INTERFACE CONNECTOR (MALE DB-9 AS VIEWED FROM REAR OF CHASSIS) ............... 5-5
FIGURE 5-4. SERIAL INTERFACE HEADER (ON LEGACY-FREE SYSTEM BOARD) ........................................... 5-6
FIGURE 5-5. PARALLEL INTERFACE CONNECTOR (FEMALE DB-25 AS VIEWED FROM REAR OF CHASSIS).... 5-14
FIGURE 5-6. 8042-TO-KEYBOARD TRANSMISSION OF CODE EDH, TIMING DIAGRAM ............................. 5-15
FIGURE 5-7. KEYBOARD OR POINTING DEVICE INTERFACE CONNECTOR ................................................ 5-21
FIGURE 5-8. USB I/F, BLOCK DIAGRAM............................................................................................... 5-22
FIGURE 5-9. USB PACKET FORMATS.................................................................................................... 5-23
FIGURE 5-10. UNIVERSAL SERIAL BUS CONNECTOR .............................................................................. 5-25
FIGURE 5-11. AUDIO SUBSYSTEM FUNCTIONAL BLOCK DIAGRAM ......................................................... 5-27
FIGURE 5-12. AC’97 LINK BUS PROTOCOL .......................................................................................... 5-28
FIGURE 5-13. AD1881 AUDIO CODEC FUNCTIONAL BLOCK DIAGRAM................................................... 5-29
FIGURE 5-14. 10/100 TX NETWORK INTERFACE CONTROLLER BLOCK DIAGRAM................................... 5-32
FIGURE 5-15. ETHERNET TPE CONNECTOR (RJ-45, VIEWED FROM CARD EDGE)..................................... 5-36
FIGURE 6-1. GRAPHICS SUBSYSTEM BLOCK DIAGRAM ............................................................................ 6-2
FIGURE 6-2. 82810E/DC-100 INTEGRATED GRAPHICS CONTROLLER ....................................................... 6-3
FIGURE 7–1. POWER DISTRIBUTION AND CONTROL, BLOCK DIAGRAM..................................................... 7-1
FIGURE 7–2. POWER CABLE DIAGRAM .................................................................................................. 7-4
FIGURE 7–3. SIGNAL DISTRIBUTION DIAGRAM....................................................................................... 7-5
FIGURE 7–4. HEADER PINOUTS ............................................................................................................. 7-6
FIGURE B–1. ASCII CHARACTER SET ...................................................................................................B-1

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FIGURE C–1. KEYSTROKE PROCESSING ELEMENTS, BLOCK DIAGRAM ....................................................C-2
FIGURE C–2. PS/2 KEYBOARD-TO-SYSTEM TRANSMISSION, TIMING DIAGRAM ......................................C-3
FIGURE C–3. U.S. ENGLISH (101-KEY) KEYBOARD KEY POSITIONS .......................................................C-5
FIGURE C–4. NATIONAL (102-KEY) KEYBOARD KEY POSITIONS ............................................................C-5
FIGURE C–5. U.S. ENGLISH WINDOWS (101W-KEY) KEYBOARD KEY POSITIONS ...................................C-6
FIGURE C–6. NATIONAL WINDOWS (102W-KEY) KEYBOARD KEY POSITIONS ........................................C-6
FIGURE C–7. EASY ACCESS KEY POSITIONS ..........................................................................................C-7
FIGURE C–8. PS/2 KEYBOARD CABLE CONNECTOR (MALE).................................................................C-15
FIGURE C–9. USB KEYBOARD CABLE CONNECTOR (MALE).................................................................C-15

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LIST OF TABLES
TABLE 1–1. ACRONYMS AND ABBREVIATIONS....................................................................................... 1-3
TABLE 2-1. FEATURE DIFFERENCE MATRIX ........................................................................................... 2-2
TABLE 2-2. ARCHITECTURAL COMPARISON ............................................................................................. 2-8
TABLE 2-3. INTEL 810E CHIPSET COMPARISON .................................................................................... 2-12
TABLE 2-4. SUPPORT COMPONENT FUNCTIONS .................................................................................... 2-13
TABLE 2-5. ENVIRONMENTAL SPECIFICATIONS .................................................................................... 2-15
TABLE 2-6. ELECTRICAL SPECIFICATIONS............................................................................................ 2-15
TABLE 2-7. PHYSICAL SPECIFICATIONS................................................................................................ 2-16
TABLE 2-8. MULTIBAY 24X CD-ROM DRIVE SPECIFICATIONS............................................................. 2-16
TABLE 2-9. MULTIBAY 24X CD-ROM DRIVE SPECIFICATIONS............................................................. 2-17
TABLE 2-10. HARD DRIVE SPECIFICATIONS ......................................................................................... 2-17
TABLE 3–1. CELERON PROCESSOR STATISTICAL COMPARISON ............................................................... 3-2
TABLE 3–2. PENTIUM III PROCESSOR STATISTICAL COMPARISON ........................................................... 3-3
TABLE 3–3. SPD ADDRESS MAP (SDRAM DIMM)................................................................................. 3-6
TABLE 3–4. HOST/PCI BRIDGE CONFIGURATION REGISTERS (GMCH, FUNCTION 0)................................ 3-8
TABLE 4-1. PCI DEVICE CONFIGURATION ACCESS................................................................................. 4-4
TABLE 4-2. SYSTEM BOARD PCI DEVICE IDENTIFICATION ..................................................................... 4-5
TABLE 4-3. LPC BRIDGE CONFIGURATION REGISTERS (ICH, FUNCTION 0).............................................. 4-7
TABLE 4-4. PCI/AGP BRIDGE CONFIGURATION REGISTERS (MCH, FUNCTION 1) .................................. 4-11
TABLE 4-5. MASKABLE INTERRUPT PRIORITIES AND ASSIGNMENTS ...................................................... 4-13
TABLE 4-6. MASKABLE INTERRUPT CONTROL REGISTERS .................................................................... 4-13
TABLE 4-7. INTERVAL TIMER FUNCTIONS............................................................................................ 4-16
TABLE 4-8. INTERVAL TIMER CONTROL REGISTERS ............................................................................. 4-16
TABLE 4-9. CLOCK GENERATION AND DISTRIBUTION........................................................................... 4-16
TABLE 4-10. CONFIGURATION MEMORY (CMOS) MAP ....................................................................... 4-18
TABLE 4-11. SYSTEM I/O MAP ........................................................................................................... 4-29
TABLE 5–1. IDE PCI CONFIGURATION REGISTERS ................................................................................ 5-2
TABLE 5–2. IDE BUS MASTER CONTROL REGISTERS .............................................................................. 5-2
TABLE 5–3. 40-PIN PRIMARY IDE CONNECTOR PINOUT......................................................................... 5-3
TABLE 5–4. 50-PIN SECONDARY IDE CONNECTOR PINOUT.................................................................... 5-4
TABLE 5–5. DB-9 SERIAL CONNECTOR PINOUT...................................................................................... 5-5
TABLE 5–6. SERIAL INTERFACE CONFIGURATION REGISTERS.................................................................. 5-6
TABLE 5–7. SERIAL INTERFACE CONTROL REGISTERS ............................................................................ 5-7
TABLE 5–8. PARALLEL INTERFACE CONFIGURATION REGISTERS........................................................... 5-10
TABLE 5–9. PARALLEL INTERFACE CONTROL REGISTERS ...................................................................... 5-11
TABLE 5–10. DB-25 PARALLEL CONNECTOR PINOUT .......................................................................... 5-14
TABLE 5–11. 8042-TO-KEYBOARD COMMANDS .................................................................................. 5-16
TABLE 5–12. KEYBOARD INTERFACE CONFIGURATION REGISTERS ....................................................... 5-17
TABLE 5–13. CPU COMMANDS TO THE 8042...................................................................................... 5-19
TABLE 5–14. KEYBOARD/POINTING DEVICE CONNECTOR PINOUT ........................................................ 5-21
TABLE 5–15. USB INTERFACE CONFIGURATION REGISTERS ................................................................. 5-24
TABLE 5–16. USB CONTROL REGISTERS............................................................................................. 5-24
TABLE 5–17. USB CONNECTOR PINOUT.............................................................................................. 5-25
TABLE 5–18. USB CABLE LENGTH DATA............................................................................................ 5-25

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TABLE 5–19. AC’97 AUDIO CONTROLLER PCI CONFIGURATION REGISTERS ........................................ 5-30
TABLE 5–20. AC’97 AUDIO CODEC CONTROL REGISTERS ................................................................... 5-30
TABLE 5–21. AUDIO SUBSYSTEM SPECIFICATIONS ............................................................................... 5-31
TABLE 5–22. AOL EVENTS ................................................................................................................ 5-33
TABLE 5–23. NIC CONTROLLER PCI CONFIGURATION REGISTERS ....................................................... 5-35
TABLE 5–24. NIC CONTROL REGISTERS ............................................................................................. 5-35
TABLE 5–25. 82559 NIC OPERATING SPECIFICATIONS ........................................................................ 5-36
TABLE 6-1. INTEL GRAPHICS DISPLAY MODES....................................................................................... 6-4
TABLE 6-2. PCI CONFIGURATION SPACE REGISTERS .............................................................................. 6-5
TABLE 6-3. STANDARD VGA MODE I/O MAPPING ................................................................................ 6-5
TABLE 6-4. MONITOR POWER MANAGEMENT CONDITIONS .................................................................... 6-6
TABLE 6-5. DB-15 MONITOR CONNECTOR PINOUT................................................................................ 6-6
TABLE 8-1. DESKTOP MANAGEMENT FUNCTIONS (INT15) ..................................................................... 8-2
TABLE 8-2. CMOS FEATURE BITS ........................................................................................................ 8-9
TABLE 8-3. PNP BIOS FUNCTIONS ..................................................................................................... 8-12
TABLE 8-4. APM BIOS FUNCTIONS (INT15) ...................................................................................... 8-17
TABLE A–1. POWER-ON MESSAGES ..................................................................................................... A-1
TABLE A–2. BEEP/KEYBOARD LED CODES.......................................................................................... A-1
TABLE A–3. POWER-ON SELF TEST (POST) MESSAGES........................................................................ A-2
TABLE A–4. SYSTEM ERROR MESSAGES............................................................................................... A-3
TABLE A–5. MEMORY ERROR MESSAGES............................................................................................. A-4
TABLE A–6. KEYBOARD ERROR MESSAGES.......................................................................................... A-4
TABLE A–7. PRINTER ERROR MESSAGES .............................................................................................. A-5
TABLE A–8. VIDEO (GRAPHICS) ERROR MESSAGES .............................................................................. A-5
TABLE A–9. DISKETTE DRIVE ERROR MESSAGES.................................................................................. A-6
TABLE A–10. SERIAL INTERFACE ERROR MESSAGES............................................................................. A-6
TABLE A–11. SERIAL INTERFACE ERROR MESSAGES............................................................................. A-7
TABLE A–12. SYSTEM STATUS ERROR MESSAGES ................................................................................ A-8
TABLE A–13. HARD DRIVE ERROR MESSAGES...................................................................................... A-8
TABLE A–14. HARD DRIVE ERROR MESSAGES...................................................................................... A-9
TABLE A–15. HARD DRIVE MESSAGES ................................................................................................. A-9
TABLE A–16. AUDIO ERROR MESSAGES ............................................................................................. A-10
TABLE A–17. DVD/CD-ROM DRIVE ERROR MESSAGES .................................................................... A-10
TABLE A–18. NETWORK INTERFACE ERROR MESSAGES ...................................................................... A-10
TABLE A–19. SCSI INTERFACE ERROR MESSAGES ............................................................................. A-11
TABLE A–20. POINTING DEVICE INTERFACE ERROR MESSAGES........................................................... A-11
TABLE A–21. CEMM PRIVILEGED OPS ERROR MESSAGES.................................................................. A-12
TABLE A–22. CEMM EXCEPTION ERROR MESSAGES ......................................................................... A-12
TABLE C–1. KEYBOARD-TO-SYSTEM COMMANDS ...............................................................................C-11
TABLE C–2. KEYBOARD SCAN CODES.................................................................................................C-12

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Compaq iPAQ Family of Internet Devices
First Edition - March 2000
1-1
Chapter 1
INTRODUCTION
1. Chapter 1 INTRODUCTION
1.1 ABOUT THIS GUIDE
This guide provides technical information about the Compaq iPAQ Family of Internet Devices.
This document includes information regarding system design, function, and features that can be
used by programmers, engineers, technicians, and system administrators.
This guide and any applicable addendum are available online at the following location:
http://www.compaq.com/support/techpubs/technical_reference_guides/index.html
1.1.1 USING THIS GUIDE
The chapters of this guide primarily describe the hardware and firmware elements and primarily
deal with the system board and the power supply assembly. The appendices contain general
information about standard peripheral devices such as the keyboard.
1.1.2 ADDITIONAL INFORMATION SOURCES
For more information on chipset components mentioned in this guide refer to the indicated
manufacturers’ documentation, which may be available at the following online sources:
♦Compaq Computer Corporation: http://www.compaq.com
♦Intel Corporation: http://www.intel.com
♦Standard Microsystems Corporation: http://www.smsc.com
1.2 MODEL NUMBERING CONVENTION
The model numbering convention for Compaq iPAQ units is as follows:
iPAQ/XNNN/Nb/N/NNN
Memory (in MB)
Operating system: 4 = Win NT 4.0; 9 = Win95/98
Chipset type (b = 810e)
Hard drive size (in GB)
Processor speed (in MHz)
Processor type: C = Celeron; P = Pentium

Chapter 1 Introduction
Compaq iPAQ Family of Internet Devices
First Edition – March 2000
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1.3 NOTATIONAL CONVENTIONS
1.3.1 VALUES
Hexadecimal values are indicated by a numerical or alpha-numerical value followed by the letter
“h.”Binary values are indicated by a value of ones and zeros followed by the letter “b.”
Numerical values that have no succeeding letter can be assumed to be decimal.
1.3.2 RANGES
Ranges or limits for a parameter are shown using the following methods:
Example A: Bits <7..4> = bits 7, 6, 5, and 4.
Example B: IRQ3-7, 9 = IRQ signals 3 through 7, and IRQ signal 9
1.3.3 SIGNAL LABELS
Signal names are indicated using abbreviations, acronyms, or, if possible, the full signal name in
all capital letters. Signals that are meant to be active (asserted) low are indicated with a dash
immediately following the name.
1.3.4 REGISTER NOTATION AND USAGE
This guide uses standard Intel naming conventions in discussing the microprocessor’s (CPU)
internal registers. Registers that are accessed through programmable I/O using an indexing
scheme are indicated using the following format:
03C5.17h
Index port
Data port
In the example above, register 03C5.17h is accessed by writing the index port value 17h to the
index address (03C4h), followed by a write to or a read from port 03C5h.
1.3.5 BIT NOTATION
Bit values are labeled with bit <0> representing the least-significant bit (LSb) and bit <7>
representing the most-significant bit (MSb) of a byte. Bytes, words, double words, and quad
words are typically shown with most-significant portions on the left or top and the least-
significant portions on the right or bottom respectively.

Technical Reference Guide
Compaq iPAQ Family of Internet Devices
First Edition - March 2000
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1.4 COMMON ACRONYMS AND ABBREVIATIONS
Table 1-1 lists the acronyms and abbreviations used in this guide.
Table 1–1. Acronyms and Abbreviations
Table 1-1.
Acronyms and Abbreviations
Acronym/Abbreviation Description
A ampere
AC alternating current
ACPI Advanced Configuration and Power Interface
A/D analog-to-digital
AGP Accelerated graphics port
API application programming interface
APM advanced power management
AOL Alert-ON-LAN
ASIC application-specific integrated circuit
AT 1) attention (modem commands) 2) 286-based PC architecture
ATA AT attachment (IDE protocol)
ATAPI AT attachment w/packet interface extensions
AVI audio-video interleaved
AVGA Advanced VGA
BAT Basic assurance test
BCD binary-coded decimal
BIOS basic input/output system
bis second/new revision
BitBLT bit block transfer
BNC Bayonet Neill-Concelman (connector)
bps or b/s bits per second
BSP Bootstrap processor
BTO Built to order
CAS column address strobe
CD compact disk
CD-ROM compact disk read-only memory
CDS compact disk system
CF carry flag
CGA color graphics adapter
Ch channel
cm centimeter
CMC cache/memory controller
CMOS complimentary metal-oxide semiconductor (configuration memory)
Cntlr controller
Cntrl control
codec compressor/decompressor
CPQ Compaq
CPU central processing unit
CRT cathode ray tube
CSM Compaq system management / Compaq server management
CTO Configure to order
DAA direct access arrangement
DAC digital-to-analog converter
DC direct current
DCH DOS compatibility hole
DDC Display Data Channel
DF direction flag
Continued

Chapter 1 Introduction
Compaq iPAQ Family of Internet Devices
First Edition –March 2000
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Table 1-1. Acronyms and Abbreviations
Continued
Acronym/Abbreviation Description
DIMM dual inline memory module
DIN Deutche IndustriNorm (connector standard)
DIP dual inline package
DMA direct memory access
DMI Desktop management interface
dpi dots per inch
DRAM dynamic random access memory
DRQ data request
EDID extended display identification data
EDO extended data out (RAM type)
EEPROM electrically eraseable PROM
EGA enhanced graphics adapter
EIA Electronic Industry Association
EISA extended ISA
EPP enhanced parallel port
EIDE enhanced IDE
ESCD Extended System Configuration Data (format)
EV Environmental Variable (data)
ExCA Exchangeable Card Architecture
FIFO first in / first out
FL flag (register)
FM frequency modulation
FPM fast page mode (RAM type)
FPU Floating point unit (numeric or math coprocessor)
FPS Frames per second
ft foot
GB gigabyte
GMCH Graphics/memory controller hub
GND ground
GPIO general purpose I/O
GPOC general purpose open-collector
GART Graphics address re-mapping table
GUI graphics user interface
h hexadecimal
HW hardware
hex hexadecimal
Hz hertz
ICH I/O controller hub
IDE integrated drive element
IEEE Institute of Electrical and Electronic Engineers
IF interrupt flag
I/F interface
in inch
INT interrupt
I/O input/output
IPL initial program loader
IrDA InfraRed Data Association
IRQ interrupt request
ISA industry standard architecture
JEDEC Joint Electron Device Engineering Council
Kb / KB kilobits / kilobytes (x 1024 bits / x 1024 bytes)
Kb/s kilobits per second
kg kilogram
KHz kilohertz
kv kilovolt
Continued

Technical Reference Guide
Compaq iPAQ Family of Internet Devices
First Edition - March 2000
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Table 1-1. Acronyms and Abbreviations
Continued
Acronym/Abbreviation Description
lb pound
LAN local area network
LCD liquid crystal display
LED light-emitting diode
LIF low insertion force (socket)
LPC Low pin count
LSI large scale integration
LSb / LSB least significant bit / least significant byte
LUN logical unit (SCSI)
MCH Memory controller hub
MMX multimedia extensions
MPEG Motion Picture Experts Group
ms millisecond
MSb / MSB most significant bit / most significant byte
mux multiplex
MVA motion video acceleration
MVW motion video window
n variable parameter/value
NIC network interface card/controller
NiCad nickel cadmium
NiMH nickel-metal hydride
NMI non-maskable interrupt
NRZI Non-return-to-zero inverted
ns nanosecond
NT nested task flag
NTSC National Television Standards Committee
NVRAM non-volatile random access memory
OEM original equipment manufacturer
OS operating system
PAL 1. programmable array logic 2. phase altering line
PC Internet Device
PCI peripheral component interconnect
PCM pulse code modulation
PCMCIA Internet Device Memory Card International Association
PF parity flag
PIN personal identification number
PIO Programmed I/O
POST power-on self test
PROM programmable read-only memory
PTR pointer
RAM random access memory
RAS row address strobe
rcvr receiver
RF resume flag
RGB red/green/blue (monitor input)
RH Relative humidity
RIMM RDRAM inline memory module
RMS root mean square
ROM read-only memory
RPM revolutions per minute
RTC real time clock
R/W read/write
Continued