Cypress Semiconductor CY62146EV30 User manual

CY62146EV30 MoBL®
4-Mbit (256K x 16) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-05567 Rev. *C Revised March 26, 2007
Features
• Very high speed: 45 ns
• Wide voltage range: 2.20V–3.60V
• Pin compatible with CY62146DV30
• Ultra low standby power
— Typical standby current: 1 µA
— Maximum standby current: 7 µA
• Ultra low active power
— Typical active current: 2 mA @ f = 1 MHz
• Easy memory expansion with CE, and OE features
• Automatic power down when deselected
• CMOS for optimum speed and power
• Available in a Pb-free 48-ball VFBGA and 44-pin TSOP II
packages
Functional Description [1]
The CY62146EV30 is a high performance CMOS static RAM
organized as 256K words by 16 bits. This device features
advanced circuit design to provide ultra low active current.
This is ideal for providing More Battery Life™ (MoBL®) in
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
reduces power consumption by 80% when addresses are not
toggling. The device can also be put into standby mode
reducing power consumption by more than 99% when
deselected (CE HIGH). The input and output pins (IO0through
IO15) are placed in a high impedance state when:
• Deselected (CE HIGH)
• Outputs are disabled (OE HIGH)
• Both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH)
• Write operation is active (CE LOW and WE LOW)
Write to the device by taking Chip Enable (CE) and Write
Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW,
then data from IO pins (IO0through IO7), is written into the
location specified on the address pins (A0through A17). If Byte
High Enable (BHE) is LOW, then data from IO pins (IO8
through IO15) is written into the location specified on the
address pins (A0through A17).
Read from the device by taking Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH.
If Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appear on IO0to IO7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on IO8to IO15. See the “Truth Table” on page 9 for a
complete description of read and write modes.
Product Portfolio
Product VCC Range (V) Speed
(ns)
Power Dissipation
Operating ICC (mA)
Standby ISB2 (µA)
f = 1 MHz f = fmax
Min Typ [2] Max Typ [2] Max Typ [2] Max Typ [2] Max
CY62146EV30LL 2.2 3.0 3.6 45 ns 2 2.5 15 20 1 7
Notes:
1. For best practice recommendations, please refer to the Cypress application note System Design Guidelines on http://www.cypress.com.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA= 25°C.

CY62146EV30 MoBL®
Document #: 38-05567 Rev. *C Page 2 of 12
Logic Block Diagram
Pin Configurations [3, 4]
256K x 16
RAM Array IO0–IO7
ROW DECODER
A8
A7
A6
A5
A2
COLUMN DECODER
A11
A12 A13
A14
A15
SENSE AMPS
DATA IN DRIVERS
OE
A4
A3IO8–IO15
CE
WE
BHE
A16
A0
A1
A9
A10
BLE
A17
1
2
3
4
5
6
7
8
9
11
14 31
32
36
35
34
33
37
40
39
38
12
13
41
44
43
42
16
15
29
30
A
5
18
17
20
19
27
28
25
26
22
21
23
24
A
6
A
7
A
4
A
3
A
2
A
1
A
0
A
15
A
16
A
8
A
9
A
10
A
11
A
13
A
14
A
12
OE
BHE
BLE
CE
WE
IO
0
IO
1
IO
2
IO
3
IO
4
IO
5
IO
6
IO
7
IO
8
IO
9
IO
10
IO
11
IO
12
IO
13
IO
14
IO
15
V
CC
V
CC
V
SS
V
SS
NC
10
A
17
48-ball VFBGA
44-pin TSOP II
Top View Top View
WE
A11
A10
A6
A0
A3CE
IO10
IO8
IO9
A4
A5
IO11
IO13
IO12
IO14
IO15
VSS
A9
A8
OE
A7
IO0
BHE
NC
A2
A1
BLE
IO2
IO1
IO3
IO4
IO5IO6
IO7
A15
A14
A13 A12
NC
NC NC
326
5
41
D
E
B
A
C
F
G
H
A16
NC
VCC
VCC VSS
A17
Notes:
3. NC pins are not connected on the die.
4. Pins H1, G2, and H6 in the BGA package are address expansion pins for 8 Mb, 16 Mb and 32 Mb, respectively.

CY62146EV30 MoBL®
Document #: 38-05567 Rev. *C Page 3 of 12
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of
the device. These user guidelines are not tested.
Storage Temperature ................................ –65°C to + 150°C
Ambient Temperature with
Power Applied ........................................... –55°C to + 125°C
Supply Voltage to Ground
Potential .............................–0.3V to + 3.9V (VCCmax + 0.3V)
DC Voltage Applied to Outputs
in High-Z State [5, 6]................–0.3V to 3.9V (VCCmax + 0.3V)
DC Input Voltage [5, 6] ........... –0.3V to 3.9V (VCC max + 0.3V)
Output Current into Outputs (LOW) ............................ 20 mA
Static Discharge Voltage ......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-up Current ..................................................... >200 mA
Operating Range
Device Range
Ambient
Temperature VCC [7]
CY62146EV30 Industrial –40°C to +85°C 2.2V to 3.6V
Electrical Characteristics (Over the Operating Range)
Parameter Description Test Conditions
45 ns
UnitMin Typ [2] Max
VOH Output HIGH Voltage IOH = –0.1 mA 2.0 V
IOH = –1.0 mA, VCC >2.70V 2.4 V
VOL Output LOW Voltage IOL = 0.1 mA 0.4 V
IOL = 2.1 mA, VCC >2.70V 0.4 V
VIH Input HIGH Voltage VCC = 2.2V to 2.7V 1.8 VCC + 0.3 V
VCC= 2.7V to 3.6V 2.2 VCC + 0.3 V
VIL Input LOW Voltage VCC = 2.2V to 2.7V –0.3 0.6 V
VCC= 2.7V to 3.6V –0.3 0.8 V
IIX Input Leakage Current GND < VI< VCC –1 +1 µA
IOZ Output Leakage Current GND < VO <VCC, Output Disabled –1 +1 µA
ICC VCC Operating Supply Current f = fmax = 1/tRC VCC = VCC(max),
IOUT = 0 mA
CMOS levels
15 20 mA
f = 1 MHz 2 2.5
ISB1 Automatic CE Power down
Current — CMOS Inputs
CE > VCC−0.2V,
VIN >VCC–0.2V or VIN <0.2V
f = fmax (Address and Data Only),
f = 0 (OE, BHE, BLE and WE), VCC = 3.60V
17µA
ISB2 [8] Automatic CE Power down
Current — CMOS Inputs
CE > VCC – 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V,
f = 0, VCC = 3.60V
17µA
Notes:
5. VIL(min) = –2.0V for pulse durations less than 20 ns.
6. VIH(max) = VCC + 0.75V for pulse durations less than 20 ns.
7. Full device AC operation assumes a minimum of 100 µs ramp time from 0 to Vcc(min) and 200 µs wait time after Vcc stabilization.
8. Only chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be left floating.

CY62146EV30 MoBL®
Document #: 38-05567 Rev. *C Page 4 of 12
Capacitance (For All Packages) [9]
Parameter Description Test Conditions Max Unit
CIN Input Capacitance TA= 25°C, f = 1 MHz,
VCC = VCC(typ)
10 pF
COUT Output Capacitance 10 pF
Thermal Resistance [9]
Parameter Description Test Conditions
VFBGA
Package
TSOP II
Package Unit
ΘJA Thermal Resistance
(Junction to Ambient)
Still Air, soldered on a 3 × 4.5 inch,
two-layer printed circuit board
75 77 °C/W
ΘJC Thermal Resistance
(Junction to Case)
10 13 °C/W
AC Test Loads and Waveforms
Parameters 2.50V 3.0V Unit
R1 16667 1103 Ω
R2 15385 1554 Ω
RTH 8000 645 Ω
VTH 1.20 1.75 V
Data Retention Characteristics (Over the Operating Range)
Parameter Description Conditions Min Typ [2] Max Unit
VDR VCC for Data Retention 1.5 V
ICCDR [8] Data Retention Current VCC = 1.5V, CE > VCC – 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V
0.8 7 µA
tCDR [9] Chip Deselect to Data Retention Time 0 ns
tR [10] Operation Recovery Time tRC ns
Data Retention Waveform
VCC
VCC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
Rise Time = 1 V/ns Fall Time = 1 V/ns
OUTPUT V
ALL INPUT PULSES
RTH
R1
Equivalent to: THEVENIN EQUIVALENT
VCC(min)
VCC(min)
tCDR
VDR >1.5V
DATA RETENTION MODE
tR
VCC
CE
Notes:
9. Tested initially and after any design or process changes that may affect these parameters.
10. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 µs or stable at VCC(min) > 100 µs.

CY62146EV30 MoBL®
Document #: 38-05567 Rev. *C Page 5 of 12
Switching Characteristics (Over the Operating Range) [11, 12]
Parameter Description
45 ns
UnitMin Max
Read Cycle
tRC Read Cycle Time 45 ns
tAA Address to Data Valid 45 ns
tOHA Data Hold from Address Change 10 ns
tACE CE LOW to Data Valid 45 ns
tDOE OE LOW to Data Valid 22 ns
tLZOE OE LOW to Low-Z [13] 5ns
tHZOE OE HIGH to High-Z [13, 14] 18 ns
tLZCE CE LOW to Low-Z [13] 10 ns
tHZCE CE HIGH to High-Z [13, 14] 18 ns
tPU CE LOW to Power Up 0ns
tPD CE HIGH to Power Down 45 ns
tDBE BLE / BHE LOW to Data Valid 22 ns
tLZBE BLE / BHE LOW to Low-Z [13] 5ns
tHZBE BLE / BHE HIGH to High-Z [13, 14] 18 ns
Write Cycle [15]
tWC Write Cycle Time 45 ns
tSCE CE LOW to Write End 35 ns
tAW Address Setup to Write End 35 ns
tHA Address Hold from Write End 0 ns
tSA Address Setup to Write Start 0 ns
tPWE WE Pulse Width 35 ns
tBW BLE / BHE LOW to Write End 35 ns
tSD Data Setup to Write End 25 ns
tHD Data Hold from Write End 0 ns
tHZWE WE LOW to High-Z [13, 14] 18 ns
tLZWE WE HIGH to Low-Z [13] 10 ns
N
otes:
11. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1V/ns) or less, timing reference levels of VCC(typ)/2, input
pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” on page 4.
12. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. Please see application note AN13842 for further
clarification.
13. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any
given device.
14. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedence state.
15. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of
these signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.

CY62146EV30 MoBL®
Document #: 38-05567 Rev. *C Page 6 of 12
Switching Waveforms
Read Cycle 1 (Address Transition Controlled) [16, 17]
Read Cycle No. 2 (OE Controlled) [17, 18]
PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
ADDRESS
DATA OUT
50%
50%
DATA VALID
t
RC
t
ACE
t
LZBE
t
LZCE
t
PU
HIGHIMPEDANCE
I
CC
t
HZOE
t
HZCE
t
PD
t
HZBE
t
LZOE
t
DBE
t
DOE
IMPEDANCE
HIGH
I
SB
DATA OUT
OE
CE
V
CC
SUPPLY
CURRENT
BHE/BLE
ADDRESS
Notes:
16. The device is continuously selected. OE, CE = VIL, BHE and/or BLE = VIL.
17. WE is HIGH for read cycle.
18. Address valid before or similar to CE and BHE, BLE transition LOW.

CY62146EV30 MoBL®
Document #: 38-05567 Rev. *C Page 7 of 12
Write Cycle No. 1 (WE Controlled) [15, 19, 20]
Write Cycle No. 2 (CE Controlled) [15, 19, 20]
Switching Waveforms (continued)
tHD
tSD
tPWE tSA
tHA tAW
tWC
tHZOE
DATAIN
NOTE 21
tBW
tSCE
DATA IO
ADDRESS
CE
WE
OE
BHE/BLE
tHD
tSD
tPWE
tHA tAW
tSCE
tWC
tHZOE
DATAIN
tBW
tSA
CE
ADDRESS
WE
DATA IO
OE
BHE/BLE
NOTE 21
Notes:
19. Data IO is high impedance if OE = VIH.
20. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
21. During this period, the IOs are in output state and input signals must not be applied.

CY62146EV30 MoBL®
Document #: 38-05567 Rev. *C Page 8 of 12
Write Cycle No. 3 (WE Controlled, OE LOW) [20]
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) [20]
Switching Waveforms (continued)
DATAIN
tHD
tSD
tLZWE
tPWE tSA
tHA tAW
tSCE
tWC
tHZWE
tBW
NOTE 21
CE
ADDRESS
WE
DATA IO
BHE/BLE
t
HD
t
SD
t
SA
t
HA
t
AW
tWC
DATA
IN
t
BW
tSCE
t
PWE
tHZWE
tLZWE
NOTE 21
DATA IO
ADDRESS
CE
WE
BHE/BLE

CY62146EV30 MoBL®
Document #: 38-05567 Rev. *C Page 9 of 12
Truth Table
CE WE OE BHE BLE Inputs/Outputs Mode Power
H X X X X High-Z Deselect/Power down Standby (ISB)
L X X H H High-Z Output Disabled Active (ICC)
L H L L L Data Out (IO0–IO15) Read Active (ICC)
L H L H L Data Out (IO0–IO7);
IO8–IO15 in High-Z
Read Active (ICC)
L H L L H Data Out (IO8–IO15);
IO0–IO7 in High-Z
Read Active (ICC)
L H H L L High-Z Output Disabled Active (ICC)
L H H H L High-Z Output Disabled Active (ICC)
L H H L H High-Z Output Disabled Active (ICC)
L L X L L Data In (IO0–IO15) Write Active (ICC)
L L X H L Data In (IO0–IO7);
IO8–IO15 in High-Z
Write Active (ICC)
L L X L H Data In (IO8–IO15);
IO0–IO7 in High-Z
Write Active (ICC)
Ordering Information
Speed
(ns) Ordering Code
Package
Diagram Package Type
Operating
Range
45 CY62146EV30LL-45BVXI 51-85150 48-ball VFBGA (Pb-free) Industrial
CY62146EV30LL-45ZSXI 51-85087 44-pin TSOP II (Pb-free)
Please contact your local Cypress sales representative for availability of other parts

CY62146EV30 MoBL®
Document #: 38-05567 Rev. *C Page 10 of 12
Package Diagrams
Figure 1. 48-ball VFBGA (6 x 8 x 1 mm), 51-85150
A
1
A1 CORNER
0.75
0.75
Ø0.30±0.05(48X)
Ø0.25 M C A B
Ø0.05 M C
B
A
0.15(4X)
0.21±0.05
1.00 MAX
C
SEATING PLANE
0.55 MAX.
0.25 C
0.10 C
A1 CORNER
TOP VIEW BOTTOM VIEW
234
3.75
5.25
B
C
D
E
F
G
H
65
465231
D
H
F
G
E
C
B
A
6.00±0.10
8.00±0.10
A
8.00±0.10
6.00±0.10
B
1.875
2.625
0.26 MAX.
51-85150-*D

CY62146EV30 MoBL®
Document #: 38-05567 Rev. *C Page 11 of 12
© Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for
the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended
to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Figure 2. 44-pin TSOP II, 51-85087
MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All product and company names
mentioned in this document are the trademarks of their respective holders.
Package Diagrams (continued)
51-85087-*A

CY62146EV30 MoBL®
Document #: 38-05567 Rev. *C Page 12 of 12
Document History Page
Document Title:CY62146EV30 MoBL®, 4-Mbit (256K x 16) Static RAM
Document Number: 38-05567
REV. ECN NO. Issue Date
Orig. of
Change Description of Change
** 223225 See ECN AJU New Data Sheet
*A 247373 See ECN SYT Changed Advance Information to Preliminary
Moved Product Portfolio to Page 2
Changed VCC stabilization time in footnote #8 from 100 µs to 200 µs
Removed Footnote #14(tLZBE) from Previous revision
Changed ICCDR from 2.0 µA to 2.5 µA
Changed typo in Data Retention Characteristics(tR) from 100 µs to tRC ns
Changed tOHA from 6 ns to 10 ns for both 35 ns and 45 ns Speed Bin
Changed tHZOE, tHZBE, tHZWE from 12 to 15 ns for 35 ns Speed Bin and 15 to
18 ns for 45 ns Speed Bin
Changed tSCE and tBW from 25 to 30 ns for 35 ns Speed Bin and 40 to 35 ns
for 45 ns Speed Bin
Changed tHZCE from 12 to 18 ns for 35 ns Speed Bin and 15 to 22 ns for 45
ns Speed Bin
Changed tSD from 15 to 18 ns for 35 ns Speed Bin and 20 to 22 ns for
45 ns Speed Bin
Changed tDOE from 15 to 18 ns for 35 ns Speed Bin
Changed tDBE from 15 to 18 ns for 35 ns Speed Bin
Changed Ordering Information to include Pb-Free Packages
*B 414807 See ECN ZSD Changed from Preliminary information to Final
Changed the address of Cypress Semiconductor Corporation on Page #1
from “3901 North First Street” to “198 Champion Court”
Removed 35ns Speed Bin
Removed “L” version of CY62146EV30
Changed ball E3 from DNU to NC
Removed the redundant foot note on DNU.
Changed ICC (Max) value from 2 mA to 2.5 mA and ICC (Typ) value from
1.5 mA to 2 mA at f=1 MHz
Changed ICC (Typ) value from 12 mA to 15 mA at f = fmax
Changed ISB1 and ISB2 Typ values from 0.7 µA to 1 µA and Max values from
2.5 µA to 7 µA.
Changed the AC test load capacitance from 50pF to 30pF on Page# 4
Changed ICCDR from 2.5 µA to 7 µA.
Added ICCDR typical value.
Changed tLZOE from 3 ns to 5 ns
Changed tLZCE and tLZWE from 6 ns to 10 ns
Changed tLZBE from 6 ns to 5 ns
Changed tHZCE from 22 ns to 18 ns
Changed tPWE from 30 ns to 35 ns.
Changed tSD from 22 ns to 25 ns.
Updated the package diagram 48-ball VFBGA from *B to *D
Updated the ordering information table and replaced the Package Name
column with Package Diagram.
*C 925501 See ECN VKN Added footnote #8 related to ISB2 and ICCDR
Added footnote #12 related AC timing parameters