Cypress Semiconductor CY7C1007BN User manual

1M x 1 Static RAM
CY7C107BN
CY7C1007BN
Cypress Semiconductor Corporation • 198ChampionCourt • San Jose,CA 95134-1709 • 408-943-2600
Document #: 001-06426 Rev. ** Revised February 1, 2006
Features
•Highspeed
—t
AA = 15 ns
• CMOS for optimum speed/power
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
Functional Description
The CY7C107BN and CY7C1007BN are high-performance
CMOS static RAMs organized as 1,048,576 words by 1 bit.
Easy memory expansion is provided by an active LOW Chip
Enable (CE) and three-state drivers. These devices have an
automatic power-down feature that reduces power
consumption by more than 65% when deselected.
Writing to the devices is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the input pin
(DIN) is written into the memory location specified on the
address pins (A0through A19).
Reading from the devices is accomplished by taking Chip
Enable (CE) LOW while Write Enable (WE) remains HIGH.
Under these conditions, the contents of the memory location
specified by the address pins will appear on the data output
(DOUT) pin.
The output pin (DOUT) is placed in a high-impedance state
when the device is deselected (CE HIGH) or during a write
operation (CE and WE LOW).
The CY7C107BN is available in a standard 400-mil-wide SOJ;
the CY7C1007BN is available in a standard 300-mil-wide SOJ
LogicBlock Diagram Pin Configuration
Top View
SOJ
512 x 2048
ARRA
Y
A5
A6
A7
COLUMN
DECODER
ROW DECODER
SENSE AMPS
POWER
DOWN
WE
CE
INPUT BUFFER
DOUT
DIN
A4
A3
A2
A1
A0
1
2
3
4
5
6
7
8
9
10
11
14 15
16
20
19
18
17
21
24
23
22
12
13
25
28
27
26
GND
A11
A12
A13
A14
WE
VCC
A9
A10
CE
A0
DOUT DIN
A8
A7
A6
A2
A1
A4
NC
NC
A15
A16
A8
A12 A14 A16 A15 A10 A11 A13 A17 A18 A19
A17
A18
A19
A5
A3
A9
Selection Guide
7C107BN-15
7C1007BN-15
Maximum Access Time (ns) 15
Maximum Operating Current (mA) 80
Maximum CMOS Standby Current ISB2 (mA) 2
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CY7C107BN
CY7C1007BN
Document #: 001-06426 Rev. ** Page 2 of 7
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ..................................-65°C to +150°C
Ambient Temperature with
Power Applied..............................................-55°C to +125°C
Supply Voltage on VCC Relative to GND[1] .....-0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State[1] .................................... -0.5V to VCC + 0.5V
DC Input Voltage[1]..................................-0.5V to VCC + 0.5V
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.....................................................>200 mA
Operating Range
Range Ambient Temperature[2] VCC
Commercial 0°C to +70°C 5V ± 10%
Industrial -40°C to +85°C 5V ± 10%
Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions
7C107BN-15
7C1007BN-15
Min. Max. Unit
VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 V
VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA 0.4 V
VIH Input HIGH Voltage 2.2 VCC + 0.3 V
VIL Input LOW Voltage[1] -0.3 0.8 V
IIX Input Leakage Current GND < VI< VCC -1 +1 mA
IOZ Output Leakage Current GND < VI <VCC,
Output Disabled –5 +5 mA
IOS Output Short Circuit
Current[3] VCC = Max., VOUT = GND -300 mA
ICC VCC Operating Supply
Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC 80 mA
ISB1 Automatic CE Power-Down
Current— TTL Inputs Max. VCC, CE > VIH, VIN >VIH or VIN < VIL, f = f MAX 20 mA
ISB2 Automatic CE Power-Down
Current — CMOS Inputs Max. VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V or VIN < 0.3V, f = 0 2mA
Capacitance[4]
Parameter Description Test Conditions Max. Unit
CIN: Addresses Input Capacitance TA= 25 × C, f = 1 MHz,
VCC = 5.0V 7pF
CIN: Controls 10 pF
COUT Output Capacitance 10 pF
Notes:
1. VIL (min.) = –2.0V for pulse durations of less than 20 ns.
2. TAis the “Instant On” case temperature.
3. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
4. Tested initially and after any design or process changes that may affect these parameters.
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CY7C107BN
CY7C1007BN
Document #: 001-06426 Rev. ** Page 3 of 7
AC Test Loads and Waveforms
Switching Characteristics[5] Over the Operating Range
7C107BN-15
7C1007BN-15
Parameter Description Min. Max. Unit
READ CYCLE
tRC Read Cycle Time 15 ns
tAA Address to Data Valid 15 ns
tOHA Data Hold from Address Change 3 ns
tACE CE LOW to Data Valid 15 ns
tLZCE CE LOW to Low Z[6] 3ns
tHZCE CE HIGH to High Z[6, 7] 7ns
tPU CE LOW to Power-Up 0 ns
tPD CE HIGH to Power-Down 15 ns
WRITE CYCLE[8]
tWC Write Cycle Time 15 ns
tSCE CE LOW to Write End 12 ns
tAW Address Set-Up to Write End 12 ns
tHA Address Hold from Write End 0 ns
tSA Address Set-Up to Write Start 0 ns
tPWE WE Pulse Width 12 ns
tSD Data Set-Up to Write End 8 ns
tHD Data Hold from Write End 0 ns
tLZWE WE HIGH to Low Z[6] 3ns
tHZWE WE LOW to High Z[6, 7] 7ns
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE and tHZWE is less than tLZWE for any given device.
7. tHZCE and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any
of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
3.0V
5V
OUTPUT
R1 480Ω
R2
255Ω
30 pF
INCLUDING
JIG AND
SCOPE
GND 90%
10% 90%
10%
≤ 3ns ≤ 3ns
5V
OUTPUT
5pF
INCLUDING
JIG AND
SCOPE
(a) (b)
OUTPUT 1.73V
Equivalentto: THÉVENIN EQUIVALENT
ALL INPUT PULSES
R2
255Ω
R1 480Ω
167Ω
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CY7C1007BN
Document #: 001-06426 Rev. ** Page 4 of 7
Switching Waveforms
Read Cycle No. 1[10, 11]
Read Cycle No. 2[11, 12]
Write Cycle No. 1 (CE Controlled)[13]
Notes:
9. No input may exceed VCC + 0.5V.
10.Device is continuously selected, CE= VIL.
11. WE is HIGH for read cycle.
12.Address valid prior to or coincident with CE transition LOW.
13.If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
ADDRESS
DATA OUT
50%
50%
DATA VALID
tRC
tACE
tLZCE
tPU
HIGH IMPEDANCE
tHZCE
tPD
HIGH
ICC
ISB
IMPEDANCE
ADDRESS
CE
DATA OUT
VCC
SUPPLY
CURRENT
DATA VALID
tSCE
tAW
tSA
tPWE
tHA
tHD
tSD
tWC
HIGH IMPEDANCE
ADDRESS
CE
WE
DATA OUT
DATA IN
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CY7C1007BN
Document #: 001-06426 Rev. ** Page 5 of 7
Write Cycle No. 2 (WE Controlled)[13]
Truth Table
CE WE DOUT Mode Power
H X High Z Power-Down Standby (ISB)
L H Data Out Read Active (ICC)
L L High Z Write Active (ICC)
Ordering Information
Speed
(ns) Ordering Code Package Diagram Package Type Operating Range
15 CY7C107BN-15VC 51-85032 28-Lead (400-Mil) Molded SOJ Commercial
CY7C1007BN-15VC 51-85031 28-Lead (300-Mil) Molded SOJ
CY7C1007BN-15VXC 51-85031 28-Lead (300-Mil) Molded SOJ (Pb-free)
CY7C107BN-15VI 51-85032 28-Lead (400-Mil) Molded SOJ Industrial
Please contact local sales representative regarding availability of these parts
Switching Waveforms (continued)
tWC
DATA VALID
DATA UNDEFINED HIGH IMPEDANCE
tSCE
tAW
tSA tPWE tHA
tHD
tHZWE tLZWE
tSD
ADDRESS
CE
WE
DATA OUT
DATA IN
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CY7C1007BN
Document #: 001-06426 Rev. ** Page 6 of 7
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
All product or company names mentioned in this document may be the trademarks of their respective holders.
Package Diagrams
51-85032-*B
PIN 1 I.D
.435
.395 .445
.405
.128
.148
.360
.380
.026
.015
.032
.020
DIMENSIONS IN INCHES MIN.
MAX.
.025 MIN.
.007
.013
.050
TYP.
.720
.730
114
15 28
0.004
SEATING PLANE
51-85032.*B
28-Lead (400-Mil) Molded SOJ (51-85032)
MIN.
MAX.
PIN 1 ID
0.291
0.300
0.050
TYP.
0.007
0.013
0.330
0.350
0.120
0.140
0.025 MIN.
0.262
0.272
0.697
0.713
0.013
0.019 0.014
0.020
0.032
0.026
A
A
DETAIL
EXTERNAL LEAD DESIGN
OPTION 1 OPTION 2
114
15 28
0.004
SEATING PLANE
NOTE :
1. JEDEC STD REF MO088
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.006 in (0.152 mm) PER SIDE
3. DIMENSIONS IN INCHES
51-85031-*C
28-Lead (300-Mil) Molded SOJ (51-85031)
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CY7C107BN
CY7C1007BN
Document #: 001-06426 Rev. ** Page 7 of 7
Document History Page
Document Title: CY7C107BN/CY7C1007BN 1M x 1 Static RAM
Document Number: 001-06426
REV. ECN NO. Issue Date Orig. of Change Description of Change
** 423847 See ECN NXR New Data Sheet
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