Cypress CY8C28 series Product manual

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CY8C28xxx TRM
CY8C28xxx
PSoC®Programmable System-on-Chip™ TRM
(Technical Reference Manual)
Document No. 001-52594 Rev. *G
January 20, 2017
Cypress Semiconductor
198 Champion Court
San Jose, CA 95134-1709
Phone (USA): 800.858.1810
Phone (Intnl): 408.943.2600
http://www.cypress.com

2 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *G
Copyrights
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tive owners.

CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *G iii
Contents Overview
Section A: Overview 21
1. Pin Information....................................................................................................................29
Section B: PSoC®Core 35
2. CPU Core (M8C).................................................................................................................39
3. Supervisory ROM (SROM)...................................................................................................49
4. RAM Paging........................................................................................................................57
5. Interrupt Controller..............................................................................................................65
6. General Purpose I/O (GPIO)................................................................................................73
7. Analog Output Drivers.........................................................................................................79
8. Internal Main Oscillator (IMO)..............................................................................................81
9. Internal Low Speed Oscillator (ILO) .....................................................................................85
10. External Crystal Oscillator (ECO).........................................................................................87
11. Phase-Locked Loop (PLL) ...................................................................................................93
12. Sleep and Watchdog ...........................................................................................................97
Section C: Register Reference 109
13. Register Details................................................................................................................. 125
Section D: Digital System 311
14. Global Digital Interconnect (GDI).......................................................................................317
15. Array Digital Interconnect (ADI) .........................................................................................325
16. Row Digital Interconnect (RDI) .......................................................................................... 327
17. Digital Blocks ....................................................................................................................335
Section E: Analog System 383
18. Analog Interface................................................................................................................ 393
19. Analog Array.....................................................................................................................409
20. Analog Input Configuration ................................................................................................417
21. Analog Reference .............................................................................................................421
22. Continuous Time PSoC®Block..........................................................................................425
23. Switched Capacitor PSoC®Block ......................................................................................431
24. Two Column Limited Analog System.................................................................................. 441
Section F: System Resources 461
25. Digital Clocks.................................................................................................................... 465
26. Multiply Accumulate (MAC)................................................................................................477
27. Decimator ......................................................................................................................... 483
28. I2C....................................................................................................................................493
29. Internal Voltage Reference ................................................................................................ 511
30. System Resets..................................................................................................................513
31. Switch Mode Pump (SMP)................................................................................................. 519
32. POR and LVD....................................................................................................................523

Contents Overview
iv CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *G
33. I/O Analog Multiplexer....................................................................................................... 525
34. Real Time Clock (RTC) ..................................................................................................... 533
35. 10-Bit SAR ADC Controller ............................................................................................... 537
Section H: Glossary 545
Index 561

CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *G v
Contents
Section A: Overview 21
Document Organization ...................................................................................................................21
Top Level Architecture .....................................................................................................................22
PSoC Core ..............................................................................................................................22
Digital System .........................................................................................................................22
Analog System ........................................................................................................................22
System Resources ..................................................................................................................22
PSoC Device Characteristics ...........................................................................................................24
PSoC Device Distinctions ................................................................................................................25
Getting Started .................................................................................................................................26
Support ...................................................................................................................................26
Product Upgrades ...................................................................................................................26
Development Kits ....................................................................................................................26
Document History .............................................................................................................................26
Documentation Conventions ............................................................................................................27
Register Conventions ..............................................................................................................27
Numeric Naming .....................................................................................................................27
Units of Measure .....................................................................................................................27
Acronyms ................................................................................................................................28
1. Pin Information 29
1.1 Pinouts for the CY8C28xxx.....................................................................................................29
1.1.1 20-Pin Part Pinouts ...................................................................................................30
1.1.2 28-Pin Part Pinouts....................................................................................................31
1.1.3 44-Pin Part Pinouts ...................................................................................................32
1.1.4 48-Pin Part Pinouts ...................................................................................................33
1.1.5 56-Pin Part Pinout......................................................................................................34
Section B: PSoC®Core 35
Top Level Core Architecture ............................................................................................................35
Interpreting the Core Documentation ...............................................................................................35
Core Register Summary ...................................................................................................................36
2. CPU Core (M8C) 39
2.1 Overview.................................................................................................................................39
2.2 Internal Registers....................................................................................................................39
2.3 Address Spaces......................................................................................................................39
2.4 Instruction Set Summary ........................................................................................................40
2.5 Instruction Formats.................................................................................................................42
2.5.1 One-Byte Instructions ................................................................................................42
2.5.2 Two-Byte Instructions ................................................................................................42
2.5.3 Three-Byte Instructions..............................................................................................43

Contents
vi CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *G
2.6 Addressing Modes..................................................................................................................43
2.6.1 Source Immediate .....................................................................................................43
2.6.2 Source Direct.............................................................................................................44
2.6.3 Source Indexed .........................................................................................................44
2.6.4 Destination Direct......................................................................................................45
2.6.5 Destination Indexed...................................................................................................45
2.6.6 Destination Direct Source Immediate........................................................................45
2.6.7 Destination Indexed Source Immediate.....................................................................46
2.6.8 Destination Direct Source Direct ...............................................................................46
2.6.9 Source Indirect Post Increment.................................................................................47
2.6.10 Destination Indirect Post Increment...........................................................................47
2.7 Register Definitions ................................................................................................................48
2.7.1 CPU_F Register .......................................................................................................48
3. Supervisory ROM (SROM) 49
3.1 Architectural Description.........................................................................................................49
3.1.1 Additional SROM Feature..........................................................................................50
3.1.2 SROM Function Descriptions ....................................................................................50
3.1.2.1 SWBootReset Function...............................................................................50
3.1.2.2 HWBootReset Function...............................................................................51
3.1.2.3 ReadBlock Function....................................................................................51
3.1.2.4 WriteBlock Function ....................................................................................52
3.1.2.5 EraseBlock Function ...................................................................................52
3.1.2.6 ProtectBlock Function .................................................................................52
3.1.2.7 TableRead Function....................................................................................52
3.1.2.8 EraseAll Function........................................................................................53
3.1.2.9 Checksum Function.....................................................................................53
3.1.2.10 Calibrate0 Function.....................................................................................53
3.1.2.11 Calibrate1 Function.....................................................................................53
3.1.2.12 WriteAndVerify Function..............................................................................54
3.2 Register Definitions ................................................................................................................54
3.2.1 FLS_PR1 Register ....................................................................................................54
3.2.2 Related Registers......................................................................................................54
3.3 Clocking Strategy ...................................................................................................................55
3.3.1 DELAY Parameter .....................................................................................................55
3.3.2 CLOCK Parameter ....................................................................................................55
4. RAM Paging 57
4.1 Architectural Description.........................................................................................................57
4.1.1 Basic Paging..............................................................................................................57
4.1.2 Stack Operations .......................................................................................................58
4.1.3 Interrupts ...................................................................................................................58
4.1.4 MVI Instructions.........................................................................................................58
4.1.5 Current Page Pointer.................................................................................................58
4.1.6 Index Memory Page Pointer......................................................................................59
4.2 Register Definitions ................................................................................................................60
4.2.1 TMP_DRx Registers..................................................................................................60
4.2.2 CUR_PP Register......................................................................................................60
4.2.3 STK_PP Register ......................................................................................................61
4.2.4 IDX_PP Register .......................................................................................................61
4.2.5 MVR_PP Register .....................................................................................................61
4.2.6 MVW_PP Register ....................................................................................................62

CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *G vii
Contents
4.2.7 CPU_F Register.........................................................................................................62
4.2.8 MVR_PP Register......................................................................................................62
4.2.9 MVW_PP Register ....................................................................................................63
4.2.10 CPU_F Register.........................................................................................................63
5. Interrupt Controller 65
5.1 Architectural Description.........................................................................................................65
5.1.1 Posted versus Pending Interrupts..............................................................................66
5.2 Application Description ...........................................................................................................67
5.3 Register Definitions.................................................................................................................68
5.3.1 INT_CLRx Registers .................................................................................................68
5.3.1.1 INT_CLR0 Register.....................................................................................68
5.3.1.2 INT_CLR1 Register.....................................................................................69
5.3.1.3 INT_CLR2 Register.....................................................................................69
5.3.1.4 INT_CLR3 Register.....................................................................................69
5.3.2 INT_MSKx Registers ................................................................................................70
5.3.2.1 INT_MSK3 Register.....................................................................................70
5.3.2.2 INT_MSK2 Register.....................................................................................70
5.3.2.3 INT_MSK0 Register.....................................................................................70
5.3.2.4 INT_MSK1 Register.....................................................................................71
5.3.3 INT_VC Register........................................................................................................71
5.3.4 CPU_F Register ........................................................................................................72
6. General Purpose I/O (GPIO) 73
6.1 Architectural Description.........................................................................................................73
6.1.1 Digital I/O ..................................................................................................................73
6.1.2 Global I/O ..................................................................................................................73
6.1.3 Analog Input ..............................................................................................................74
6.1.4 GPIO Block Interrupts................................................................................................75
6.2 Register Definitions.................................................................................................................76
6.2.1 PRTxDR Registers ....................................................................................................76
6.2.2 PRTxIE Registers .....................................................................................................76
6.2.3 PRTxGS Registers ....................................................................................................76
6.2.4 PRTxDMx Registers ..................................................................................................77
6.2.5 PRTxICx Registers ....................................................................................................77
7. Analog Output Drivers 79
7.1 Architectural Description.........................................................................................................79
7.2 Register Definitions.................................................................................................................80
7.2.1 ABF_CR0 Register ....................................................................................................80
8. Internal Main Oscillator (IMO) 81
8.1 Architectural Description.........................................................................................................81
8.2 Application Description ...........................................................................................................81
8.2.1 Trimming the IMO......................................................................................................81
8.2.2 Engaging Slow IMO...................................................................................................81
8.3 Register Definitions.................................................................................................................82
8.3.1 CPU_SCR1 Register .................................................................................................82
8.3.2 OSC_CR2 Register ...................................................................................................82
8.3.3 IMO_TR Register.......................................................................................................83
8.3.4 IMO_TR1 Register.....................................................................................................83

viii CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *G
Contents
9. Internal Low Speed Oscillator (ILO) 85
9.1 Architectural Description.........................................................................................................85
9.2 Register Definitions ...............................................................................................................85
9.2.1 ILO_TR Register .......................................................................................................85
10. External Crystal Oscillator (ECO) 87
10.1 Architectural Description.........................................................................................................87
10.1.1 ECO External Components .......................................................................................88
10.2 Register Definitions ...............................................................................................................89
10.2.1 CPU_SCR1 Register ................................................................................................89
10.2.2 OSC_CR0 Register ..................................................................................................90
10.2.3 OSC_CR2 Register ..................................................................................................91
10.2.4 ECO_TR Register .....................................................................................................91
11. Phase-Locked Loop (PLL) 93
11.1 Architectural Description.........................................................................................................93
11.2 Register Definitions ................................................................................................................93
11.2.1 OSC_CR0 Register ...................................................................................................94
11.2.2 OSC_CR2 Register ...................................................................................................95
12. Sleep and Watchdog 97
12.1 Architectural Description.........................................................................................................97
12.1.1 32 kHz Clock Selection..............................................................................................97
12.1.2 Sleep Timer ...............................................................................................................97
12.2 Application Description...........................................................................................................98
12.3 Register Definitions ................................................................................................................99
12.3.1 INT_MSK0 Register...................................................................................................99
12.3.2 RES_WDT Register...................................................................................................99
12.3.3 CPU_SCR1 Register...............................................................................................100
12.3.4 CPU_SCR0 Register...............................................................................................101
12.3.5 OSC_CR0 Register .................................................................................................102
12.3.6 OSC_CR2 Register ................................................................................................103
12.3.7 ILO_TR Register......................................................................................................103
12.3.8 ECO_TR Register....................................................................................................104
12.4 Timing Diagrams ..................................................................................................................104
12.4.1 Sleep Sequence ......................................................................................................104
12.4.2 Wakeup Sequence ..................................................................................................105
12.4.3 Bandgap Refresh.....................................................................................................107
12.4.4 Watchdog Timer.......................................................................................................107
12.5 Power Consumption .............................................................................................................108
Section C: Register Reference 109
Register General Conventions .......................................................................................................109
Register Naming Conventions .......................................................................................................109
Register Mapping Tables ...............................................................................................................109
CY8C28x03 Register Maps ..................................................................................................110
Register Map Bank 0 Table: User Space .................................................................110
Register Map Bank 1 Table: Configuration Space ...................................................111
CY8C28x13 Register Maps ..................................................................................................112
Register Map Bank 0 Table: User Space .................................................................112
Register Map Bank 1 Table: Configuration Space ...................................................113

CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *G ix
CY8C28x23 Register Maps ...................................................................................................114
Register Map Bank 0 Table: User Space .................................................................114
Register Map Bank 1 Table: Configuration Space ...................................................115
CY8C28x33 Register Maps ...................................................................................................116
Register Map Bank 0 Table: User Space .................................................................116
Register Map Bank 1 Table: Configuration Space ...................................................117
CY8C28x43 Register Maps ...................................................................................................118
Register Map Bank 0 Table: User Space .................................................................118
Register Map Bank 1 Table: Configuration Space ...................................................119
CY8C28x45 Register Maps ...................................................................................................120
Register Map Bank 0 Table: User Space .................................................................120
Register Map Bank 1 Table: Configuration Space ...................................................121
CY8C28x52 Register Maps ...................................................................................................122
Register Map Bank 0 Table: User Space .................................................................122
Register Map Bank 1 Table: Configuration Space ...................................................123
13. Register Details 125
13.1 Maneuvering Around the Registers ......................................................................................125
Register Conventions ............................................................................................................126
13.1.1 Register Naming Conventions.................................................................................126
13.2 Bank 0 Registers ..................................................................................................................127
13.2.1 PRTxDR ..................................................................................................................127
13.2.2 PRTxIE ...................................................................................................................128
13.2.3 PRTxGS ..................................................................................................................129
13.2.4 PRTxDM2 ...............................................................................................................130
13.2.5 DxCxxDR0 ..............................................................................................................131
13.2.6 DxCxxDR1 ..............................................................................................................132
13.2.7 DxCxxDR2 ..............................................................................................................133
13.2.8 DxCxxCR0 (Timer Control:000) ..............................................................................134
13.2.9 DxCxxCR0 (Counter Control:001) ..........................................................................135
13.2.10 DxCxxCR0 (Dead Band Control:100) .....................................................................136
13.2.11 DxCxxCR0 (CRCPRS Control:010) ........................................................................137
13.2.12 DxCxxCR0 (PWMDBL Control:011) .......................................................................138
13.2.13 DCCxxCR0 (SPIM Control:0-110) ..........................................................................140
13.2.14 DCCxxCR0 (SPIS Control:1-110) ...........................................................................141
13.2.15 DxCxxCR0 (DSM Control:111) ...............................................................................142
13.2.16 DCCxxCR0 (UART Transmitter Control) ................................................................143
13.2.17 DCCxxCR0 (UART Receiver Control) ....................................................................144
13.2.18 AMX_IN ..................................................................................................................145
13.2.19 AMUX_CFG ............................................................................................................146
13.2.20 CLK_CR3 ................................................................................................................147
13.2.21 ARF_CR .................................................................................................................148
13.2.22 CMP_CR0 ...............................................................................................................149
13.2.23 ASY_CR .................................................................................................................150
13.2.24 CMP_CR1 ...............................................................................................................151
13.2.25 SADC_DH ...............................................................................................................153
13.2.26 SADC_DL ...............................................................................................................154
13.2.27 TMP_DRx ...............................................................................................................155
13.2.28 ACCxxCR3 .............................................................................................................156
13.2.29 ACCxxCR0 .............................................................................................................157
13.2.30 ACCxxCR1 .............................................................................................................159
13.2.31 ACCxxCR2 .............................................................................................................160
13.2.32 ASCxxCR0 ..............................................................................................................161

x CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *G
Contents
13.2.33 ASCxxCR1 .............................................................................................................162
13.2.34 ASCxxCR2 .............................................................................................................163
13.2.35 ASCxxCR3 .............................................................................................................164
13.2.36 ASDxxCR0 .............................................................................................................165
13.2.37 ASDxxCR1 .............................................................................................................166
13.2.38 ASDxxCR2 .............................................................................................................167
13.2.39 ASDxxCR3 .............................................................................................................168
13.2.40 DECx_DH ...............................................................................................................169
13.2.41 DECx_DL ................................................................................................................170
13.2.42 MULx_X ..................................................................................................................171
13.2.43 MULx_Y ..................................................................................................................172
13.2.44 MULx_DH ...............................................................................................................173
13.2.45 MULx_DL ................................................................................................................174
13.2.46 MACx_X/ACCx_DR1 ..............................................................................................175
13.2.47 MACx_Y/ACCx_DR0 ..............................................................................................176
13.2.48 MACx_CL0/ACCx_DR3 ..........................................................................................177
13.2.49 MACx_CL1/ACCx_DR2 ..........................................................................................178
13.2.50 RDIxRI ....................................................................................................................179
13.2.51 RDIxSYN ................................................................................................................180
13.2.52 RDIxIS ....................................................................................................................181
13.2.53 RDIxLT0 .................................................................................................................182
13.2.54 RDIxLT1 .................................................................................................................184
13.2.55 RDIxRO0 ................................................................................................................186
13.2.56 RDIxRO1 ................................................................................................................187
13.2.57 RDIxDSM ................................................................................................................188
13.2.58 CUR_PP .................................................................................................................189
13.2.59 STK_PP ..................................................................................................................190
13.2.60 IDX_PP ...................................................................................................................191
13.2.61 MVR_PP .................................................................................................................192
13.2.62 MVW_PP ................................................................................................................193
13.2.63 I2Cx_CFG ...............................................................................................................194
13.2.64 I2Cx_SCR ...............................................................................................................195
13.2.65 I2Cx_DR .................................................................................................................197
13.2.66 I2Cx_MSCR ............................................................................................................198
13.2.67 INT_CLR0 ...............................................................................................................199
13.2.68 INT_CLR1 ...............................................................................................................201
13.2.69 INT_CLR2 ...............................................................................................................203
13.2.70 INT_CLR3 ...............................................................................................................204
13.2.71 INT_MSK3 ..............................................................................................................206
13.2.72 INT_MSK2 ..............................................................................................................207
13.2.73 INT_MSK0 ..............................................................................................................208
13.2.74 INT_MSK1 ..............................................................................................................209
13.2.75 INT_VC ...................................................................................................................210
13.2.76 RES_WDT ..............................................................................................................211
13.2.77 DEC_CR0 ...............................................................................................................212
13.2.78 DEC_CR1 ...............................................................................................................213
13.2.79 CPU_F ....................................................................................................................214
13.2.80 IDACx_D .................................................................................................................215
13.2.81 CPU_SCR1 ............................................................................................................216
13.2.82 CPU_SCR0 ............................................................................................................217
13.3 Bank 1 Registers ..................................................................................................................218
13.3.1 PRTxDM0 ...............................................................................................................218
13.3.2 PRTxDM1 ...............................................................................................................219

CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *G xi
13.3.3 PRTxIC0 .................................................................................................................220
13.3.4 PRTxIC1 .................................................................................................................221
13.3.5 DxCxxFN ................................................................................................................222
13.3.6 DxCxxIN ..................................................................................................................224
13.3.7 DxCxxOU ................................................................................................................226
13.3.8 DxCxxCR1 (Timer Control:000) ..............................................................................228
13.3.9 DxCxxCR1 (Counter Control:001) ..........................................................................229
13.3.10 DxCxxCR1 (CRCPRS Control:010) ........................................................................230
13.3.11 DxCxxCR1 (PWMDBL Control:011) .......................................................................231
13.3.12 DxCxxCR1 (Dead Band Control:100) .....................................................................232
13.3.13 DxCxxCR1 (SPIM Control:0-110) ...........................................................................233
13.3.14 DxCxxCR1 (SPIS Control:0-110) ............................................................................234
13.3.15 DxCxxCR1 (DSM Control:111) ...............................................................................235
13.3.16 CLK_CR0 ................................................................................................................236
13.3.17 CLK_CR1 ................................................................................................................237
13.3.18 ABF_CR0 ................................................................................................................238
13.3.19 AMD_CR0 ...............................................................................................................239
13.3.20 CMP_GO_EN .........................................................................................................240
13.3.21 CMP_GO_EN1 .......................................................................................................241
13.3.22 AMD_CR1 ...............................................................................................................242
13.3.23 ALT_CR0 ................................................................................................................243
13.3.24 ALT_CR1 ................................................................................................................244
13.3.25 CLK_CR2 ................................................................................................................245
13.3.26 AMUX_CFG1 ..........................................................................................................246
13.3.27 SADC_TSCR0 ........................................................................................................247
13.3.28 SADC_TSCR1 ........................................................................................................248
13.3.29 ACE_AMD_CR0 .....................................................................................................249
13.3.30 ACE_AMX_IN .........................................................................................................250
13.3.31 ACE_CMP_CR0 .....................................................................................................251
13.3.32 ACE_CMP_CR1 .....................................................................................................252
13.3.33 ACE_CMP_GI_EN ..................................................................................................253
13.3.34 ACE_ALT_CR0 .......................................................................................................254
13.3.35 ACE_ABF_CR0 .....................................................................................................255
13.3.36 ACExxCR1 ..............................................................................................................256
13.3.37 ACExxCR2 ..............................................................................................................257
13.3.38 ASExxCR0 ..............................................................................................................258
13.3.39 SADC_TSCMPL .....................................................................................................259
13.3.40 SADC_TSCMPH .....................................................................................................260
13.3.41 ACE_AMD_CR1 .....................................................................................................261
13.3.42 ACE_PWM_CR ......................................................................................................262
13.3.43 ACE_ADCx_CR ......................................................................................................263
13.3.44 ACE_CLK_CR0 ......................................................................................................264
13.3.45 ACE_CLK_CR1 ......................................................................................................265
13.3.46 ACE_CLK_CR3 ......................................................................................................266
13.3.47 DECx_CR0 .............................................................................................................267
13.3.48 DEC_CR3 ...............................................................................................................268
13.3.49 DEC_CR4 ...............................................................................................................269
13.3.50 DEC_CR5 ...............................................................................................................270
13.3.51 GDI_O_IN_CR ........................................................................................................271
13.3.52 GDI_E_IN_CR ........................................................................................................272
13.3.53 GDI_O_OU_CR ......................................................................................................273
13.3.54 GDI_E_OU_CR ......................................................................................................274
13.3.55 RTC_H ....................................................................................................................275

xii CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *G
Contents
13.3.56 RTC_M ...................................................................................................................276
13.3.57 RTC_S ....................................................................................................................277
13.3.58 RTC_CR .................................................................................................................278
13.3.59 SADC_CR0 ............................................................................................................279
13.3.60 SADC_CR1 ............................................................................................................280
13.3.61 SADC_CR2 ............................................................................................................281
13.3.62 SADC_CR3 ............................................................................................................282
13.3.63 SADC_CR4 ............................................................................................................283
13.3.64 I2Cx_ADDR ............................................................................................................284
13.3.65 AMUX_CLK ............................................................................................................285
13.3.66 GDI_O_IN ...............................................................................................................286
13.3.67 GDI_E_IN ...............................................................................................................287
13.3.68 GDI_O_OU .............................................................................................................288
13.3.69 GDI_E_OU .............................................................................................................289
13.3.70 DECx_CR ...............................................................................................................290
13.3.71 MUX_CRx ...............................................................................................................291
13.3.72 IDAC_CR1 ..............................................................................................................292
13.3.73 OSC_GO_EN .........................................................................................................293
13.3.74 OSC_CR4 ...............................................................................................................294
13.3.75 OSC_CR3 ...............................................................................................................295
13.3.76 OSC_CR0 ...............................................................................................................296
13.3.77 OSC_CR1 ...............................................................................................................297
13.3.78 OSC_CR2 ...............................................................................................................298
13.3.79 VLT_CR ..................................................................................................................299
13.3.80 VLT_CMP ...............................................................................................................300
13.3.81 ADCx_TR ...............................................................................................................301
13.3.82 IDAC_MODE ..........................................................................................................302
13.3.83 IMO_TR ..................................................................................................................303
13.3.84 ILO_TR ...................................................................................................................304
13.3.85 BDG_TR .................................................................................................................305
13.3.86 ECO_TR .................................................................................................................306
13.3.87 IMO_TR1 ................................................................................................................307
13.3.88 FLS_PR1 ................................................................................................................308
13.3.89 IDAC_CR0 ..............................................................................................................309
Section D: Digital System 311
Top-Level Digital Architecture ........................................................................................................311
Interpreting the Digital Documentation ...........................................................................................311
Digital Register Summary ..............................................................................................................312
14. Global Digital Interconnect (GDI) 317
14.1 Architectural Description.......................................................................................................317
14.1.1 20-Pin Global Interconnect......................................................................................318
14.1.2 28-Pin Global Interconnect......................................................................................319
14.1.3 44-Pin Global Interconnect......................................................................................320
14.1.4 48-Pin Global Interconnect......................................................................................321
14.1.5 56-Pin Global Interconnect......................................................................................322
14.2 Register Definitions ..............................................................................................................322
14.2.1 GDI_x_IN Registers/GDI_x_IN_CR Registers.........................................................322
14.2.2 GDI_x_OU/GDI_x_OU_CR Registers.....................................................................323

CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *G xiii
15. Array Digital Interconnect (ADI) 325
15.1 Architectural Description.......................................................................................................325
16. Row Digital Interconnect (RDI) 327
16.1 Architectural Description.......................................................................................................327
16.2 Register Definitions...............................................................................................................329
16.2.1 RDIxRI Register.......................................................................................................329
16.2.2 RDIxSYN Register...................................................................................................330
16.2.3 RDIxIS Register.......................................................................................................331
16.2.4 RDIxLTx Registers...................................................................................................332
16.2.5 RDIxROx Registers .................................................................................................333
16.2.5.1 RDIxRO0 Register.....................................................................................333
16.2.5.2 RDIxRO1 Register.....................................................................................333
16.2.6 RDIxDSM Register ..................................................................................................334
16.3 Timing Diagram ....................................................................................................................334
17. Digital Blocks 335
17.1 Architectural Description.......................................................................................................335
17.1.1 Input Multiplexers.....................................................................................................336
17.1.2 Input Clock Resynchronization................................................................................336
17.1.2.1 Clock Resynchronization Summary...........................................................337
17.1.3 Output Demultiplexers.............................................................................................337
17.1.4 Block Chaining Signals............................................................................................337
17.1.5 Input Data Synchronization......................................................................................337
17.1.6 Timer Function ........................................................................................................337
17.1.6.1 Usability Exceptions ..................................................................................338
17.1.6.2 Block Interrupt ...........................................................................................338
17.1.7 Counter Function .....................................................................................................338
17.1.7.1 Counter Timing..........................................................................................338
17.1.7.2 Usability Exceptions ..................................................................................339
17.1.7.3 Block Interrupt ...........................................................................................339
17.1.8 Dead Band Function................................................................................................339
17.1.8.1 Usability Exceptions ..................................................................................340
17.1.8.2 Block Interrupt ...........................................................................................340
17.1.9 PWMDBL Function..................................................................................................340
17.1.9.1 Usability Exceptions ..................................................................................341
17.1.9.2 Block Interrupt ...........................................................................................341
17.1.10 CRCPRS Function ..................................................................................................341
17.1.10.1Usability Exceptions ..................................................................................342
17.1.10.2Block Interrupt ...........................................................................................342
17.1.11 SPI Protocol Function .............................................................................................343
17.1.11.1SPI Protocol Signal Definitions..................................................................343
17.1.12 SPI Master Function ................................................................................................344
17.1.12.1Usability Exceptions ..................................................................................344
17.1.12.2Block Interrupt ...........................................................................................344
17.1.13 SPI Slave Function..................................................................................................344
17.1.13.1Usability Exceptions ..................................................................................345
17.1.13.2Block Interrupt ...........................................................................................345
17.1.14 Asynchronous Transmitter and Receiver Functions................................................345
17.1.14.1Asynchronous Transmitter Function..........................................................345
17.1.14.2Usability Exceptions ..................................................................................346
17.1.14.3Block Interrupt ...........................................................................................346

xiv CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *G
Contents
17.1.14.4Asynchronous Receiver Function..............................................................346
17.1.14.5Usability Exceptions..................................................................................346
17.1.14.6Block Interrupt ...........................................................................................346
17.1.15 DSM function...........................................................................................................346
17.1.15.1Usability Exception....................................................................................347
17.1.15.2Block interrupt ...........................................................................................347
17.2 Register Definitions .............................................................................................................348
17.2.1 DxCxxDRx Registers ..............................................................................................349
17.2.1.1 Timer Register Definitions.........................................................................349
17.2.1.2 Counter Register Definitions .....................................................................350
17.2.1.3 Dead Band Register Definitions ................................................................350
17.2.1.4 PWMDBL Register Definitions ..................................................................351
17.2.1.5 CRCPRS Register Definitions...................................................................351
17.2.1.6 SPI Master Register Definitions ................................................................352
17.2.1.7 SPI Slave Register Definitions ..................................................................352
17.2.1.8 Transmitter Register Definitions................................................................352
17.2.1.9 Receiver Register Definitions....................................................................353
17.2.1.10DSM Register Definitions ..........................................................................353
17.2.2 DxCxxCR0 Register.................................................................................................353
17.2.3 DxCxxCR1 Register.................................................................................................357
17.2.4 INT_MSK1 Register ..............................................................................................359
17.2.5 DxCxxFN Registers ................................................................................................360
17.2.6 DxCxxIN Registers .................................................................................................361
17.2.7 DxCxxOU Registers ................................................................................................361
17.3 Timing Diagrams .................................................................................................................363
17.3.1 Timer Timing ...........................................................................................................363
17.3.2 Counter Timing .......................................................................................................366
17.3.3 Dead Band Timing ..................................................................................................367
17.3.3.1 Changing the PWM Duty Cycle.................................................................367
17.3.3.2 Kill Operation.............................................................................................368
17.3.4 PWMDBL Timing.....................................................................................................369
17.3.5 CRCPRS Timing .....................................................................................................370
17.3.6 SPI Mode Timing ....................................................................................................370
17.3.7 SPIM Timing ...........................................................................................................371
17.3.8 SPIS Timing ............................................................................................................374
17.3.9 Transmitter Timing ..................................................................................................377
17.3.10 Receiver Timing ......................................................................................................379
17.3.11 DSM Timing ............................................................................................................382
Section E: Analog System 383
Top Level Analog Architecture .......................................................................................................383
Interpreting the Analog Documentation .........................................................................................387
Application Description ..................................................................................................................387
Defining the Analog Blocks ...................................................................................................387
Analog Functionality ..............................................................................................................388
Analog Register Summary .............................................................................................................389
18. Analog Interface 393
18.1 Architectural Description.......................................................................................................393
18.1.1 Analog Data Bus Interface.......................................................................................394
18.1.2 Analog Comparator Bus Interface ...........................................................................394
18.1.3 Analog Column Clock Generation ...........................................................................394

CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *G xv
18.1.3.1 Column Clock Synchronization..................................................................395
18.1.4 Decimator and Incremental ADC Interface..............................................................395
18.1.4.1 Decimator..................................................................................................395
18.1.4.2 Incremental ADC ......................................................................................395
18.1.5 Analog Modulator Interface (Mod Bits) ....................................................................396
18.1.6 Analog Synchronization Interface (Stalling).............................................................396
18.2 Application Description .........................................................................................................396
18.2.1 SAR Hardware Acceleration....................................................................................396
18.2.1.1 Architectural Description............................................................................396
18.2.1.2 Application Description..............................................................................397
18.2.1.3 SAR Timing ...............................................................................................399
18.3 Register Definitions...............................................................................................................400
18.3.1 CLK_CR3 Register ..................................................................................................400
18.3.2 CMP_CR0 Register .................................................................................................401
18.3.3 ASY_CR Register....................................................................................................402
18.3.4 CMP_CR1 Register .................................................................................................403
18.3.5 DEC_CR0 Register..................................................................................................403
18.3.6 DEC_CR1 Register..................................................................................................404
18.3.7 CLK_CR0 Register ..................................................................................................404
18.3.8 CLK_CR1 Register ..................................................................................................405
18.3.9 AMD_CR0 Register .................................................................................................405
18.3.10 CMP_GO_EN Register............................................................................................406
18.3.11 CMP_GO_EN1 Register..........................................................................................406
18.3.12 AMD_CR1 Register .................................................................................................407
18.3.13 ALT_CR0 Register ..................................................................................................407
18.3.14 ALT_CR1 Register ..................................................................................................407
18.3.15 CLK_CR2 Register .................................................................................................408
19. Analog Array 409
19.1 Architectural Description.......................................................................................................409
19.1.1 NMux Connections ..................................................................................................410
19.1.2 PMux Connections...................................................................................................411
19.1.3 RBotMux Connections.............................................................................................412
19.1.4 AMux Connections...................................................................................................413
19.1.5 CMux Connections ..................................................................................................414
19.1.6 BMux SC/SD Connections.......................................................................................415
19.1.7 Analog Comparator Bus .........................................................................................416
19.2 Temperature Sensing Capability .........................................................................................416
20. Analog Input Configuration 417
20.1 Architectural Description.......................................................................................................417
20.1.1 Six Column Analog Input Configuration...................................................................418
20.2 Register Definitions .............................................................................................................419
20.2.1 AMX_IN Register ....................................................................................................419
20.2.2 ABF_CR0 Register .................................................................................................420
20.2.3 AMUX_CFG1 Register ...........................................................................................420
21. Analog Reference 421
21.1 Architectural Description.......................................................................................................421
21.2 Register Definitions ..............................................................................................................422
21.2.1 ARF_CR Register ...................................................................................................422

xvi CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *G
Contents
22. Continuous Time PSoC®Block 425
22.1 Architectural Description ......................................................................................................425
22.2 Register Definitions .............................................................................................................426
22.2.1 ACCxxCR3 Register ...............................................................................................427
22.2.2 ACCxxCR0 Register ...............................................................................................429
22.2.3 ACCxxCR1 Register ...............................................................................................429
22.2.4 ACCxxCR2 Register ...............................................................................................430
23. Switched Capacitor PSoC®Block 431
23.1 Architectural Description.......................................................................................................431
23.2 Application Description.........................................................................................................433
23.3 Register Definitions .............................................................................................................434
23.3.1 ASCxxCR0 Register ...............................................................................................435
23.3.2 ASCxxCR1 Register ...............................................................................................436
23.3.3 ASCxxCR2 Register ...............................................................................................436
23.3.4 ASCxxCR3 Register ...............................................................................................437
23.3.5 ASDxxCR0 Register ...............................................................................................438
23.3.6 ASDxxCR1 Register ...............................................................................................439
23.3.7 ASDxxCR2 Register ...............................................................................................439
23.3.8 ASDxxCR3 Register ...............................................................................................440
24. Two Column Limited Analog System 441
24.1 Architectural Description ......................................................................................................441
24.1.1 Analog Interface .....................................................................................................441
24.1.1.1 Analog Comparator Bus Interface ............................................................442
24.1.1.2 Analog Column Clock Generation ............................................................442
24.1.1.3 Single Slope ADC .....................................................................................442
24.1.1.4 PWM ADC Interface..................................................................................444
24.1.1.5 Analog Modulator Interface (Mod Bits) .....................................................444
24.1.1.6 Sample and Hold Feature .........................................................................444
24.1.2 Analog Array ...........................................................................................................445
24.1.2.1 NMux Connections ...................................................................................445
24.1.2.2 PMux Connections ....................................................................................446
24.1.2.3 Temperature Sensing Capability ..............................................................446
24.1.3 Analog Input Configuration .....................................................................................446
24.1.4 Analog Reference ...................................................................................................450
24.1.5 Continuous Time PSoC Block ................................................................................450
24.1.6 Switched Capacitor PSoC Block .............................................................................450
24.1.6.1 Application Description for the SC Block...................................................450
24.2 PSoC Device Distinctions.....................................................................................................450
24.3 Register Definitions .............................................................................................................452
24.3.1 Summary Table for Two Column Limited Analog System Registers .......................452
24.3.2 DEC_CR0 Register..................................................................................................453
24.3.3 DEC_CR1 Register..................................................................................................453
24.3.4 ADCx_TR Register .................................................................................................454
24.3.5 ACE_AMD_CR0 Register .......................................................................................454
24.3.6 ACE_AMX_IN Register ...........................................................................................454
24.3.7 ACE_CMP_CR0 Register .....................................................................................455
24.3.8 ACE_CMP_CR1 Register .....................................................................................455
24.3.9 ACE_CMP_GI_EN Register ...................................................................................455
24.3.10 ACE_ALT_CR0 Register ........................................................................................456

CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *G xvii
24.3.11 ACE_ABF_CR0 Register ........................................................................................456
24.3.12 ACExxCR1 Register ...............................................................................................456
24.3.13 ACExxCR2 Register ...............................................................................................457
24.3.14 ASExxCR0 Register ...............................................................................................457
24.3.15 ACE_AMD_CR1 Register .......................................................................................457
24.3.16 ACE_PWM_CR Register ........................................................................................458
24.3.17 ACE_ADCx_CR Register .......................................................................................458
24.3.18 ACE_CLK_CR0 Register ........................................................................................459
24.3.19 ACE_CLK_CR1 Register ........................................................................................459
24.3.20 ACE_CLK_CR3 Register ........................................................................................459
Section F: System Resources 461
Top-Level System Resources Architecture ....................................................................................461
Interpreting the System Resources Documentation .......................................................................461
System Resources Register Summary ..........................................................................................462
25. Digital Clocks 465
25.1 Architectural Description.......................................................................................................465
25.1.1 Internal Main Oscillator ...........................................................................................465
25.1.2 Internal Low Speed Oscillator .................................................................................465
25.1.3 32.768 kHz Crystal Oscillator...................................................................................467
25.1.4 External Clock .......................................................................................................467
25.1.4.1 Clock Doubler............................................................................................467
25.1.4.2 Switch Operation.......................................................................................467
25.2 Register Definitions ..............................................................................................................469
25.2.1 INT_CLR0 Register ................................................................................................469
25.2.2 INT_MSK0 Register ................................................................................................469
25.2.3 OSC_GO_EN Register ...........................................................................................470
25.2.4 OSC_CR4 Register ................................................................................................471
25.2.5 OSC_CR3 Register ................................................................................................472
25.2.6 OSC_CR0 Register ..............................................................................................473
25.2.7 OSC_CR1 Register ................................................................................................474
25.2.8 OSC_CR2 Register ..............................................................................................475
26. Multiply Accumulate (MAC) 477
26.1 Architectural Description ......................................................................................................477
26.2 Application Description .........................................................................................................478
26.2.1 Multiplication with No Accumulation .......................................................................478
26.2.2 Accumulation After Multiplication.............................................................................478
26.3 Register Definitions ..............................................................................................................478
26.3.1 MULx_X Register ....................................................................................................479
26.3.2 MULx_Y Register ....................................................................................................479
26.3.3 MULx_DH Register .................................................................................................479
26.3.4 MULx_DL Register .................................................................................................480
26.3.5 MACx_X/ACCx_DR1 Register ................................................................................480
26.3.6 MACx_Y/ACCx_DR0 Register ................................................................................480
26.3.7 MACx_CL0/ACCx_DR3 Register ...........................................................................481
26.3.8 MACx_CL1/ACCx_DR2 Register ...........................................................................481
27. Decimator 483
27.1 Architectural Description.......................................................................................................483
27.1.1 Type 2 Decimator Block ..........................................................................................483

xviii CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *G
Contents
27.1.1.1 Dedicated Data/Clock Input Selections for Single Decimator Row ...........485
27.1.1.2 Single External Decimation Clock Supports Four Decimators ..................486
27.1.1.3 Single Incremental Gating Clock Supports Six Analog Compare Outputs486
27.1.1.4 ACC/ACE Interrupts Replacement............................................................487
27.2 Register Definitions .............................................................................................................488
27.2.1 DECx_DH Register .................................................................................................488
27.2.2 DECx_DL Register .................................................................................................488
27.2.3 DEC_CR0 Register..................................................................................................489
27.2.4 DEC_CR1 Register..................................................................................................489
27.2.5 DECx_CR0 Register ...............................................................................................490
27.2.6 DEC_CR3 Register .................................................................................................490
27.2.7 DEC_CR4 Register .................................................................................................491
27.2.8 DEC_CR5 Register .................................................................................................491
27.2.9 DECx_CR Registers ...............................................................................................492
28. I2C493
28.1 Architectural Description.......................................................................................................493
28.1.1 Dual I2C HW............................................................................................................493
28.1.2 Basic I2C Data Transfer...........................................................................................494
28.2 Application Description.........................................................................................................494
28.2.1 Slave Operation ......................................................................................................494
28.2.2 Master Operation ....................................................................................................496
28.3 Register Definitions .............................................................................................................497
28.3.1 I2Cx_ADDR Register ..............................................................................................497
28.3.2 I2Cx_CFG Register ................................................................................................498
28.3.3 I2Cx_SCR Register ................................................................................................500
28.3.4 I2Cx_DR Register ...................................................................................................502
28.3.5 I2Cx_MSCR Register .............................................................................................502
28.4 PSoC Device Distinctions.....................................................................................................504
28.5 Timing Diagrams ..................................................................................................................504
28.5.1 Clock Generation.....................................................................................................504
28.5.2 Basic Input/Output Timing .......................................................................................505
28.5.3 Status Timing...........................................................................................................505
28.5.4 Master Start Timing..................................................................................................506
28.5.5 Master Restart Timing .............................................................................................508
28.5.6 Master Stop Timing .................................................................................................508
28.5.7 Master/Slave Stall Timing .......................................................................................509
28.5.8 Master Lost Arbitration Timing ................................................................................509
28.5.9 Master Clock Synchronization.................................................................................510
29. Internal Voltage Reference 511
29.1 Architectural Description.......................................................................................................511
29.2 Register Definitions .............................................................................................................511
29.2.1 BDG_TR Register ...................................................................................................511
30. System Resets 513
30.1 Architectural Description.......................................................................................................513
30.2 Pin Behavior During Reset ...................................................................................................513
30.2.1 GPIO Behavior on Power Up...................................................................................513
30.2.2 GPIO Behavior on External Reset...........................................................................513
30.3 Register Definitions .............................................................................................................514
30.3.1 CPU_SCR1 Register ..............................................................................................514

CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *G xix
30.3.2 CPU_SCR0 Register ..............................................................................................515
30.4 Timing Diagrams ..................................................................................................................516
30.4.1 Power On Reset .....................................................................................................516
30.4.2 External Reset ........................................................................................................516
30.4.3 Watchdog Timer Reset ...........................................................................................516
30.4.4 Reset Details ...........................................................................................................518
30.5 Power Consumption ............................................................................................................518
31. Switch Mode Pump (SMP) 519
31.1 Architectural Description.......................................................................................................519
31.2 Application Description .........................................................................................................520
31.2.1 Component Value Selection.....................................................................................520
31.3 Register Definitions ..............................................................................................................521
31.3.1 VLT_CR Register ....................................................................................................521
32. POR and LVD 523
32.1 Architectural Description.......................................................................................................523
32.2 Register Definitions ..............................................................................................................523
32.2.1 VLT_CR Register ....................................................................................................523
32.2.2 VLT_CMP Register .................................................................................................524
33. I/O Analog Multiplexer 525
33.1 Architectural Description ......................................................................................................525
33.1.1 IOMUX and GPIO....................................................................................................525
33.1.2 Dual Channel 8-Bit IDAC.........................................................................................525
33.2 PSoC Device Distinctions.....................................................................................................526
33.3 Application Description .........................................................................................................526
33.3.1 Capacitive Sensing .................................................................................................526
33.3.2 Chip-Wide Analog Input ..........................................................................................528
33.3.3 Crosspoint Switch ...................................................................................................528
33.3.4 Charging Current .....................................................................................................528
33.4 Register Definitions ..............................................................................................................528
33.4.1 AMUX_CFG Register .............................................................................................528
33.4.2 IDAC1_D Register ..................................................................................................529
33.4.3 IDAC0_D Register ...................................................................................................529
33.4.4 AMUX_CFG1 Register ...........................................................................................529
33.4.5 AMUX_CLK Register ..............................................................................................530
33.4.6 MUX_CRx Registers ...............................................................................................530
33.4.7 IDAC_MODE ...........................................................................................................531
33.4.8 IDAC_CR0 Register.................................................................................................531
33.4.9 IDAC_CR1 Register ................................................................................................531
34. Real Time Clock (RTC) 533
34.1 Architectural Description.......................................................................................................533
34.1.1 BCD Code Counter..................................................................................................533
34.1.2 Writing RTC Data.....................................................................................................533
34.1.3 Reading RTC Data...................................................................................................533
34.1.4 General Timer..........................................................................................................534
34.2 Register Definitions ..............................................................................................................534
34.2.1 RTC_H.....................................................................................................................534
34.2.2 RTC_M.....................................................................................................................534
34.2.3 RTC_S.....................................................................................................................534