Cypress enCoRe V CY7C643 Series Product manual

enCoRe™ V CY7C643xx,
enCoRe™ V LV CY7C604xx
Technical Reference Manual (TRM)
Document No. 001-32519 Rev *H
November 19, 2018
Cypress Semiconductor
198 Champion Court
San Jose, CA 95134-1709
www.cypress.com

enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document Number: 001-32519 Rev. *H 2
Copyrights
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enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H 3
Contents
Section A: Overview 9
1. Pin Information 15
1.1 Pinouts....................................................................................................................................15
1.1.1 CY7C60413 enCoRe V LV 16-Pin Part Pinout ....................................................15
1.1.2
CY7C60445 enCoRe V LV 32-Pin Part Pinout16
1.1.3 CY7C64345, CY7C64343, enCoRe V 32-Pin Part Pinout .....................................17
1.1.4 CY8C20646A/AS/LCY8C20666A/AS/L
CY7C64355, CY7C64356 enCoRe V 48-Pin Part Pinout18
1.1.5 CY7C60455, CY7C60456 enCoRe V LV 48-Pin Part Pinout.................................19
1.1.6 CY8C20066A, CY8CTMG200-00LTXI, CY8CTMG200A-00LTXI PSoC,
CY7C64300 enCoRe V and CY7C60400 enCoRe V LV OCD 48-Pin Part Pinout20
1.1.7 32-Pin QFN (with USB) .........................................................................................21
1.1.8 48-Pin SSOP .........................................................................................................22
Section B: enCoRe V Core 23
2. CPU Core (M8C) 26
2.1 Overview.................................................................................................................................26
2.2 Internal Registers....................................................................................................................26
2.3 Address Spaces......................................................................................................................26
2.4 Instruction Set Summary ........................................................................................................27
2.5 Instruction Formats .................................................................................................................29
2.5.1 One-Byte Instructions ............................................................................................29
2.5.2 Two-Byte Instructions.............................................................................................29
2.5.3 Three-Byte Instructions..........................................................................................30
2.6 Register Definitions.................................................................................................................31
2.6.1 CPU_F Register ....................................................................................................31
2.6.2 Related Registers ..................................................................................................31
3. Supervisory ROM (SROM) 32
3.1 Architectural Description.........................................................................................................32
3.1.1 Additional SROM Feature ......................................................................................33
3.1.2 SROM Function Descriptions.................................................................................33
3.2 Register Definitions.................................................................................................................37
4. RAM Paging 38
4.1 Architectural Description.........................................................................................................38
4.1.1 Basic Paging ..........................................................................................................38
4.1.2 Stack Operations....................................................................................................38
4.1.3 Interrupts................................................................................................................39
4.1.4 MVI Instructions .....................................................................................................39
4.1.5 Current Page Pointer .............................................................................................39

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Contents
4.1.6 Index Memory Page Pointer ..................................................................................40
4.2 Register Definitions.................................................................................................................41
4.2.1 TMP_DRx Registers .............................................................................................41
4.2.2 CUR_PP Register .................................................................................................41
4.2.3 STK_PP Register ..................................................................................................42
4.2.4 IDX_PP Register ...................................................................................................42
4.2.5 MVR_PP Register .................................................................................................42
4.2.6 MVW_PP Register ................................................................................................43
4.2.7 Related Registers ..................................................................................................43
5. Interrupt Controller 44
5.1 Architectural Description.........................................................................................................44
5.1.1 Posted versus Pending Interrupts..........................................................................45
5.2 Application Overview ..............................................................................................................45
5.3 Register Definitions.................................................................................................................46
5.3.1 INT_CLR0 Register ...............................................................................................46
5.3.2 INT_CLR1 Register................................................................................................47
5.3.3 INT_CLR2 Register ...............................................................................................48
5.3.4 INT_MSK0 Register ...............................................................................................49
5.3.5 INT_MSK1 Register ...............................................................................................49
5.3.6 INT_MSK2 Register ...............................................................................................50
5.3.7 INT_SW_EN Register ...........................................................................................50
5.3.8 INT_VC Register ...................................................................................................51
5.3.9 Related Registers ..................................................................................................51
6. General-Purpose I/O (GPIO) 52
6.1 Architectural Description.........................................................................................................52
6.1.1 General Description ...............................................................................................53
6.1.2 Digital I/O ...............................................................................................................53
6.1.3 Analog and Digital Inputs .......................................................................................53
6.1.4 Port 1 Distinctions ..................................................................................................53
6.1.5 Port 0 Distinctions ..................................................................................................53
6.1.6 GPIO Block Interrupts ............................................................................................54
6.1.7 Data Bypass...........................................................................................................55
6.2 Register Definitions.................................................................................................................56
6.2.1 PRTxDR Registers ................................................................................................56
6.2.2 PRTxIE Registers .................................................................................................56
6.2.3 PRTxDMx Registers .............................................................................................57
6.2.4 IO_CFG1 Register .................................................................................................58
6.2.5 IO_CFG2 Register .................................................................................................58
7. Analog-to-Digital Converter (ADC) 59
7.1 Architectural Description.........................................................................................................59
7.2 Brief Overview of ADC Components and Registers ...............................................................60
7.2.1 Interface Command/Status Block...........................................................................60
7.2.2 ADC .......................................................................................................................60
7.3 ADC Register Definitions - Application Interface ....................................................................64
7.3.1 ADC Data Register ................................................................................................64
7.3.2 ADC Status Register ..............................................................................................64
7.4 Application Overview ..............................................................................................................65
7.4.1 Use of Application Interface ...................................................................................65
7.4.2 Status Codes..........................................................................................................65
7.4.3 ADC Usage Guidelines ..........................................................................................65

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Contents
7.4.4 Typical ADC Operation Procedure.........................................................................66
8. Internal Main Oscillator (IMO) 67
8.1 Architectural Description.........................................................................................................67
8.2 Application Overview ..............................................................................................................67
8.2.1 Trimming the IMO ..................................................................................................67
8.2.2 Engaging Slow IMO ...............................................................................................67
8.3 Register Definitions.................................................................................................................68
8.3.1 IMO_TR Register ...................................................................................................68
8.3.2 IMO_TR1 Register ................................................................................................68
8.3.3 CPU_SCR1 Register .............................................................................................69
8.3.4 OSC_CR2 Register................................................................................................69
8.3.5 Related Registers ..................................................................................................69
8.4 Timing Diagrams.....................................................................................................................69
8.5 Clocking Strategy....................................................................................................................70
8.6 Usage Guidelines ...................................................................................................................70
8.6.1 Power Down Guidelines.........................................................................................70
8.7 Block Size/Area ......................................................................................................................70
8.8 Gate Count .............................................................................................................................70
8.9 Block Pin List ..........................................................................................................................70
8.10 Block Level Interfaces.............................................................................................................70
8.11 Initialization .............................................................................................................................70
8.12 Wounding................................................................................................................................70
8.13 On-Chip Debugger Modes......................................................................................................70
8.14 Test Modes .............................................................................................................................70
8.15 Power Modes..........................................................................................................................70
8.16 Design Flow ............................................................................................................................70
8.17 Operating Condition Requirements .......................................................................................71
8.18 DC Specifications ..................................................................................................................71
8.19 AC Specifications....................................................................................................................71
9. Internal Low-speed Oscillator (ILO) 72
9.1 Architectural Description.........................................................................................................72
9.2 Register Definitions.................................................................................................................73
9.2.1 ILO_TR Register ...................................................................................................73
10. External Crystal Oscillator (ECO) 74
10.1 Architectural Description.........................................................................................................74
10.2 Application Overview ..............................................................................................................75
10.3 Register Definitions.................................................................................................................76
10.3.1 ECO_ENBUS Register .........................................................................................76
10.3.2 ECO_TRIM Register .............................................................................................76
10.3.3 ECO_CFG Register ..............................................................................................76
10.3.4 Related Registers ..................................................................................................77
10.4 Usage Modes and Guidelines.................................................................................................77
11. Sleep and Watchdog 78
11.1 Architectural Description.........................................................................................................78
11.1.1 Sleep Control Implementation Logic ......................................................................79
11.1.2 Sleep Timer............................................................................................................81
11.2 Application Overview ..............................................................................................................81
11.3 Register Definitions.................................................................................................................82
11.3.1 RES_WDT Register ..............................................................................................82
11.3.2 SLP_CFG Register ...............................................................................................82

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Contents
11.3.3 SLP_CFG2 Register .............................................................................................83
11.3.4 SLP_CFG3 Register .............................................................................................83
11.3.5 Related Registers ..................................................................................................83
11.4 Timing Diagrams.....................................................................................................................84
11.4.1 Sleep Sequence.....................................................................................................84
11.4.2 Wakeup Sequence.................................................................................................85
11.4.3 Bandgap Refresh ...................................................................................................85
11.4.4 Watchdog Timer.....................................................................................................86
11.5 ................................................................................................................................................86
12. Regulated I/O 87
12.1 Architectural Description.........................................................................................................87
12.1.1 Bias Generator.......................................................................................................88
12.1.2 Charge Pump.........................................................................................................88
12.1.3 Comparator ............................................................................................................88
12.1.4 Replica Structure....................................................................................................88
12.1.5 Pass Transistors ....................................................................................................88
12.2 Application Overview ..............................................................................................................88
12.3 Register Definitions.................................................................................................................89
12.3.1 IO_CFG1 Register .................................................................................................89
12.3.2 IO_CFG2 Register .................................................................................................89
13. I/O Analog Multiplexer 90
13.1 Architectural Description.........................................................................................................90
13.2 Register Definitions.................................................................................................................91
13.2.1 MUX_CRx Registers..............................................................................................91
Section C: System Resources 92
14. Digital Clocks 96
14.1 Architectural Description.........................................................................................................96
14.1.1 Internal Main Oscillator ..........................................................................................96
14.1.2 Internal Low-speed Oscillator ................................................................................96
14.1.3 External Clock........................................................................................................97
14.2 Register Definitions.................................................................................................................99
14.2.1 USB_MISC_CR Register ......................................................................................99
14.2.2 OUT_P1 Register ..................................................................................................99
14.2.3 OSC_CR0 Register .............................................................................................101
14.2.4 OSC_CR2 Register .............................................................................................102
15. I2C Slave 103
15.1 Architectural Description.......................................................................................................103
15.1.1 Basic I2C Data Transfer .......................................................................................104
15.2 Application Overview ............................................................................................................105
15.2.1 Slave Operation ...................................................................................................105
15.3 Register Definitions...............................................................................................................106
15.3.1 I2C_XCFG Register .............................................................................................106
15.3.2 I2C_ADDR Register.............................................................................................106
15.3.3 I2C_CFG Register ..............................................................................................107
15.3.4 I2C_SCR Register ..............................................................................................109
15.3.5 I2C_DR Register ................................................................................................. 110
15.4 Timing Diagrams...................................................................................................................111
15.4.1 Clock Generation ................................................................................................. 111
15.4.2 Basic I/O Timing................................................................................................... 111

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Contents
15.4.3 Status Timing .......................................................................................................112
15.4.4 Slave Stall Timing.................................................................................................113
16. System Resets 114
16.1 Architectural Description.......................................................................................................114
16.2 Pin Behavior During Reset ...................................................................................................114
16.2.1 GPIO Behavior on Power Up ...............................................................................114
16.2.2 Powerup External Reset Behavior .......................................................................115
16.2.3 GPIO Behavior on External Reset .......................................................................115
16.3 Register Definitions...............................................................................................................116
16.3.1 CPU_SCR1 Register ...........................................................................................116
16.3.2 CPU_SCR0 Register ...........................................................................................117
16.4 Timing Diagrams...................................................................................................................118
16.4.1 Power-On-Reset ..................................................................................................118
16.4.2 External Reset .....................................................................................................118
16.4.3 Watchdog Timer Reset ........................................................................................118
16.4.4 Reset Details........................................................................................................120
16.5 Power Modes........................................................................................................................120
17. POR and LVD 121
17.1 Architectural Description.......................................................................................................121
17.2 Register Definitions...............................................................................................................122
17.2.1 VLT_CR Register .................................................................................................122
17.2.2 VLT_CMP Register ..............................................................................................122
18. SPI 123
18.1 Architectural Description.......................................................................................................123
18.1.1 SPI Protocol Function ..........................................................................................123
18.1.2 SPI Master Function ............................................................................................124
18.1.3 SPI Slave Function ..............................................................................................124
18.1.4 Input Synchronization ..........................................................................................125
18.2 Register Definitions...............................................................................................................125
18.2.1 SPI_TXR Register................................................................................................125
18.2.2 SPI_RXR Register ...............................................................................................126
18.2.3 SPI_CR Register..................................................................................................127
18.2.4 SPI_CFG Register ...............................................................................................128
18.2.5 Related Registers ................................................................................................128
18.3 Timing Diagrams...................................................................................................................129
18.3.1 SPI Mode Timing .................................................................................................129
18.3.2 SPIM Timing ........................................................................................................130
18.3.3 SPIS Timing .........................................................................................................134
19. Programmable Timer 137
19.1 Architectural Description.......................................................................................................137
19.1.1 Operation .............................................................................................................137
19.2 Register Definitions...............................................................................................................139
19.2.1 PT0_CFG Register ..............................................................................................139
19.2.2 PT1_CFG Register ..............................................................................................139
19.2.3 PT2_CFG Register ..............................................................................................140
19.2.4 PTx_DATA0 Register ...........................................................................................140
19.2.5 PTx_DATA1 Register ...........................................................................................140
20. Full-Speed USB 141
20.1 Architectural Description.......................................................................................................141

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Contents
20.2 Application Description .........................................................................................................141
20.2.1 USB SIE...............................................................................................................141
20.2.2 USB SRAM ..........................................................................................................142
20.2.3 Oscillator Lock .....................................................................................................144
20.2.4 Transceiver ..........................................................................................................144
20.2.5 USB Suspend ......................................................................................................145
20.2.6 Regulator .............................................................................................................145
20.3 Register Definitions...............................................................................................................147
20.3.1 USB_SOF0 Register............................................................................................147
20.3.2 USB_CR0 Register ..............................................................................................147
20.3.3 USBIO_CR0 Register ..........................................................................................148
20.3.4 USBIO_CR1 Register ..........................................................................................148
20.3.5 EP0_CR Register.................................................................................................149
20.3.6 EP0_CNT Register ..............................................................................................150
20.3.7 EP0_DRx Register...............................................................................................150
20.3.8 EPx_CNT1 Register.............................................................................................151
20.3.9 EPx_CNT0 Register.............................................................................................152
20.3.10 EPx_CR0 Register...............................................................................................153
20.3.11 PMAx_WA Register .............................................................................................154
20.3.12 PMAx_DR Register..............................................................................................155
20.3.13 PMAx_RA Register ..............................................................................................156
20.3.14 USB_CR1 Register ..............................................................................................157
20.3.15 USB_MISC_CR Register ....................................................................................157
20.3.16 IMO_TR1 Register ...............................................................................................158
Section D: Registers 159
21. Register Reference 163
21.1 Maneuvering Around the Registers ......................................................................................163
21.2 Register Conventions ...........................................................................................................163
21.3 Bank 0 Registers ..................................................................................................................164
21.4 Bank 1 Registers ..................................................................................................................212
Section E: Glossary 239

enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H 9
Section A: Overview
The enCoRe™ V family consists of many On-Chip Controller devices. The CY8C20x46A/46AS/96A/46L/96LCY7C643xx and
CY7C604xx enCoRe V devices have fixed analog and digital resources in addition to a fast CPU, flash program memory, and
SRAM data memory to support various algorithms.
For the most up-to-date ordering, pinout, packaging, or electrical specification information, refer to the enCoRe V device’s
datasheet. For the most current technical reference manual information and newest product documentation, go to the
Cypress web site at http://www.cypress.com >> Documentation.
This section contains:
■Pin Information on page 15.
Document Organization
This manual is organized into sections and chapters, according to enCoRe V functionality. Each section contains a top-level
architectural diagram and a register summary (if applicable). Most chapters within the sections have an introduction, an archi-
tectural/application description, register definitions, and timing diagrams. The sections are as follows:
■Overview – Presents the top-level architecture, helpful information to get started, and document history and
conventions. The enCoRe V device pinouts are detailed in Pin Information, on page 15.
■enCoRe V Core – Describes the heart of the enCoRe V device in various chapters, beginning with an architectural over-
view and a summary list of registers pertaining to the enCoRe V core.
■System Resources – Presents additional enCoRe V system resources, beginning with an overview and a summary list of
registers pertaining to system resources.
■Registers – Lists all enCoRe V device registers in register mapping tables, and presents bit-level detail of each register in
its own Register Reference chapter. Where applicable, detailed register descriptions are also located in each chapter.
■Glossary – Defines the specialized terminology used in this manual. Glossary terms are presented in bold, italic font
throughout this manual.
■Index – Lists the location of key topics and elements that constitute and empower the enCoRe V devices.

enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H 10
Top-Level Architecture
The enCoRe V block diagram on the next page illustrates the top-level architecture of the
CY8C20X46A/46AS/96A/46L/96LCY7C643xx and CY7C604xx devices. Each major grouping in the diagram is covered in this
manual in its own section: enCoRe V Core and System Resources. Banding these two main areas together is the communica-
tion network of the system bus.
enCoRe V Core
The enCoRe V Core is a powerful engine that supports a rich instruction set. It includes the SRAM for data storage, an inter-
rupt controller for easy program execution to new addresses, sleep and watchdog timers, a regulated 3.0-V output option for
Port 1 I/Os, and multiple clock sources that include the IMO (internal main oscillator) and ILO (internal low-speed oscillator)
for precision, programmable clocking.
The CPU core, called the M8C, is a powerful processor with speeds up to 24 MHz. The M8C is a four MIPS 8-bit Harvard
architecture microprocessor. Within the CPU core are the SROM and Flash memory components that provide flexible pro-
gramming.
enCoRe V GPIOs provide connection to the CPU and external resources of the device. Each pin’s drive mode is selectable
from four options, allowing great flexibility in external interfacing. Every pin also has the capability to generate a system inter-
rupt on low level and change from last read.
System Resources
The System Resources provide additional enCoRe V capability. These system resources include:
■Digital clocks to increase flexibility.
■I2C functionality with “no bus stalling.”
■Various system resets supported by the M8C.
■Power-on-reset (POR) circuit protection.
■SPI master and slave functionality.
■A programmable timer to provide periodic interrupts.
■Clock boost network providing a stronger signal to switches.
■Full-speed USB interface for USB 2.0 communication with 512 bytes of dedicated buffer memory and an internal 3-V reg-
ulator.

enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H 11
enCoRe V Core Top-Level Block Diagram
CAPSENSE
SYSTEM
1K/2K
SRAM
Interrupt
Controller
Sleep and
Watchdog
M ultiple Clock Sources
Internal Low S peed O scillator (ILO )
6/12/2 4 M H z Intern al M ain O scillator
(IM O )
PSoC CORE
CPU Core (M8C)
Supervisory ROM (SROM) 8K/16K/32K Flash
Nonvolatile Memory
SYSTEM RESOURCES
SYSTEM BUS
Analog
Reference
SYSTEM BUS
Port 3 Port 2 Port 1 Port 0
CapSense
Module
Global Analog Interconnect
1.8/2.5/3V
LDO
Analog
Mux
Two
Comparators
I2C
Slave
SPI
Master/
Slave
POR
and
LVD
USB System
Resets
Internal
Voltage
References
Three 16-Bit
Programmable
Timers
PWRSYS
(Regulator)
Port 4
Digital
Clocks

enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H 12
Getting Started
The quickest path to understanding enCoRe V is by reading the enCoRe V device’s datasheet and using PSoC Designer™
Integrated Development Environment (IDE). This manual is useful for understanding the details of the enCoRe V integrated
circuit.
Important Note For the most up-to-date Ordering, Packaging, or Electrical Specification information, refer to the individual
enCoRe V device’s datasheet or go to http://www.cypress.com.
Support
Free support for enCoRe V products is available online at http://www.cypress.com. Resources include Training Seminars,
Discussion Forums, Application Notes, TightLink Technical Support Email/Knowledge Base, and Application Support Techni-
cians.
Technical Support can be reached at http://www.cypress.com/support.
Product Upgrades
Cypress provides scheduled upgrades and version enhancements for PSoC Designer free of charge. You can order the
upgrades from your distributor on CD-ROM or download them directly from http://www.cypress.com under Software. Also pro-
vided are critical updates to system documentation under http://www.cypress.com >> Documentation.
Development Kits
Development Kits are available from the following distributors: Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store
contains development kits, C compilers, and all accessories for enCoRe V development. Go to the Cypress Online Store at
http://www.cypress.com under Order >> USB Kits.
Document History
This section serves as a chronicle of the CY8C20XX6A/AS/LenCoRe™ V and enCoRe™ V LV CY7C643xx and CY7C604xx
Technical Reference Manual.
Technical Reference Manual History
Version/
Release Date Originator Description of Change
** September 2007 HMT First release of the enCoRe™ V and enCoRe™ V LV CY7C643xx and CY7C604xx Technical Reference Manual.
*A June 2008 HMT Second release of the enCoRe™ V and enCoRe™ V LV CY7C643xx and CY7C604xx Technical Reference Manual.
*B June 2009 FSU Third release of the enCoRe™ V and enCoRe™ V LV CY7C643xx and CY7C604xx Technical Reference Manual.
*C September 2009 FSU Fourth release of the enCoRe™ V and enCoRe™ V LV CY7C643xx and CY7C604xx Technical Reference Manual.
*D November 2009 FSU Multiple fixes, primarily to the sleep and I2C chapters.
*E December 2009 FSU Multiple fixes, primarily to the External Crystal Oscillator chapter.
*F September 2012 ANTG Updated external clock source description
*G October 2015 ASRI Removed all instances of IMODIS related information and provided information for "no glitch protection in the device for
an external clock".
*H November 2018 RAJV Updated the template

enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H 13
Documentation Conventions
There are only four distinguishing font types used in this
manual, besides those found in the headings.
■The first is the use of italics when referencing a docu-
ment title or file name.
■The second is the use of bold italics when referencing a
term described in the Glossary of this manual.
■The third is the use of Times New Roman font, distinguish-
ing equation examples.
■The fourth is the use of Courier New font, distinguish-
ing code examples.
Register Conventions
The following table lists the register conventions that are
specific to this manual. A more detailed set of register con-
ventions is located in the Register Reference chapter on
page 163.
Numeric Naming
Hexadecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example,
‘14h’ or ‘3Ah’) and hexadecimal numbers may also be rep-
resented by a ‘0x’ prefix, the C coding convention. Binary
numbers have an appended lowercase ‘b’ (for example,
01010100b’ or ‘01000011b’). Numbers not indicated by an
‘h’ or ‘b’ are decimal.
Units of Measure
This table lists the units of measure used in this manual.
Register Conventions
Convention Example Description
‘x’ in a register
name PRTxIE Multiple instances/address ranges of the same register
R R : 00 Read register or bit(s)
W W : 00 Write register or bit(s)
O RO : 00 Only a read/write register or bit(s).
L RL : 00 Logical register or bit(s)
C RC : 00 Clearable register or bit(s)
00 RW : 00 Reset value is 0x00 or 00h
XX RW : XX Register is not reset
0, 0,04h Register is in bank 0
1, 1,23h Register is in bank 1
x, x,F7h Register exists in register bank 0 and reg-
ister bank 1
Empty, grayed-
out table cell
Reserved bit or group of bits, unless oth-
erwise stated
Units of Measure
Symbol Unit of Measure
°C degrees Celsius
dB decibels
fF femtofarads
Hz hertz
kkilo, 1000
K210, 1024
KB 1024 bytes
Kbit 1024 bits
kHz kilohertz (32.000)
kkilohms
MHz megahertz
Mmegaohms
Amicroamperes
Fmicrofarads
smicroseconds
Vmicrovolts
Vrms microvolts root-mean-square
mA milliamperes
ms milliseconds
mV millivolts
nA nanoampheres
ns nanoseconds
nV nanovolts
ohms
pF picofarads
pp peak-to-peak
ppm parts per million
sps samples per second
sigma: one standard deviation
Vvolts

enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H 14
Acronyms
This table lists the acronyms that are used in this manual.
Acronyms
Acronym Description
ABUS analog output bus
AC alternating current
ADC analog-to-digital converter
API Application Programming Interface
BR bit rate
BRA bus request acknowledge
BRQ bus request
CI carry in
CMP compare
CO carry out
CPU central processing unit
CRC cyclic redundancy check
DAC digital-to-analog converter
DC direct current
DI digital or data input
DMA direct memory access
DO digital or data output
ECO external crystal oscillator
FB feedback
GIE global interrupt enable
GPIO general-purpose I/O
ICE in-circuit emulator
IDE integrated development environment
ILO internal low-speed oscillator
IMO internal main oscillator
I/O input/output
IOR I/O read
IOW I/O write
IPOR imprecise power-on-reset
IRQ interrupt request
ISR interrupt service routine
ISSP in system serial programming
IVR interrupt vector read
LRb last received bit
LRB last received byte
LSb least significant bit
LSB least significant byte
MISO master-in-slave-out
MOSI master-out-slave-in
MSb most significant bit
MSB most significant byte
PC program counter
PCH program counter high
PCL program counter low
PD power down
PMA PSoC® memory arbiter
POR power-on-reset
PPOR precision power-on-reset
PRS pseudo random sequence
PSSDC power system sleep duty cycle
RAM random access memory
RETI return from interrupt
RO relaxation oscillator
ROM read-only memory
RW read/write
SIE serial interface engine
SE0 single-ended zero
SOF start of frame
SP stack pointer
SPI serial peripheral interconnect
SPIM serial peripheral interconnect master
SPIS serial peripheral interconnect slave
SRAM static random access memory
SROM supervisory read-only memory
SSADC single slope ADC
SSC supervisory system call
TC terminal count
USB universal serial bus
WDT watchdog timer
WDR watchdog reset
XRES external reset
Acronyms (continued)
Acronym Description

enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H 15
1. Pin Information
This chapter lists, describes, and illustrates all pins and pinout configurations for the CY8C20X46A/46AS/96A/46L/
96LCY7C643xx and CY7C604xx enCoRe V devices. For up-to-date ordering, pinout, and packaging information, refer to the
individual enCoRe V device’s datasheet or go to http://www.cypress.com.
1.1 Pinouts
TheCY8C20X46A/46AS/96A/46L/96LCY7C643xx and CY7C604xx enCoRe V devices are available in a variety of packages.
Every port pin (labeled with a “P”), except for Vss, Vdd, and XRES in the following tables and illustrations, is capable of Dig-
ital I/O.
1.1.1 CY7C60413 enCoRe V LV 16-Pin Part Pinout
,
Table 1-1. 16-Pin QFN/COL Part Pinout
Pin
No.
Type Name Description Devices
Digital Analog
1IO IP2[5] XTAL Out
2IO IP2[3] XTAL In
3 IOHR I P1[7] I2C SCL, SPI SS
4 IOHR I P1[5] I2C SDA, SPI MISO
5 IOHR I P1[3] SPI CLK
6 IOHR I P1[1] TC CLK1, I2C SCL, SPI MOSI
7 Power Vss Ground pin
8 IOHR I P1[0] TC DATA1, I2C SDA, SPI CLK
9 IOHR I P1[2]
10 IOHR I P1[4] EXTCLK
11 Input XRES Active high external reset with internal pull down
12 IOH IP0[4]
13 Power Vdd Power pin
14 IOH IP0[7]
15 IOH IP0[3]
16 IOH IP0[1]
Legend A = Analog, I = Input, O = Output, H = 5-mA High Output Drive, R = Regulated Output Option.
1These are the ISSP pins, which are not High-Z at POR.
P2[5]
P1[7]
P1[5]
P1[3]
P0[3] P0[7]
Vdd
P0[4]
P1[1] P1[0]
P1[2]
P2[3]
P1[4]
XRES
P0[1]
Vss
QFN
(Top View)
1
2
3
4
12
11
10
9
16 15 14
13
5 6 7 8

enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H 16
Pin Information
1.1.2
CY7C60445 enCoRe V LV 32-Pin Part Pinout
Table 1-2. 32-Pin QFN Part Pinout2
Pin
No.
Digital
Analog
Name Description
CY7C60445 enCoRe V LV Devices
1IOH IP0[1] Integrating input
2IO I P2[7]
3IO I P2[5] XTAL Out
4IO IP2[3] XTAL In
5IO IP2[1]
6IO I P3[3]
7IO IP3[1]
8IOHR IP1[7] I2C SCL, SPI SS
9IOHR IP1[5] I2C SDA, SPI MISO
10 IOHR IP1[3] SPI CLK
11 IOHR IP1[1] TC CLK1, I2C SCL, SPI MOSI
12 Power Vss Ground pin
13 IOHR IP1[0] TC DATA1, I2C SDA, SPI CLK
14 IOHR IP1[2]
15 IOHR IP1[4] EXTCLK
16 IOHR IP1[6]
17 Input XRES Active high external reset with internal pull down
18 IO I P3[0]
19 IO I P3[2]
20 IO I P2[0]
21 IO IP2[2]
22 IO IP2[4]
23 IO IP2[6]
24 IOH IP0[0]
25 IOH IP0[2]
26 IOH IP0[4]
27 IOH IP0[6]
28 Power Vdd Power pin
29 IOH IP0[7]
30 IOH IP0[5]
31 IOH IP0[3]
32 Power Vss Ground pin
Legend A = Analog, I = Input, O = Output, NC = No Connection, H = 5 mA High Output Drive, R = Regulated Output Option.
1 These are the ISSP pins, which are not High-Z at POR.
2The center pad on the QFN package must be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not con-
nected to ground, it must be electrically floated and not connected to any other signal.
P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
P3[3]
QFN
(Top View)
9
10 11 12
13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
32
31
30
29
28 27 26
25
Vss
P0[3] P0[7]
Vdd
P0[6] P0[4] P0[2]
P3[1]
P1[7]
P0[0]
P2[6]
P3[0]
XRES
P1[5] P1[3]
P1[1]
Vss
P1[0] P1[2] P1[4] P1[6]
P2[4]
P2[2]
P2[0]
P3[2]
P0[5]

enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H 17
Pin Information
1.1.3 CY7C64345, CY7C64343, enCoRe V 32-Pin Part Pinout
Table 1-3. 32-Pin QFN Part Pinout2
Pin
No.
Digital
Analog
Name Description
CY7C64345, CY7C64343 enCoRe V Devices
1IOH IP0[1]
2IO I P2[5] XTAL Out
3IO IP2[3]XTAL In
4IO IP2[1]
5IOHR IP1[7] I2C SCL, SPI SS
6IOHR I P1[5] I2C SDA, SPI MISO
7IOHR IP1[3] SPI CLK
8IOHR IP1[1] TC CLK1, I2C SCL, SPI MOSI
9Power Vss Ground pin
10 IO D+ USB PHY
11 IO D- USB PHY
12 Power Vdd Power pin
13 IOHR IP1[0] TC DATA1, I2C SDA, SPI CLK
14 IOHR IP1[2]
15 IOHR IP1[4] EXTCLK
16 IOHR IP1[6]
17 Input XRES Active high external reset with internal
pull down
18 IO IP3[0]
19 IO IP3[2]
20 IO IP2[0]
21 IO IP2[2]
22 IO IP2[4]
23 IO IP2[6]
24 IOH IP0[0]
25 IOH IP0[2]
26 IOH IP0[4]
27 IOH IP0[6]
28 Power Vdd Power pin
29 IOH IP0[7]
30 IOH IP0[5]
31 IOH IP0[3]
32 Power Vss Ground pin
LEGEND A = Analog, I = Input, O = Output, NC = No Connection, H = 5 mA High Output Drive, R = Regulated Output Option.
1 These are the ISSP pins, which are not High Z at POR (Power On Reset).
2The center pad on the QFN package must be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not con-
nected to ground, it must be electrically floated and not connected to any other signal.
P0[1]
P2[5]
P2[3]
P2[1]
P1[7]
P1[5]
QFN
(Top View)
9
10 11 12
13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
32
31
30
29
28 27 26
25
Vss
P0[3] P0[7]
Vdd
P0[6] P0[4] P0[2]
P1[3]
P1[1]
P0[0]
P2[6]
P3[0]
XRES
Vss
D+
D-
Vdd
P1[0] P1[2] P1[4] P1[6]
P2[4]
P2[2]
P2[0]
P3[2]
P0[5]

enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H 18
Pin Information
1.1.4 CY8C20646A/AS/LCY8C20666A/AS/L
CY7C64355, CY7C64356 enCoRe V 48-Pin Part Pinout
Table 1-4. 48-Pin Part Pinout2
Pin
No.
Digital
Analog
Name Description
CY7C64355, CY7C64356 enCoRe VDevices
1NC No connection
2IO IP2[7]
3IO I P2[5] XTAL Out
4IO I P2[3] XTAL In
5IO IP2[1]
6IO IP4[3]
7IO IP4[1]
8IO IP3[7]
9IO IP3[5]
10 IO IP3[3]
11 IO IP3[1]
12 IOHR I P1[7] I2C SCL, SPI SS
13 IOHR I P1[5] I2C SDA, SPI MISO
14 NC No connection
15 NC No connection
16 IOHR I P1[3] SPI CLK
17 IOHR I P1[1] TC CLK1, I2C SCL, SPI MOSI
18 Power Vss Ground pin
19 IO D + USB PHY
20 IO D - USB PHY
21 Power Vdd Power pin
22 IOHR I P1[0] TC DATA1, I2C SDA, SPI CLK
23 IOHR I P1[2]
24 IOHR I P1[4] EXTCLK
25 IOHR I P1[6]
26 Input XRES Active high external reset with internal pull down
27 IO IP3[0]
28 IO IP3[2]
29 IO IP3[4]
30 IO IP3[6]
Pin
No.
Digital
Analog
Name Description31 IO IP4[0]
32 IO IP4[2]
33 IO IP2[0] 41 Power Vdd Power pin
34 IO IP2[2] 42 NC No connection
35 IO IP2[4] 43 NC No connection
36 IO IP2[6] 44 IOH IP0[7]
37 IOH IP0[0] 45 IOH IP0[5]
38 IOH IP0[2] 46 IOH IP0[3]
39 IOH IP0[4] 47 Power Vss Ground pin
40 IOH IP0[6] 48 IOH IP0[1]
Legend A = Analog, I = Input, O = Output, NC = No Connection, H = 5 mA High Output Drive, R = Regulated Output Option.
1These are the ISSP pins, which are not High-Z at POR.
2The center pad on the QFN package must be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected
to ground, it must be electrically floated and not connected to any other signal.
QFN
(Top View)
P0[1] Vss P0[3] P0[5] P0[7] NC NC Vdd P0[6]
P0[4]
P0[2] P0[0]
10
11
12
P2[7]
NC
P2[5]
P2[3]
P2[1]
P4[3]
P4[1]
P3[7]
P3[5]
P3[3]
P3[1]
P1[7]
35
34
33
32
31
30
29
28
27
26
25
36
48 47 46 45 44 43
42
41 40 39 38 37
P2[4]
P2[2]
P2[0]
P4[2]
P4[0]
P3[6]
P3[4]
P3[2]
P3[0]
XRES
P1[6]
P2[6]
1
2
3
4
5
6
7
8
9
13 14 15 16 17 18 19 20 21 22
23 24
P1[5]
NC NC
P1[3]
P1[1]
Vss
D+
D-
Vdd
P1[0]
P1[2] P1[4]

enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H 19
Pin Information
1.1.5 CY7C60455, CY7C60456 enCoRe V LV 48-Pin Part Pinout
Table 1-5. 48-Pin Part Pinout2
Pin
No.
Digital
Analog
Name Description
CY7C60455, CY7C60456 enCoRe V LV Devices
1NC No connection
2IO IP2[7]
3IO I P2[5] XTAL Out
4IO I P2[3] XTAL In
5IO IP2[1]
6IO IP4[3]
7IO IP4[1]
8IO IP3[7]
9IO IP3[5]
10 IO IP3[3]
11 IO IP3[1]
12 IOHR IP1[7] I2C SCL, SPI SS
13 IOHR IP1[5] I2C SDA, SPI MISO
14 NC No connection
15 NC No connection
16 IOHR IP1[3] SPI CLK
17 IOHR IP1[1] TC CLK1, I2C SCL, SPI MOSI
18 Power Vss Ground pin
19 NC No connection
20 NC No connection
21 Power Vdd Power pin
22 IOHR IP1[0] TC DATA1, I2C SDA, SPI CLK
23 IOHR IP1[2]
24 IOHR IP1[4] EXTCLK
25 IOHR IP1[6]
26 Input XRES Active high external reset with
internal pull down
27 IO IP3[0]
28 IO IP3[2]
29 IO IP3[4]
30 IO IP3[6]
31 IO IP4[0]
32 IO IP4[2] Pin
No.
Digital
Analog
Name Description
33 IO IP2[0] 41 Power Vdd Power pin
34 IO IP2[2] 42 NC No connection
35 IO IP2[4] 43 NC No connection
36 IO IP2[6] 44 IOH IP0[7]
37 IOH IP0[0] 45 IOH IP0[5]
38 IOH IP0[2] 46 IOH IP0[3]
39 IOH IP0[4] 47 Power Vss Ground pin
40 IOH IP0[6] 48 IOH IP0[1]
LEGEND A = Analog, I = Input, O = Output, NC = No Connection, H = 5 mA High Output Drive, R = Regulated Output Option.
1 These are the ISSP pins, which are not High Z at POR (Power On Reset).
2The center pad on the QFN package must be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not con-
nected to ground, it must be electrically floated and not connected to any other signal.
QFN
(Top View)
P0[1] Vss P0[3] P0[5] P0[7] NC NC Vdd P0[6]
P0[4]
P0[2] P0[0]
10
11
12
P2[7]
NC
P2[5]
P2[3]
P2[1]
P4[3]
P4[1]
P3[7]
P3[5]
P3[3]
P3[1]
P1[7]
35
34
33
32
31
30
29
28
27
26
25
36
48 47 46 45 44 43
42
41 40 39 38 37
P2[4]
P2[2]
P2[0]
P4[2]
P4[0]
P3[6]
P3[4]
P3[2]
P3[0]
XRES
P1[6]
P2[6]
1
2
3
4
5
6
7
8
9
13 14 15 16 17 18 19 20 21 22
23 24
P1[5]
NC NC
P1[3]
P1[1]
Vss
NC NC
Vdd
P1[0] P1[2] P1[4]

enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H 20
Pin Information
1.1.6 CY8C20066A, CY8CTMG200-00LTXI, CY8CTMG200A-00LTXI PSoC, CY7C64300
enCoRe V and CY7C60400 enCoRe V LV OCD 48-Pin Part Pinout
The 48-pin QFN part is for on-chip debugging (OCD). Note that this part is only used for in-circuit debugging. It is NOT avail-
able for production.
Table 1-6. 48-Pin OCD Part Pinout2
Pin
No.
Digital
Analog
Name Description
CY8C20066A, CY8CTMG200-00LTXI, CY8CTMG200A-00LTXI,
CY7C64300, CY7C60400 enCoRe V OCD Devices
1OCDOE OCD directional pin
2IO IP2[7]
3IO I P2[5] XTAL Out
4IO I P2[3] XTAL In
5IO IP2[1]
6IO IP4[3]
7IO IP4[1]
8IO IP3[7]
9IO IP3[5]
10 IO IP3[3]
11 IO IP3[1]
12 IOHR IP1[7] I2C SCL, SPI SS
13 IOHR IP1[5] I2C SDA, SPI MISO
14 CCLK OCD CPU CLK OUTPUT
15 HCLK OCD HIGH SPEED CLK
16 IOHR IP1[3] SPI CLK
17 IOHR IP1[1] TC CLK1, I2C SCL, SPI MOSI
18 Power Vss Ground pin
19 IO D+ USB PHY
20 IO D– USB PHY
21 Power Vdd Power pin
22 IOHR IP1[0] TC DATA1, I2C SDA, SPI CLK
23 IOHR IP1[2] NOT FOR PRODUCTION – OCD Part
24 IOHR IP1[4] EXTCLK
25 IOHR IP1[6]
26 Input XRES Active high external reset with
internal pull down
27 IO IP3[0]
28 IO IP3[2]
29 IO IP3[4]
30 IO IP3[6]
31 IO IP4[0]
32 IO IP4[2] Pin
No.
Digital
Analog
Name Description
33 IO IP2[0] 41 Power Vdd Power pin
34 IO IP2[2] 42 OCDO OCD even data I/O
35 IO IP2[4] 43 OCDE OCD odd data output
36 IO IP2[6] 44 IOH IP0[7]
37 IOH IP0[0] 45 IOH IP0[5]
38 IOH IP0[2] 46 IOH IP0[3]
39 IOH IP0[4] 47 Power Vss Ground pin
40 IOH IP0[6] 48 IOH IP0[1]
Legend A = Analog, I = Input, O = Output, NC = No Connection, H = 5-mA High Output Drive, R = Regulated Output Option.
1ISSP pin which is not High-Z at POR.
2The center pad (CP) on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not con-
nected to ground, it must be electrically floated and not connected to any other signal.
QFN
(Top View)
P0[1] Vss P0[3] P0[5] P0[7] OCDE OCDO Vdd P0[6]
P0[4]
P0[2] P0[0]
10
11
12
P2[7]
OCDOE
P2[5]
P2[3]
P2[1]
P4[3]
P4[1]
P3[7]
P3[5]
P3[3]
P3[1]
P1[7]
35
34
33
32
31
30
29
28
27
26
25
36
48 47 46 45 44 43
42
41 40 39 38 37
P2[4]
P2[2]
P2[0]
P4[2]
P4[0]
P3[6]
P3[4]
P3[2]
P3[0]
XRES
P1[6]
P2[6]
1
2
3
4
5
6
7
8
9
13 14 15 16 17 18 19 20 21 22
23 24
P1[5]
CCLK
HCLK
P1[3]
P1[1]
Vss
D +
D -
Vdd
P1[0] P1[2] P1[4]