Cypress PSoC CY8C24533 Product manual

PSoC® CY8C24533, CY8C23533, CY8C23433 TRM
PSoC®CY8C24533, CY8C23533, CY8C23433
Technical Reference Manual (TRM)
Document # 001-20559 Rev. *D
January 19, 2017
Cypress Semiconductor
198 Champion Court
San Jose, CA 95134-1709
Phone (USA): 800.858.1810
Phone (Intnl.): 408.943.2600
http://www.cypress.com

2Document # 001-20559 Rev. *D
Copyrights
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Document # 001-20559 Rev. *D 3
Contents Overview
Section A: Overview 17
1. Pin Information .................................................................................................................25
Section B: PSoC Core 31
2. CPU Core (M8C) ..............................................................................................................35
3. Supervisory ROM (SROM)...............................................................................................45
4. RAM Paging......................................................................................................................55
5. Interrupt Controller...........................................................................................................61
6. General Purpose IO (GPIO) ............................................................................................69
7. Analog Output Drivers......................................................................................................77
8. Internal Main Oscillator (IMO) .........................................................................................79
9. Internal Low Speed Oscillator (ILO)................................................................................83
10. External Crystal Oscillator (ECO)....................................................................................85
11. Phase-Locked Loop (PLL) ...............................................................................................91
12. Sleep and Watchdog ........................................................................................................95
Section C: Register Reference 107
13. Register Details...............................................................................................................111
Section D: Digital System 225
14. Global Digital Interconnect (GDI)..................................................................................229
15. Array Digital Interconnect (ADI) ....................................................................................233
16. Row Digital Interconnect (RDI)......................................................................................235
17. Digital Blocks..................................................................................................................241
Section E: Analog System 279
18. Analog Interface .............................................................................................................283
19. Analog Array...................................................................................................................297
20. Analog Input Configuration............................................................................................305
21. Analog Reference...........................................................................................................309
22. Continuous Time PSoC Block........................................................................................313
23. Switched Capacitor PSoC Block ...................................................................................319
24. SAR8 ADC PSoC Block .................................................................................................329
Section F: System Resources 335
25. Digital Clocks..................................................................................................................339
26. Multiply Accumulate (MAC) ...........................................................................................349
27. Decimator........................................................................................................................355
28. I2C...................................................................................................................................359
29. Internal Voltage Reference ............................................................................................375
30. System Resets................................................................................................................377
31. POR and LVD .................................................................................................................383

Contents Overview
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Section G: Glossary 385
Index 401

Document # 001-20559 Rev. *D 5
Contents
Section A: Overview 17
Document Organization ......................................................................................................................17
Top-Level Architecture ........................................................................................................................18
PSoC Core ................................................................................................................................18
Digital System ............................................................................................................................18
Analog System ..........................................................................................................................18
System Resources ....................................................................................................................18
PSoC Device Characteristics ..............................................................................................................20
PSoC Device Distinctions ...................................................................................................................20
Getting Started ...................................................................................................................................21
Support ......................................................................................................................................21
Product Upgrades ......................................................................................................................21
Development Kits .....................................................................................................................21
Document History ................................................................................................................................21
Documentation Conventions ..............................................................................................................22
Register Conventions ..............................................................................................................22
Numeric Naming .......................................................................................................................22
Units of Measure ....................................................................................................................22
Acronyms ..................................................................................................................................23
1. Pin Information..................................................................................................................25
1.1 Pinouts .......................................................................................................................................25
1.1.1 28-Pin Part Pinout.......................................................................................................26
1.1.2 32-Pin Part Pinout.......................................................................................................28
1.1.3 56-Pin Part Pinout.......................................................................................................29
Section B: PSoC Core 31
Top-Level Core Architecture ................................................................................................................31
Interpreting Core Documentation .........................................................................................................31
Core Register Summary ......................................................................................................................32
2. CPU Core (M8C).................................................................................................................35
2.1 Overview ....................................................................................................................................35
2.2 Internal Registers ....................................................................................................................35
2.3 Address Spaces .......................................................................................................................35
2.4 Instruction Set Summary ............................................................................................................36
2.5 Instruction Formats ...................................................................................................................38
2.5.1 One-Byte Instructions..................................................................................................38
2.5.2 Two-Byte Instructions..................................................................................................38
2.5.3 Three-Byte Instructions...............................................................................................39
2.6 Addressing Modes ....................................................................................................................39
2.6.1 Source Immediate.......................................................................................................39
2.6.2 Source Direct ..............................................................................................................40
2.6.3 Source Indexed...........................................................................................................40

Contents Overview
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2.6.4 Destination Direct .......................................................................................................41
2.6.5 Destination Indexed ...................................................................................................41
2.6.6 Destination Direct Source Immediate .........................................................................41
2.6.7 Destination Indexed Source Immediate......................................................................42
2.6.8 Destination Direct Source Direct.................................................................................42
2.6.9 Source Indirect Post Increment ..................................................................................43
2.6.10 Destination Indirect Post Increment............................................................................43
2.7 Register Definitions ...................................................................................................................44
2.7.1 CPU_F Register .........................................................................................................44
3. Supervisory ROM (SROM)................................................................................................. 45
3.1 Architectural Description ...........................................................................................................45
3.1.1 Additional SROM Feature...........................................................................................46
3.1.2 SROM Function Descriptions ....................................................................................46
3.1.2.1 SWBootReset Function ............................................................................46
3.1.2.2 ReadBlock Function..................................................................................47
3.1.2.3 WriteBlock Function..................................................................................48
3.1.2.4 EraseBlock Function.................................................................................48
3.1.2.5 ProtectBlock Function...............................................................................49
3.1.2.6 TableRead Function ................................................................................49
3.1.2.7 EraseAll Function......................................................................................49
3.1.2.8 Checksum Function..................................................................................50
3.1.2.9 Calibrate0 Function...................................................................................50
3.1.2.10 Calibrate1 Function...................................................................................50
3.2 Register Definitions ..................................................................................................................51
3.2.1 CPU_SCR1 Register .................................................................................................51
3.2.2 FLS_PR1 Register .....................................................................................................52
3.3 Clocking ....................................................................................................................................53
3.3.1 DELAY Parameter.......................................................................................................53
3.3.2 CLOCK Parameter......................................................................................................53
4. RAM Paging ...................................................................................................................... 55
4.1 Architectural Description ...........................................................................................................55
4.1.1 Basic Paging ..............................................................................................................55
4.1.2 Stack Operations .......................................................................................................56
4.1.3 Interrupts ....................................................................................................................56
4.1.4 MVI Instructions .........................................................................................................56
4.1.5 Current Page Pointer .................................................................................................56
4.1.6 Index Memory Page Pointer ......................................................................................57
4.2 Register Definitions ...................................................................................................................58
4.2.1 TMP_DRx Registers ..................................................................................................58
4.2.2 CPU_F Register..........................................................................................................59
5. Interrupt Controller........................................................................................................... 61
5.1 Architectural Description ............................................................................................................61
5.1.1 Posted versus Pending Interrupts...............................................................................62
5.2 Application Description ..............................................................................................................63
5.3 Register Definitions ...................................................................................................................64
5.3.1 INT_CLRx Registers ..................................................................................................64
5.3.1.1 INT_CLR0 Register ..................................................................................64
5.3.1.2 INT_CLR1 Register ..................................................................................65
5.3.1.3 INT_CLR3 Register ..................................................................................65
5.3.2 INT_MSKx Registers .................................................................................................65
5.3.2.1 INT_MSK3 Register..................................................................................65

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Contents Overview
5.3.2.2 INT_MSK0 Register..................................................................................66
5.3.2.3 INT_MSK1 Register..................................................................................66
5.3.3 INT_VC Register ........................................................................................................66
5.3.4 CPU_F Register .........................................................................................................67
6. General Purpose IO (GPIO) ...............................................................................................69
6.1 Architectural Description.............................................................................................................69
6.1.1 Digital IO ....................................................................................................................69
6.1.2 Global IO ....................................................................................................................70
6.1.3 Analog Input ...............................................................................................................70
6.1.4 GPIO Block Interrupts ...............................................................................................71
6.2 Register Definitions ...................................................................................................................72
6.2.1 PRTxDR Registers .....................................................................................................72
6.2.2 PRTxIE Registers .......................................................................................................72
6.2.3 PRTxGS Registers .....................................................................................................73
6.2.4 PRTxDMx Registers ................................................................................................74
6.2.5 PRTxICx Registers ...................................................................................................75
7. Analog Output Drivers ......................................................................................................77
7.1 Architectural Description ............................................................................................................77
7.2 Register Definitions ..................................................................................................................78
7.2.1 ABF_CR0 Register .....................................................................................................78
8. Internal Main Oscillator (IMO) ...........................................................................................79
8.1 Architectural Description.............................................................................................................79
8.2 Application Description...............................................................................................................79
8.2.1 Trimming the IMO .......................................................................................................79
8.3 Register Definitions ...................................................................................................................80
8.3.1 CPU_SCR1 Register ..................................................................................................80
8.3.2 OSC_CR2 Register ....................................................................................................81
8.3.3 IMO_TR Register .......................................................................................................81
9. Internal Low Speed Oscillator (ILO)..................................................................................83
9.1 Architectural Description.............................................................................................................83
9.2 Register Definitions ...................................................................................................................83
9.2.1 ILO_TR Register ........................................................................................................83
10. External Crystal Oscillator (ECO) .....................................................................................85
10.1 Architectural Description.............................................................................................................85
10.1.1 ECO External Components.........................................................................................86
10.2 PSoC Device Distinctions...........................................................................................................86
10.3 Register Definitions ...................................................................................................................87
10.3.1 CPU_SCR1 Register .................................................................................................87
10.3.2 OSC_CR0 Register ....................................................................................................88
10.3.3 ECO_TR Register ......................................................................................................89
11. Phase-Locked Loop (PLL).................................................................................................91
11.1 Architectural Description.............................................................................................................91
11.2 Register Definitions ..................................................................................................................91
11.2.1 OSC_CR0 Register.....................................................................................................92
11.2.2 OSC_CR2 Register ....................................................................................................93
12. Sleep and Watchdog..........................................................................................................95
12.1 Architectural Description.............................................................................................................95
12.1.1 32 kHz Clock Selection ..............................................................................................95

Contents Overview
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12.1.2 Sleep Timer ..............................................................................................................95
12.2 Application Description...............................................................................................................96
12.3 Register Definitions ...................................................................................................................97
12.3.1 INT_MSK0 Register ...................................................................................................97
12.3.2 RES_WDT Register ...................................................................................................97
12.3.3 CPU_SCR1 Register ................................................................................................98
12.3.4 CPU_SCR0 Register .................................................................................................99
12.3.5 OSC_CR0 Register .................................................................................................100
12.3.6 ILO_TR Register ......................................................................................................101
12.3.7 ECO_TR Register ....................................................................................................101
12.4 Timing Diagrams......................................................................................................................102
12.4.1 Sleep Sequence .......................................................................................................102
12.4.2 Wake Up Sequence..................................................................................................103
12.4.3 Bandgap Refresh......................................................................................................104
12.4.4 Watchdog Timer........................................................................................................104
12.5 Power Consumption.................................................................................................................105
Section C: Register Reference 107
Register General Conventions ...........................................................................................................107
Register Naming Conventions ...........................................................................................................107
Register Mapping Tables ...................................................................................................................107
Register Map Bank 0 Table: User Space .............................................................................108
Register Map Bank 1 Table: Configuration Space ...............................................................109
13. Register Details................................................................................................................111
13.1 Maneuvering Around the Registers..........................................................................................111
Register Conventions ............................................................................................................112
13.1.1 Register Naming Conventions .................................................................................112
13.2 Bank 0 Registers .....................................................................................................................113
13.2.1 PRTxDR ...................................................................................................................113
13.2.2 PRTxIE ....................................................................................................................114
13.2.3 PRTxGS ...................................................................................................................115
13.2.4 PRTxDM2 ................................................................................................................116
13.2.5 DxBxxDR0 ...............................................................................................................117
13.2.6 DxBxxDR1 ...............................................................................................................118
13.2.7 DxBxxDR2 ...............................................................................................................119
13.2.8 DxBxxCR0 (Timer Control) ......................................................................................120
13.2.9 DxBxxCR0 (Counter Control) ..................................................................................121
13.2.10 DxBxxCR0 (Dead Band Control) ............................................................................122
13.2.11 DxBxxCR0 (CRCPRS Control) ................................................................................123
13.2.12 DCBxxCR0 (SPIM Control) ......................................................................................124
13.2.13 DCBxxCR0 (SPIS Control) ......................................................................................125
13.2.14 DCBxxCR0 (UART Transmitter Control) .................................................................126
13.2.15 DCBxxCR0 (UART Receiver Control) .....................................................................127
13.2.16 AMX_IN ...................................................................................................................128
13.2.17 ARF_CR ..................................................................................................................129
13.2.18 CMP_CR0 ................................................................................................................130
13.2.19 ASY_CR ..................................................................................................................131
13.2.20 CMP_CR1 ................................................................................................................132
13.2.21 SARADC_DL ...........................................................................................................133
13.2.22 SARADC_CR0 .........................................................................................................134
13.2.23 SARADC_CR1 .........................................................................................................135
13.2.24 TMP_DRx ................................................................................................................136

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Contents Overview
13.2.25 ACBxxCR3 ...............................................................................................................137
13.2.26 ACBxxCR0 ...............................................................................................................138
13.2.27 ACBxxCR1 ...............................................................................................................140
13.2.28 ACBxxCR2 ...............................................................................................................142
13.2.29 ASDxxCR0 ...............................................................................................................143
13.2.30 ASDxxCR1 ...............................................................................................................144
13.2.31 ASDxxCR2 ...............................................................................................................145
13.2.32 ASDxxCR3 ...............................................................................................................146
13.2.33 ASCxxCR0 ...............................................................................................................147
13.2.34 ASCxxCR1 ...............................................................................................................148
13.2.35 ASCxxCR2 ...............................................................................................................149
13.2.36 ASCxxCR3 ...............................................................................................................150
13.2.37 RDIxRI ......................................................................................................................151
13.2.38 RDIxSYN ..................................................................................................................152
13.2.39 RDIxIS ......................................................................................................................153
13.2.40 RDIxLT0 ...................................................................................................................154
13.2.41 RDIxLT1 ...................................................................................................................155
13.2.42 RDIxRO0 ..................................................................................................................156
13.2.43 RDIxRO1 ..................................................................................................................157
13.2.44 I2C_CFG ..................................................................................................................158
13.2.45 I2C_SCR ..................................................................................................................159
13.2.46 I2C_DR ....................................................................................................................161
13.2.47 I2C_MSCR ...............................................................................................................162
13.2.48 INT_CLR0 ................................................................................................................163
13.2.49 INT_CLR1 ................................................................................................................165
13.2.50 INT_CLR3 ................................................................................................................166
13.2.51 INT_MSK3 ................................................................................................................167
13.2.52 INT_MSK0 ................................................................................................................168
13.2.53 INT_MSK1 ................................................................................................................169
13.2.54 INT_VC ....................................................................................................................170
13.2.55 RES_WDT ................................................................................................................171
13.2.56 DEC_DH ..................................................................................................................172
13.2.57 DEC_DL ..................................................................................................................173
13.2.58 DEC_CR0 ...............................................................................................................174
13.2.59 DEC_CR1 ................................................................................................................175
13.2.60 MULx_X ...................................................................................................................176
13.2.61 MULx_Y ...................................................................................................................177
13.2.62 MULx_DH .................................................................................................................178
13.2.63 MULx_DL .................................................................................................................179
13.2.64 MACx_X/ACCx_DR1 ...............................................................................................180
13.2.65 MACx_Y/ACCx_DR0 ...............................................................................................181
13.2.66 MACx_CL0/ACCx_DR3 ...........................................................................................182
13.2.67 MACx_CL1/ACCx_DR2 ...........................................................................................183
13.2.68 CPU_F ................................................................................................................184
13.2.69 CPU_SCR1 .........................................................................................................185
13.2.70 CPU_SCR0 ..............................................................................................................186
13.3 Bank 1 Registers .....................................................................................................................187
13.3.1 PRTxDM0 .................................................................................................................187
13.3.2 PRTxDM1 .................................................................................................................188
13.3.3 PRTxIC0 ...................................................................................................................189
13.3.4 PRTxIC1 ...................................................................................................................190
13.3.5 DxBxxFN ..................................................................................................................191
13.3.6 DxBxxIN ...................................................................................................................193

Contents Overview
10 Document # 001-20559 Rev. *D
13.3.7 DxBxxOU .................................................................................................................195
13.3.8 CLK_CR0 .................................................................................................................197
13.3.9 CLK_CR1 .................................................................................................................198
13.3.10 ABF_CR0 .............................................................................................................199
13.3.11 AMD_CR0 ................................................................................................................200
13.3.12 AMD_CR1 ................................................................................................................201
13.3.13 ALT_CR0 .................................................................................................................202
13.3.14 SARADC_TRS .........................................................................................................203
13.3.15 SARADC_TRCL ......................................................................................................204
13.3.16 SARADC_TRCH ......................................................................................................205
13.3.17 SARADC_CR2 .........................................................................................................206
13.3.18 SARADC_LCR .........................................................................................................207
13.3.19 GDI_O_IN ................................................................................................................208
13.3.20 GDI_E_IN ................................................................................................................209
13.3.21 GDI_O_OU ..............................................................................................................210
13.3.22 GDI_E_OU ...............................................................................................................211
13.3.23 OSC_GO_EN ..........................................................................................................212
13.3.24 OSC_CR4 ................................................................................................................213
13.3.25 OSC_CR3 ................................................................................................................214
13.3.26 OSC_CR0 ............................................................................................................215
13.3.27 OSC_CR1 ................................................................................................................216
13.3.28 OSC_CR2 ...............................................................................................................217
13.3.29 VLT_CR ...................................................................................................................218
13.3.30 VLT_CMP ................................................................................................................219
13.3.31 IMO_TR ...................................................................................................................220
13.3.32 ILO_TR ....................................................................................................................221
13.3.33 BDG_TR .................................................................................................................222
13.3.34 ECO_TR ..................................................................................................................223
13.3.35 FLS_PR1 ................................................................................................................224
Section D: Digital System 225
Top-Level Digital Architecture ...........................................................................................................225
Interpreting the Digital Documentation .............................................................................................225
Digital Register Summary .................................................................................................................226
14. Global Digital Interconnect (GDI).................................................................................... 229
14.1 Architectural Description .........................................................................................................229
14.1.1 28-Pin Global Interconnect .....................................................................................230
14.2 Register Definitions .................................................................................................................231
14.2.1 GDI_x_IN Registers ...............................................................................................231
14.2.2 GDI_x_OU Registers ...............................................................................................232
15. Array Digital Interconnect (ADI) ..................................................................................... 233
15.1 Architectural Description ..........................................................................................................233
16. Row Digital Interconnect (RDI) ....................................................................................... 235
16.1 Architectural Description ..........................................................................................................235
16.2 Register Definitions .................................................................................................................237
16.2.1 RDIxRI Register .......................................................................................................237
16.2.2 RDIxSYN Register ...................................................................................................237
16.2.3 RDIxIS Register .......................................................................................................238
16.2.4 RDIxLTx Registers .................................................................................................239
16.2.5 RDIxROx Registers ...............................................................................................240
16.2.5.1 RDIxRO0 Register..................................................................................240

Document # 001-20559 Rev. *D 11
Contents Overview
16.2.5.2 RDIxRO1 Register..................................................................................240
16.3 Timing Diagram ......................................................................................................................240
17. Digital Blocks ..................................................................................................................241
17.1 Architectural Description...........................................................................................................241
17.1.1 Input Multiplexers .....................................................................................................242
17.1.2 Input Clock Resynchronization .................................................................................242
17.1.2.1 Clock Resynchronization Summary........................................................243
17.1.3 Output De-Multiplexers ............................................................................................243
17.1.4 Block Chaining Signals ............................................................................................243
17.1.5 Input Data Synchronization.......................................................................................243
17.1.6 Timer Function .........................................................................................................243
17.1.6.1 Usability Exceptions................................................................................243
17.1.6.2 Block Interrupt.........................................................................................243
17.1.7 Counter Function ......................................................................................................244
17.1.7.1 Usability Exceptions................................................................................244
17.1.7.2 Block Interrupt.........................................................................................244
17.1.8 Dead Band Function ................................................................................................244
17.1.8.1 Usability Exceptions................................................................................245
17.1.8.2 Block Interrupt.........................................................................................245
17.1.9 CRCPRS Function ...................................................................................................245
17.1.9.1 Usability Exceptions................................................................................246
17.1.9.2 Block Interrupt.........................................................................................246
17.1.10 SPI Protocol Function ..............................................................................................247
17.1.10.1 SPI Protocol Signal Definitions...............................................................247
17.1.11 SPI Master Function .................................................................................................247
17.1.11.1 Usability Exceptions................................................................................248
17.1.11.2 Block Interrupt.........................................................................................248
17.1.12 SPI Slave Function ...................................................................................................248
17.1.12.1 Usability Exceptions................................................................................248
17.1.12.2 Block Interrupt.........................................................................................248
17.1.13 Asynchronous Transmitter and Receiver Functions .............................................249
17.1.13.1 Asynchronous Transmitter Function.......................................................249
17.1.13.2 Usability Exceptions................................................................................249
17.1.13.3 Block Interrupt.........................................................................................249
17.1.13.4 Asynchronous Receiver Function ...........................................................249
17.1.13.5 Usability Exceptions................................................................................250
17.1.13.6 Block Interrupt.........................................................................................250
17.2 Register Definitions .................................................................................................................251
17.2.1 DxBxxDRx Registers ................................................................................................252
17.2.1.1 Timer Register Definitions.......................................................................252
17.2.1.2 Counter Register Definitions...................................................................253
17.2.1.3 Dead Band Register Definitions..............................................................253
17.2.1.4 CRCPRS Register Definitions.................................................................254
17.2.1.5 SPI Master Register Definitions..............................................................254
17.2.1.6 SPI Slave Register Definitions................................................................255
17.2.1.7 Transmitter Register Definitions..............................................................255
17.2.1.8 Receiver Register Definitions..................................................................255
17.2.2 DxBxxCR0 Register .................................................................................................256
17.2.3 INT_MSK1 Register ...............................................................................................257
17.2.4 DxBxxFN Registers ..................................................................................................257
17.2.5 DxBxxIN Registers ...................................................................................................259
17.2.6 DxBxxOU Registers .................................................................................................260

Contents Overview
12 Document # 001-20559 Rev. *D
17.3 Timing Diagrams .....................................................................................................................262
17.3.1 Timer Timing ............................................................................................................262
17.3.2 Counter Timing ........................................................................................................263
17.3.3 Dead Band Timing ...................................................................................................264
17.3.3.1 Changing the PWM Duty Cycle..............................................................264
17.3.3.2 Kill Operation..........................................................................................265
17.3.4 CRCPRS Timing ......................................................................................................266
17.3.5 SPI Mode Timing .....................................................................................................266
17.3.6 SPIM Timing ............................................................................................................267
17.3.7 SPIS Timing .............................................................................................................270
17.3.8 Transmitter Timing ...................................................................................................273
17.3.9 Receiver Timing .......................................................................................................275
Section E: Analog System 279
Top-Level Analog Architecture ..........................................................................................................279
Interpreting the Analog Documentation ............................................................................................279
Application Description ......................................................................................................................280
Defining the Analog Blocks .....................................................................................................280
Analog Functionality ................................................................................................................280
Analog Register Summary .................................................................................................................281
18. Analog Interface.............................................................................................................. 283
18.1 Architectural Description .........................................................................................................283
18.1.1 Analog Data Bus Interface .......................................................................................284
18.1.2 Analog Comparator Bus Interface ............................................................................284
18.1.3 Analog Column Clock Generation ...........................................................................285
18.1.3.1 Column Clock Synchronization...............................................................285
18.1.4 Decimator and Incremental ADC Interface ..............................................................285
18.1.4.1 Decimator ...............................................................................................285
18.1.4.2 Incremental ADC ...................................................................................285
18.1.5 Analog Modulator Interface (Mod Bits) ....................................................................286
18.1.6 Analog Synchronization Interface (Stalling) .............................................................286
18.2 PSoC Device Distinctions.........................................................................................................286
18.3 Application Description.............................................................................................................286
18.3.1 SAR Hardware Acceleration ....................................................................................286
18.3.1.1 Architectural Description.........................................................................287
18.3.1.2 Application Description...........................................................................287
18.3.1.3 SAR Timing.............................................................................................290
18.4 Register Definitions .................................................................................................................291
18.4.1 CMP_CR0 Register ...............................................................................................291
18.4.2 ASY_CR Register ....................................................................................................291
18.4.3 CMP_CR1 Register .................................................................................................292
18.4.4 DEC_CR0 Register ..................................................................................................293
18.4.5 DEC_CR1 Register ..................................................................................................293
18.4.6 CLK_CR0 Register ..................................................................................................294
18.4.7 CLK_CR1 Register ..................................................................................................294
18.4.8 AMD_CR0 Register .................................................................................................295
18.4.9 AMD_CR1 Register .................................................................................................295
18.4.10 ALT_CR0 Register ...................................................................................................295
19. Analog Array ................................................................................................................... 297
19.1 Architectural Description ..........................................................................................................297
19.1.1 NMux Connections General Overview......................................................................298

Document # 001-20559 Rev. *D 13
Contents Overview
19.1.2 PMux Connections General Overview......................................................................299
19.1.3 RBotMux Connections General Overview.................................................................300
19.1.4 AMux Connections General Overview .....................................................................301
19.1.5 CMux Connections General Overview......................................................................302
19.1.6 BMux SC/SD Connections General Overview..........................................................303
19.1.7 Analog Comparator Bus ...........................................................................................303
19.2 Temperature Sensing Capability .............................................................................................303
20. Analog Input Configuration.............................................................................................305
20.1 Architectural Description...........................................................................................................305
20.1.1 Two Column Analog Input Configuration...................................................................306
20.2 Register Definitions ................................................................................................................307
20.2.1 AMX_IN Register .....................................................................................................307
20.2.2 ABF_CR0 Register ...................................................................................................307
21. Analog Reference............................................................................................................309
21.1 Architectural Description...........................................................................................................309
21.2 Register Definitions .................................................................................................................310
21.2.1 ARF_CR Register ....................................................................................................310
22. Continuous Time PSoC Block.........................................................................................313
22.1 Architectural Description ..........................................................................................................313
22.2 Register Definitions .................................................................................................................315
22.2.1 ACBxxCR3 Register .................................................................................................315
22.2.2 ACBxxCR0 Register .................................................................................................317
22.2.3 ACBxxCR1 Register .................................................................................................317
22.2.4 ACBxxCR2 Register .................................................................................................318
23. Switched Capacitor PSoC Block .....................................................................................319
23.1 Architectural Description...........................................................................................................319
23.2 Application Description.............................................................................................................321
23.3 Register Definitions .................................................................................................................322
23.3.1 ASCxxCR0 Register .................................................................................................323
23.3.2 ASCxxCR1 Register .................................................................................................324
23.3.3 ASCxxCR2 Register .................................................................................................324
23.3.4 ASCxxCR3 Register .................................................................................................325
23.3.5 ASDxxCR0 Register .................................................................................................326
23.3.6 ASDxxCR1 Register .................................................................................................327
23.3.7 ASDxxCR2 Register .................................................................................................327
23.3.8 ASDxxCR3 Register .................................................................................................328
24. SAR8 ADC PSoC Block ...................................................................................................329
24.1 Architectural Description...........................................................................................................329
24.1.1 Features....................................................................................................................329
24.2 Register Definitions .................................................................................................................330
24.2.1 SARADC_DL Register .............................................................................................330
24.2.2 SARADC_CR0 Register ...........................................................................................330
24.2.3 SARADC_CR1 Register ...........................................................................................331
24.2.4 SARADC_TRS Register ...........................................................................................332
24.2.5 SARADC_TRCL Register ........................................................................................333
24.2.6 SARADC_TRCH Register ........................................................................................333
24.2.7 SARADC_CR2 Register ...........................................................................................334
24.2.8 SARADC_LCR Register ...........................................................................................334

Contents Overview
14 Document # 001-20559 Rev. *D
Section F: System Resources 335
Top-Level System Resources Architecture .......................................................................................335
Interpreting the System Resources Documentation .........................................................................335
System Resources Register Summary ..............................................................................................336
25. Digital Clocks.................................................................................................................. 339
25.1 Architectural Description ..........................................................................................................339
25.1.1 Internal Main Oscillator ............................................................................................339
25.1.2 Internal Low Speed Oscillator ..................................................................................339
25.1.3 32.768 kHz Crystal Oscillator....................................................................................341
25.1.4 External Clock ........................................................................................................341
25.1.4.1 Clock Doubler.........................................................................................341
25.1.4.2 Switch Operation ....................................................................................341
25.2 PSoC Device Distinctions.........................................................................................................342
25.3 Register Definitions .................................................................................................................343
25.3.1 INT_CLR0 Register .................................................................................................343
25.3.2 INT_MSK0 Register .................................................................................................343
25.3.3 OSC_GO_EN Register ............................................................................................344
25.3.4 OSC_CR4 Register .................................................................................................344
25.3.5 OSC_CR3 Register .................................................................................................345
25.3.6 OSC_CR0 Register ...............................................................................................346
25.3.7 OSC_CR1 Register .................................................................................................347
25.3.8 OSC_CR2 Register ...............................................................................................348
26. Multiply Accumulate (MAC) ............................................................................................ 349
26.1 Architectural Description .........................................................................................................349
26.2 Application Description.............................................................................................................350
26.2.1 Multiplication with No Accumulation ........................................................................350
26.2.2 Accumulation After Multiplication..............................................................................350
26.3 Register Definitions .................................................................................................................351
26.3.1 MULx_X Register .....................................................................................................351
26.3.2 MULx_Y Register .....................................................................................................351
26.3.3 MULx_DH Register ..................................................................................................352
26.3.4 MULx_DL Register ..................................................................................................352
26.3.5 MACx_X/ACCx_DR1 Register .................................................................................352
26.3.6 MACx_Y/ACCx_DR0 Register .................................................................................353
26.3.7 MACx_CL0/ACCx_DR3 Register ............................................................................353
26.3.8 MACx_CL1/ACCx_DR2 Register ............................................................................353
27. Decimator........................................................................................................................ 355
27.1 Architectural Description ..........................................................................................................355
27.1.1 Decimator Block .......................................................................................................355
27.2 Register Definitions .................................................................................................................357
27.2.1 DEC_DH Register ....................................................................................................357
27.2.2 DEC_DL Register ....................................................................................................357
27.2.3 DEC_CR0 Register ..................................................................................................358
27.2.4 DEC_CR1 Register ..................................................................................................358
28. I2C ................................................................................................................................... 359
28.1 Architectural Description ..........................................................................................................359
28.1.1 Basic I2C Data Transfer............................................................................................359
28.2 Application Description.............................................................................................................360
28.2.1 Slave Operation .......................................................................................................360
28.2.2 Master Operation .....................................................................................................361

Document # 001-20559 Rev. *D 15
Contents Overview
28.3 Register Definitions .................................................................................................................362
28.3.1 I2C_CFG Register ....................................................................................................362
28.3.2 I2C_SCR Register ....................................................................................................364
28.3.3 I2C_DR Register ......................................................................................................366
28.3.4 I2C_MSCR Register .................................................................................................366
28.4 Timing Diagrams ......................................................................................................................368
28.4.1 Clock Generation ......................................................................................................368
28.4.2 Basic Input/Output Timing.........................................................................................368
28.4.3 Status Timing ............................................................................................................369
28.4.4 Master Start Timing...................................................................................................370
28.4.5 Master Restart Timing...............................................................................................371
28.4.6 Master Stop Timing ..................................................................................................371
28.4.7 Master/Slave Stall Timing .........................................................................................372
28.4.8 Master Lost Arbitration Timing .................................................................................372
28.4.9 Master Clock Synchronization...................................................................................373
29. Internal Voltage Reference..............................................................................................375
29.1 Architectural Description...........................................................................................................375
29.2 Register Definitions .................................................................................................................376
29.2.1 BDG_TR Register ....................................................................................................376
30. System Resets.................................................................................................................377
30.1 Architectural Description...........................................................................................................377
30.2 Pin Behavior During Reset .......................................................................................................377
30.2.1 GPIO Behavior on Power Up....................................................................................377
30.3 Register Definitions .................................................................................................................378
30.3.1 CPU_SCR1 Register ..............................................................................................378
30.3.2 CPU_SCR0 Register ................................................................................................379
30.4 Timing Diagrams .....................................................................................................................380
30.4.1 Power On Reset .......................................................................................................380
30.4.2 Watchdog Timer Reset .............................................................................................380
30.4.3 Reset Details.............................................................................................................382
30.5 Power Consumption ................................................................................................................382
31. POR and LVD ...................................................................................................................383
31.1 Architectural Description...........................................................................................................383
31.2 Register Definitions .................................................................................................................384
31.2.1 VLT_CR Register .....................................................................................................384
31.2.2 VLT_CMP Register ..................................................................................................384
Section G: Glossary 385
Index 401

Contents Overview
16 Document # 001-20559 Rev. *D

Document # 001-20559 Rev. *D 17
Section A: Overview
The PSoC® family consists of programmable system-on-chips with on-chip controller devices. As described in this technical
reference manual (TRM), a PSoC device includes configurable blocks of analog circuits and digital logic, as well as pro-
grammable interconnect. This architecture allows the user to create customized peripheral configurations, to match the
requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and con-
figurable input/output (IO) are included in a range of pinouts.
This document is a technical reference manual for the PSoC device: CY8C24533, CY8C23533, CY8C23433CY8C24633. For
the most up-to-date Ordering, Pinout, Packaging, or Electrical Specification information, refer to the PSoC data sheet. For the
most current technical reference manual information, refer to the addendum. To obtain the newest product documentation, go
to the Cypress web site at http://www.cypress.com/psoc. This section encompasses the following chapter:
■Pin Information on page 25
Document Organization
This manual is organized into sections and chapters, according to PSoC functionality. Each section begins with documenta-
tion interpretation, a top-level architectural explanation, PSoC device distinctions (if relevant), and a register summary (if
applicable). Most chapters within the sections have an introduction, an architectural/application description, PSoC device dis-
tinctions (if relevant), register definitions, and timing diagrams. The sections are as follows:
■Overview – Presents the PSoC top-level architecture, PSoC device characteristics and distinctions, how to get started
with helpful information, and document history and conventions. The PSoC device pinouts are detailed in the Pin
Information chapter on page 25.
■PSoC Core – Describes the heart of the PSoC device in various chapters, beginning with an architectural overview and a
summary list of registers pertaining to the PSoC core. See “PSoC Core” on page 31.
■Register Reference – Lists all PSoC device registers in Register Mapping Tables, on page 43, and presents bit-level
detail of each PSoC register in its own Register Details chapter on page 47. Where applicable, detailed register descrip-
tions are also located in each chapter.
■Digital System – Describes the configurable PSoC digital system in various chapters, beginning with an architectural
overview and a summary list of registers pertaining to the digital system. See the “Digital System” on page 161.
■Analog System – Describes the configurable PSoC analog system in various chapters, beginning with an architectural
overview and a summary list of registers pertaining to the analog system. See the “Analog System” on page 215.
■System Resources – Presents additional PSoC system resources, depending on the PSoC device, beginning with an
overview and a summary list of registers pertaining to system resources. See “System Resources” on page 271.
■Glossary – Defines the specialized terminology used in this manual. Glossary terms are presented in bold, italic font
throughout this manual. See the “Glossary” on page 321.
■Index – Lists the location of key topics and elements that constitute and empower the PSoC device. See the “Index” on
page 401.

18 Document # 001-20559 Rev. *D
Section A: Overview
Top-Level Architecture
The PSoC block diagram on the next page illustrates the
top-level architecture of the PSoC device. Each major
grouping in the diagram is covered in this manual in its own
section: PSoC Core, Digital System, Analog System, and
the System Resources. Banding these four main areas
together is the communication network of the system bus.
PSoC Core
The PSoC Core is a powerful engine that supports a rich
instruction set. It encompasses the SRAM for data storage,
an interrupt controller for easy program execution to new
addresses, sleep and watchdog timers, and multiple clock
sources that include the phase locked loop (PLL), IMO
(internal main oscillator), ILO (internal low speed oscillator),
and ECO (32.768 kHz external crystal oscillator) for preci-
sion, programmable clocking. The clocks, together with pro-
grammable clock dividers (as a System Resource), provide
the flexibility to integrate almost any timing requirement into
the PSoC device.
The CPU core, called the M8C, is a powerful processor with
speeds up to 24 MHz. The M8C is a four MIPS 8-bit Har-
vard architecture microprocessor. Within the CPU core are
the SROM and Flash memory components that provide
flexible programming.
PSoC GPIOs provide connection to the CPU, digital and
analog resources of the device. Each pin’s drive mode may
be selected from eight options, allowing great flexibility in
external interfacing. Every pin also has the capability to gen-
erate a system interrupt on high level, low level, and change
from last read.
Digital System
The Digital System is composed of digital rows in a block
array, and the Global, Array, and Row Digital Interconnects
(GDI, ADI, and RDI, respectively).The digital system block is
composed of 4 digital PSoC blocks. Each block is an 8-bit
resource that can be used alone or combined with other
blocks to form 8-, 16-, 24-, and 32-bit peripherals, which are
called user modules.
The digital blocks can be connected to any GPIO through a
series of global buses that can route any signal to any pin.
The buses also allow for signal multiplexing and for perform-
ing logic operations. This configurability frees your designs
from the constraints of a fixed peripheral controller.
Analog System
The Analog System is composed of analog columns in a
block array, analog references, analog input muxing, and
analog drivers. The analog system block is composed of 6
configurable blocks, each comprised of an opamp circuit
allowing the creation of complex analog signal flows.
Analog blocks are arranged in a column of three, which
includes one CT (Continuous Time) and two SC (Switched
Capacitor) blocks. The Analog Column 0 contains the SAR8
ADC block rather than the standard SC blocks.
System Resources
The System Resources provide additional PSoC capability.
These system resources include:
■Digital clocks to increase the flexibility of the PSoC
device.
■One multiply accumulate (MAC) provides a fast 8-bit
multiplier with 32-bit accumulate to assist in both general
math as well as digital filters.
■The decimator provides a custom hardware filter for digi-
tal signal processing applications, including the creation
of Delta Sigma ADCs.
■I2C functionality for implementing either I2C slave or
master.
■Low Voltage Detection (LVD) interrupts can signal the
application of falling voltage levels, while the advanced
POR (Power On Reset) circuit eliminates the need for a
system supervisor.
■An internal voltage reference that provides an absolute
value of 1.3 V to a variety of PSoC subsystems.
■Various system resets supported by the M8C.

Document # 001-20559 Rev. *D 19
Section A: Overview
PSoC Top-Level Block Diagram
DIGITAL SYSTEM
SRAM
256 Bytes
Interrupt
Controller
Sleep and
Watchdog
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
Global Digital Interconnect Global Analog Interconnect
PSoC CORE
CPU Core (M8C)
SROM Flash 8K
Multiply
Accum.
(MAC)
Internal
Voltage
Ref.
Digital
Clocks POR and LVD System Resets
Decimator
SYSTEM RESOURCES
ANALOG SYSTEM
Analog
Ref
I2C
Port 2 Port 1 Port 0 Analog
Drivers
System Bus
Analog
Block Array
Digital PSoC
Block Array
DBB0
1
DBB0
0DCB02 DCB03 SAR8
ADC
SC
SC
CT
Analog
Input
Muxing
1 Digital Row 2 Analog Columns
Port 3
CT

20 Document # 001-20559 Rev. *D
Section A: Overview
PSoC Device Characteristics
The PSoC digital system has 1 digital row and the analog
system has 2 analog columns, as described in the following
table.
The following table lists the resources available for
CY8C24633, CY8C24533, CY8C23533, CY8C23433-spe-
cific PSoC device groups. The check mark or appropriate
information denotes that a system resource is available for
the PSoC device. Blank fields denote that the system
resource is not available. These resources are detailed in
the section titled “System Resources” on page 271.
PSoC Device Distinctions
The PSoC device distinctions are listed in the table below and in each chapter section where it is appropriate. The PSoC
device distinctions are significant exceptions or differences between PSoC groups and devices.
PSoC Device Characteristics
PSoC Part
Number
Digital IO (max)
Digital Rows
Digital Blocks
Analog Inputs
Analog Outputs
Analog Columns
Analog Blocks
Amount of SRAM
Amount of Flash
CY8C24423A 24 1 4 12 2 2 6 256 Bytes 4 KB
CY8C24533 26 1 4 12 2 2 4a
a. 2 CT, 2 SC.
256 Bytes 8 KB
CY8C23533 26 1 4 12 2 2 4a256 Bytes 8 KB
CY8C23433 26 1 4 12 2 2 4a256 Bytes 8 KB
CY8C24633 25 1 4 12 2 2 4a256 Bytes 8 KB
Availability of System Resources for PSoC Devices
PSoC Part
Number
Digital
Clocks
I2C
Internal
Voltage Ref
POR and
LVD
System
Resets
Decimator
Multiply
Accumulate
SAR8 ADC
XRES Pin
CY8C24423A     T1 1
CY8C24533     T1 1 
CY8C23533     T1 1 
CY8C23433     T1 1 
CY8C24633     T1 1 
PSoC Device Distinctions
Device Distinctions Devices Affected Described in Chapter
Low Power Oscillator Capability The slow IMO (SLIMO) bit is available to
enable SYSCLK operation at 6 MHz and 12 MHz, instead of only 24 MHz.
The SLIMO bit is located in the CPU_SCR1 register on page 121.
CY8C24x23A
CY8C24633CY8C24533,
CY8C23533, CY8C23433
Internal Main Oscillator (IMO) chapter
on page 15.
POR and LVD Trip Levels The lowest POR level is set for 2.4V operation;
the next lowest is set for 3.0V operation (instead of 3.0V or 4.5V operation). CY8C24x23A CY8C24533, CY8C23533,
CY8C23433CY8C24633
POR and LVD chapter on page 319and
PSoC device data sheets.
Register Distinction CPU_SCR1 register on page 121bit 4 (Slow
IMO mode) is reserved. CY8C24533, CY8C23533,
CY8C23433CY8C24633 Internal Main Oscillator (IMO) chapter
on page 15.
Register Distinction CPU_SCR1 register on page 121 bits 3 and
2 (ECO EXW and ECO EX, respectively) cannot be used. CY8C24533, CY8C23533,
CY8C23433CY8C24633 External Crystal Oscillator
(ECO) chapter on page 21.
Register Distinction DEC_CR1 register on page 111 bit 7 (ECNT)
is only available in devices with a type 1 decimator. CY8C24x23A
CY8C24533, CY8C23533,
CY8C23433CY8C24633
Analog Interface chapter on page 219
and Decimator chapter on page 291.
Register Distinction OSC_GO_EN register on page 148 bit 7 is
reserved. CY8C24533, CY8C23533,
CY8C23433CY8C24633 Digital Clocks chapter on page 275.