Cypress PSoC CY8C24533 Product manual

PSoC® CY8C24533, CY8C23533, CY8C23433 TRM
PSoC®CY8C24533, CY8C23533, CY8C23433
Technical Reference Manual (TRM)
Document # 001-20559 Rev. *D
January 19, 2017
Cypress Semiconductor
198 Champion Court
San Jose, CA 95134-1709
Phone (USA): 800.858.1810
Phone (Intnl.): 408.943.2600
http://www.cypress.com

2Document # 001-20559 Rev. *D
Copyrights
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Document # 001-20559 Rev. *D 3
Contents Overview
Section A: Overview 17
1. Pin Information .................................................................................................................25
Section B: PSoC Core 31
2. CPU Core (M8C) ..............................................................................................................35
3. Supervisory ROM (SROM)...............................................................................................45
4. RAM Paging......................................................................................................................55
5. Interrupt Controller...........................................................................................................61
6. General Purpose IO (GPIO) ............................................................................................69
7. Analog Output Drivers......................................................................................................77
8. Internal Main Oscillator (IMO) .........................................................................................79
9. Internal Low Speed Oscillator (ILO)................................................................................83
10. External Crystal Oscillator (ECO)....................................................................................85
11. Phase-Locked Loop (PLL) ...............................................................................................91
12. Sleep and Watchdog ........................................................................................................95
Section C: Register Reference 107
13. Register Details...............................................................................................................111
Section D: Digital System 225
14. Global Digital Interconnect (GDI)..................................................................................229
15. Array Digital Interconnect (ADI) ....................................................................................233
16. Row Digital Interconnect (RDI)......................................................................................235
17. Digital Blocks..................................................................................................................241
Section E: Analog System 279
18. Analog Interface .............................................................................................................283
19. Analog Array...................................................................................................................297
20. Analog Input Configuration............................................................................................305
21. Analog Reference...........................................................................................................309
22. Continuous Time PSoC Block........................................................................................313
23. Switched Capacitor PSoC Block ...................................................................................319
24. SAR8 ADC PSoC Block .................................................................................................329
Section F: System Resources 335
25. Digital Clocks..................................................................................................................339
26. Multiply Accumulate (MAC) ...........................................................................................349
27. Decimator........................................................................................................................355
28. I2C...................................................................................................................................359
29. Internal Voltage Reference ............................................................................................375
30. System Resets................................................................................................................377
31. POR and LVD .................................................................................................................383

Contents Overview
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Section G: Glossary 385
Index 401

Document # 001-20559 Rev. *D 5
Contents
Section A: Overview 17
Document Organization ......................................................................................................................17
Top-Level Architecture ........................................................................................................................18
PSoC Core ................................................................................................................................18
Digital System ............................................................................................................................18
Analog System ..........................................................................................................................18
System Resources ....................................................................................................................18
PSoC Device Characteristics ..............................................................................................................20
PSoC Device Distinctions ...................................................................................................................20
Getting Started ...................................................................................................................................21
Support ......................................................................................................................................21
Product Upgrades ......................................................................................................................21
Development Kits .....................................................................................................................21
Document History ................................................................................................................................21
Documentation Conventions ..............................................................................................................22
Register Conventions ..............................................................................................................22
Numeric Naming .......................................................................................................................22
Units of Measure ....................................................................................................................22
Acronyms ..................................................................................................................................23
1. Pin Information..................................................................................................................25
1.1 Pinouts .......................................................................................................................................25
1.1.1 28-Pin Part Pinout.......................................................................................................26
1.1.2 32-Pin Part Pinout.......................................................................................................28
1.1.3 56-Pin Part Pinout.......................................................................................................29
Section B: PSoC Core 31
Top-Level Core Architecture ................................................................................................................31
Interpreting Core Documentation .........................................................................................................31
Core Register Summary ......................................................................................................................32
2. CPU Core (M8C).................................................................................................................35
2.1 Overview ....................................................................................................................................35
2.2 Internal Registers ....................................................................................................................35
2.3 Address Spaces .......................................................................................................................35
2.4 Instruction Set Summary ............................................................................................................36
2.5 Instruction Formats ...................................................................................................................38
2.5.1 One-Byte Instructions..................................................................................................38
2.5.2 Two-Byte Instructions..................................................................................................38
2.5.3 Three-Byte Instructions...............................................................................................39
2.6 Addressing Modes ....................................................................................................................39
2.6.1 Source Immediate.......................................................................................................39
2.6.2 Source Direct ..............................................................................................................40
2.6.3 Source Indexed...........................................................................................................40

Contents Overview
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2.6.4 Destination Direct .......................................................................................................41
2.6.5 Destination Indexed ...................................................................................................41
2.6.6 Destination Direct Source Immediate .........................................................................41
2.6.7 Destination Indexed Source Immediate......................................................................42
2.6.8 Destination Direct Source Direct.................................................................................42
2.6.9 Source Indirect Post Increment ..................................................................................43
2.6.10 Destination Indirect Post Increment............................................................................43
2.7 Register Definitions ...................................................................................................................44
2.7.1 CPU_F Register .........................................................................................................44
3. Supervisory ROM (SROM)................................................................................................. 45
3.1 Architectural Description ...........................................................................................................45
3.1.1 Additional SROM Feature...........................................................................................46
3.1.2 SROM Function Descriptions ....................................................................................46
3.1.2.1 SWBootReset Function ............................................................................46
3.1.2.2 ReadBlock Function..................................................................................47
3.1.2.3 WriteBlock Function..................................................................................48
3.1.2.4 EraseBlock Function.................................................................................48
3.1.2.5 ProtectBlock Function...............................................................................49
3.1.2.6 TableRead Function ................................................................................49
3.1.2.7 EraseAll Function......................................................................................49
3.1.2.8 Checksum Function..................................................................................50
3.1.2.9 Calibrate0 Function...................................................................................50
3.1.2.10 Calibrate1 Function...................................................................................50
3.2 Register Definitions ..................................................................................................................51
3.2.1 CPU_SCR1 Register .................................................................................................51
3.2.2 FLS_PR1 Register .....................................................................................................52
3.3 Clocking ....................................................................................................................................53
3.3.1 DELAY Parameter.......................................................................................................53
3.3.2 CLOCK Parameter......................................................................................................53
4. RAM Paging ...................................................................................................................... 55
4.1 Architectural Description ...........................................................................................................55
4.1.1 Basic Paging ..............................................................................................................55
4.1.2 Stack Operations .......................................................................................................56
4.1.3 Interrupts ....................................................................................................................56
4.1.4 MVI Instructions .........................................................................................................56
4.1.5 Current Page Pointer .................................................................................................56
4.1.6 Index Memory Page Pointer ......................................................................................57
4.2 Register Definitions ...................................................................................................................58
4.2.1 TMP_DRx Registers ..................................................................................................58
4.2.2 CPU_F Register..........................................................................................................59
5. Interrupt Controller........................................................................................................... 61
5.1 Architectural Description ............................................................................................................61
5.1.1 Posted versus Pending Interrupts...............................................................................62
5.2 Application Description ..............................................................................................................63
5.3 Register Definitions ...................................................................................................................64
5.3.1 INT_CLRx Registers ..................................................................................................64
5.3.1.1 INT_CLR0 Register ..................................................................................64
5.3.1.2 INT_CLR1 Register ..................................................................................65
5.3.1.3 INT_CLR3 Register ..................................................................................65
5.3.2 INT_MSKx Registers .................................................................................................65
5.3.2.1 INT_MSK3 Register..................................................................................65

Document # 001-20559 Rev. *D 7
Contents Overview
5.3.2.2 INT_MSK0 Register..................................................................................66
5.3.2.3 INT_MSK1 Register..................................................................................66
5.3.3 INT_VC Register ........................................................................................................66
5.3.4 CPU_F Register .........................................................................................................67
6. General Purpose IO (GPIO) ...............................................................................................69
6.1 Architectural Description.............................................................................................................69
6.1.1 Digital IO ....................................................................................................................69
6.1.2 Global IO ....................................................................................................................70
6.1.3 Analog Input ...............................................................................................................70
6.1.4 GPIO Block Interrupts ...............................................................................................71
6.2 Register Definitions ...................................................................................................................72
6.2.1 PRTxDR Registers .....................................................................................................72
6.2.2 PRTxIE Registers .......................................................................................................72
6.2.3 PRTxGS Registers .....................................................................................................73
6.2.4 PRTxDMx Registers ................................................................................................74
6.2.5 PRTxICx Registers ...................................................................................................75
7. Analog Output Drivers ......................................................................................................77
7.1 Architectural Description ............................................................................................................77
7.2 Register Definitions ..................................................................................................................78
7.2.1 ABF_CR0 Register .....................................................................................................78
8. Internal Main Oscillator (IMO) ...........................................................................................79
8.1 Architectural Description.............................................................................................................79
8.2 Application Description...............................................................................................................79
8.2.1 Trimming the IMO .......................................................................................................79
8.3 Register Definitions ...................................................................................................................80
8.3.1 CPU_SCR1 Register ..................................................................................................80
8.3.2 OSC_CR2 Register ....................................................................................................81
8.3.3 IMO_TR Register .......................................................................................................81
9. Internal Low Speed Oscillator (ILO)..................................................................................83
9.1 Architectural Description.............................................................................................................83
9.2 Register Definitions ...................................................................................................................83
9.2.1 ILO_TR Register ........................................................................................................83
10. External Crystal Oscillator (ECO) .....................................................................................85
10.1 Architectural Description.............................................................................................................85
10.1.1 ECO External Components.........................................................................................86
10.2 PSoC Device Distinctions...........................................................................................................86
10.3 Register Definitions ...................................................................................................................87
10.3.1 CPU_SCR1 Register .................................................................................................87
10.3.2 OSC_CR0 Register ....................................................................................................88
10.3.3 ECO_TR Register ......................................................................................................89
11. Phase-Locked Loop (PLL).................................................................................................91
11.1 Architectural Description.............................................................................................................91
11.2 Register Definitions ..................................................................................................................91
11.2.1 OSC_CR0 Register.....................................................................................................92
11.2.2 OSC_CR2 Register ....................................................................................................93
12. Sleep and Watchdog..........................................................................................................95
12.1 Architectural Description.............................................................................................................95
12.1.1 32 kHz Clock Selection ..............................................................................................95

Contents Overview
8Document # 001-20559 Rev. *D
12.1.2 Sleep Timer ..............................................................................................................95
12.2 Application Description...............................................................................................................96
12.3 Register Definitions ...................................................................................................................97
12.3.1 INT_MSK0 Register ...................................................................................................97
12.3.2 RES_WDT Register ...................................................................................................97
12.3.3 CPU_SCR1 Register ................................................................................................98
12.3.4 CPU_SCR0 Register .................................................................................................99
12.3.5 OSC_CR0 Register .................................................................................................100
12.3.6 ILO_TR Register ......................................................................................................101
12.3.7 ECO_TR Register ....................................................................................................101
12.4 Timing Diagrams......................................................................................................................102
12.4.1 Sleep Sequence .......................................................................................................102
12.4.2 Wake Up Sequence..................................................................................................103
12.4.3 Bandgap Refresh......................................................................................................104
12.4.4 Watchdog Timer........................................................................................................104
12.5 Power Consumption.................................................................................................................105
Section C: Register Reference 107
Register General Conventions ...........................................................................................................107
Register Naming Conventions ...........................................................................................................107
Register Mapping Tables ...................................................................................................................107
Register Map Bank 0 Table: User Space .............................................................................108
Register Map Bank 1 Table: Configuration Space ...............................................................109
13. Register Details................................................................................................................111
13.1 Maneuvering Around the Registers..........................................................................................111
Register Conventions ............................................................................................................112
13.1.1 Register Naming Conventions .................................................................................112
13.2 Bank 0 Registers .....................................................................................................................113
13.2.1 PRTxDR ...................................................................................................................113
13.2.2 PRTxIE ....................................................................................................................114
13.2.3 PRTxGS ...................................................................................................................115
13.2.4 PRTxDM2 ................................................................................................................116
13.2.5 DxBxxDR0 ...............................................................................................................117
13.2.6 DxBxxDR1 ...............................................................................................................118
13.2.7 DxBxxDR2 ...............................................................................................................119
13.2.8 DxBxxCR0 (Timer Control) ......................................................................................120
13.2.9 DxBxxCR0 (Counter Control) ..................................................................................121
13.2.10 DxBxxCR0 (Dead Band Control) ............................................................................122
13.2.11 DxBxxCR0 (CRCPRS Control) ................................................................................123
13.2.12 DCBxxCR0 (SPIM Control) ......................................................................................124
13.2.13 DCBxxCR0 (SPIS Control) ......................................................................................125
13.2.14 DCBxxCR0 (UART Transmitter Control) .................................................................126
13.2.15 DCBxxCR0 (UART Receiver Control) .....................................................................127
13.2.16 AMX_IN ...................................................................................................................128
13.2.17 ARF_CR ..................................................................................................................129
13.2.18 CMP_CR0 ................................................................................................................130
13.2.19 ASY_CR ..................................................................................................................131
13.2.20 CMP_CR1 ................................................................................................................132
13.2.21 SARADC_DL ...........................................................................................................133
13.2.22 SARADC_CR0 .........................................................................................................134
13.2.23 SARADC_CR1 .........................................................................................................135
13.2.24 TMP_DRx ................................................................................................................136

Document # 001-20559 Rev. *D 9
Contents Overview
13.2.25 ACBxxCR3 ...............................................................................................................137
13.2.26 ACBxxCR0 ...............................................................................................................138
13.2.27 ACBxxCR1 ...............................................................................................................140
13.2.28 ACBxxCR2 ...............................................................................................................142
13.2.29 ASDxxCR0 ...............................................................................................................143
13.2.30 ASDxxCR1 ...............................................................................................................144
13.2.31 ASDxxCR2 ...............................................................................................................145
13.2.32 ASDxxCR3 ...............................................................................................................146
13.2.33 ASCxxCR0 ...............................................................................................................147
13.2.34 ASCxxCR1 ...............................................................................................................148
13.2.35 ASCxxCR2 ...............................................................................................................149
13.2.36 ASCxxCR3 ...............................................................................................................150
13.2.37 RDIxRI ......................................................................................................................151
13.2.38 RDIxSYN ..................................................................................................................152
13.2.39 RDIxIS ......................................................................................................................153
13.2.40 RDIxLT0 ...................................................................................................................154
13.2.41 RDIxLT1 ...................................................................................................................155
13.2.42 RDIxRO0 ..................................................................................................................156
13.2.43 RDIxRO1 ..................................................................................................................157
13.2.44 I2C_CFG ..................................................................................................................158
13.2.45 I2C_SCR ..................................................................................................................159
13.2.46 I2C_DR ....................................................................................................................161
13.2.47 I2C_MSCR ...............................................................................................................162
13.2.48 INT_CLR0 ................................................................................................................163
13.2.49 INT_CLR1 ................................................................................................................165
13.2.50 INT_CLR3 ................................................................................................................166
13.2.51 INT_MSK3 ................................................................................................................167
13.2.52 INT_MSK0 ................................................................................................................168
13.2.53 INT_MSK1 ................................................................................................................169
13.2.54 INT_VC ....................................................................................................................170
13.2.55 RES_WDT ................................................................................................................171
13.2.56 DEC_DH ..................................................................................................................172
13.2.57 DEC_DL ..................................................................................................................173
13.2.58 DEC_CR0 ...............................................................................................................174
13.2.59 DEC_CR1 ................................................................................................................175
13.2.60 MULx_X ...................................................................................................................176
13.2.61 MULx_Y ...................................................................................................................177
13.2.62 MULx_DH .................................................................................................................178
13.2.63 MULx_DL .................................................................................................................179
13.2.64 MACx_X/ACCx_DR1 ...............................................................................................180
13.2.65 MACx_Y/ACCx_DR0 ...............................................................................................181
13.2.66 MACx_CL0/ACCx_DR3 ...........................................................................................182
13.2.67 MACx_CL1/ACCx_DR2 ...........................................................................................183
13.2.68 CPU_F ................................................................................................................184
13.2.69 CPU_SCR1 .........................................................................................................185
13.2.70 CPU_SCR0 ..............................................................................................................186
13.3 Bank 1 Registers .....................................................................................................................187
13.3.1 PRTxDM0 .................................................................................................................187
13.3.2 PRTxDM1 .................................................................................................................188
13.3.3 PRTxIC0 ...................................................................................................................189
13.3.4 PRTxIC1 ...................................................................................................................190
13.3.5 DxBxxFN ..................................................................................................................191
13.3.6 DxBxxIN ...................................................................................................................193

Contents Overview
10 Document # 001-20559 Rev. *D
13.3.7 DxBxxOU .................................................................................................................195
13.3.8 CLK_CR0 .................................................................................................................197
13.3.9 CLK_CR1 .................................................................................................................198
13.3.10 ABF_CR0 .............................................................................................................199
13.3.11 AMD_CR0 ................................................................................................................200
13.3.12 AMD_CR1 ................................................................................................................201
13.3.13 ALT_CR0 .................................................................................................................202
13.3.14 SARADC_TRS .........................................................................................................203
13.3.15 SARADC_TRCL ......................................................................................................204
13.3.16 SARADC_TRCH ......................................................................................................205
13.3.17 SARADC_CR2 .........................................................................................................206
13.3.18 SARADC_LCR .........................................................................................................207
13.3.19 GDI_O_IN ................................................................................................................208
13.3.20 GDI_E_IN ................................................................................................................209
13.3.21 GDI_O_OU ..............................................................................................................210
13.3.22 GDI_E_OU ...............................................................................................................211
13.3.23 OSC_GO_EN ..........................................................................................................212
13.3.24 OSC_CR4 ................................................................................................................213
13.3.25 OSC_CR3 ................................................................................................................214
13.3.26 OSC_CR0 ............................................................................................................215
13.3.27 OSC_CR1 ................................................................................................................216
13.3.28 OSC_CR2 ...............................................................................................................217
13.3.29 VLT_CR ...................................................................................................................218
13.3.30 VLT_CMP ................................................................................................................219
13.3.31 IMO_TR ...................................................................................................................220
13.3.32 ILO_TR ....................................................................................................................221
13.3.33 BDG_TR .................................................................................................................222
13.3.34 ECO_TR ..................................................................................................................223
13.3.35 FLS_PR1 ................................................................................................................224
Section D: Digital System 225
Top-Level Digital Architecture ...........................................................................................................225
Interpreting the Digital Documentation .............................................................................................225
Digital Register Summary .................................................................................................................226
14. Global Digital Interconnect (GDI).................................................................................... 229
14.1 Architectural Description .........................................................................................................229
14.1.1 28-Pin Global Interconnect .....................................................................................230
14.2 Register Definitions .................................................................................................................231
14.2.1 GDI_x_IN Registers ...............................................................................................231
14.2.2 GDI_x_OU Registers ...............................................................................................232
15. Array Digital Interconnect (ADI) ..................................................................................... 233
15.1 Architectural Description ..........................................................................................................233
16. Row Digital Interconnect (RDI) ....................................................................................... 235
16.1 Architectural Description ..........................................................................................................235
16.2 Register Definitions .................................................................................................................237
16.2.1 RDIxRI Register .......................................................................................................237
16.2.2 RDIxSYN Register ...................................................................................................237
16.2.3 RDIxIS Register .......................................................................................................238
16.2.4 RDIxLTx Registers .................................................................................................239
16.2.5 RDIxROx Registers ...............................................................................................240
16.2.5.1 RDIxRO0 Register..................................................................................240