Cypress CYW43455 User manual

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CYW43455
Single-Chip 5G WiFi IEEE 802.11n/ac MAC/
Baseband/ Radio with Integrated Bluetooth 5.0
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 002-15051 Rev. *O Revised March 22, 2019
The Cypress CYW43455 single-chip device provides the highest level of integration for Internet of Things applications and handheld
wireless system with integrated single-stream IEEE 802.11ac MAC/baseband/radio and, Bluetooth 5.0.
In IEEE 802.11ac mode, the WLAN operation supports rates of MCS0–MCS9 (up to 256 QAM) in 20 MHz, 40 MHz, and 80 MHz
channels for data rates of up to 433.3 Mbps. All rates specified in the IEEE 802.11a/b/g/n are supported. Included on-chip are 2.4 GHz
and 5 GHz transmit amplifiers and receive low-noise amplifiers. Optional external PAs and LNAs are also supported.
The WLAN section supports the following host interface options: an SDIO v3.0 interface that can operate in 4b or 1b mode, a
high-speed 4-wire UART, and a PCIe1Gen1 (3.0 compliant) interface. The Bluetooth section supports a high-speed 4-wire UART
interface.
Using advanced design techniques and process technology to reduce active and idle power, the CYW43455 is designed to address
the needs of mobile devices that require minimal power consumption and compact size. It includes a power management unit which
simplifies the system power topology and allows for direct operation from a mobile platform battery while maximizing battery life.
The CYW43455 implements highly sophisticated enhanced collaborative coexistence hardware mechanisms and algorithms, which
ensure that WLAN and Bluetooth collaboration is optimized for maximum performance. In addition, coexistence support for external
radios (such as LTE cellular and GPS) is provided via an external interface. As a result, enhanced overall quality for simultaneous
voice, video, and data transmission on a handheld system is achieved.
Cypress Part Numbering Scheme
Cypress is converting the acquired IoT part numbers from Broadcom to the Cypress part numbering scheme. Due to this conversion,
there is no change in form, fit, or function as a result of offering the device with Cypress part number marking. The table provides
Cypress ordering part number that matches an existing IoT part number.
Table 1. Mapping Table for Part Number between Broadcom and Cypress
Features
IEEE 802.11x Key Features
■IEEE 802.11ac compliant.
■Support for TurboQAM® (MCS0–MCS8 86 Mbps and MCS0–
MCS9 96 Mbps) HT20, 20 MHz channel bandwidth.
■Single-stream spatial multiplexing up to 433.3 Mbps data rate.
■Supports 20, 40, and 80 MHz channels with optional SGI (256
QAM modulation).
■Full IEEE 802.11a/b/g/n legacy compatibility with enhanced
performance.
■Supports explicit IEEE 802.11ac transmit beamforming.
■TX and RX low-density parity check (LDPC) support for
improved range and power efficiency.
■On-chip power amplifiers and low-noise amplifiers for both
bands.
■Support for optional front-end modules (FEM) with external PAs
and LNAs.
■Supports optional integrated T/R switch for 2.4 GHz band.
■Supports RF front-end architecture with a single dual-band
antenna shared between Bluetooth and WLAN for lowest
system cost.
■Shared Bluetooth and WLAN receive signal path eliminates the
need for an external power splitter while maintaining excellent
sensitivity for both Bluetooth and WLAN.
■Internal fractional-n PLL allows support for a wide range of
reference clock frequencies.
■Supports IEEE 802.15.2 external coexistence interface to
optimize bandwidth utilization with other co-located wireless
technologies such as LTE or GPS.
Broadcom Part Number Cypress Part Number
BCM43455 CYW43455
BCM43455XKUBG CYW43455XKUBG
BCM43455HKUBG CYW43455HKUBG
BCM4329 CYW4329
BCM4330 CYW4330
1. The PCIe interface is not brought up on CYW43455 and Cypress's firmware and drivers do not support this interface.

Document Number: 002-15051 Rev. *O Page 2 of 118
CYW43455
■Supports standard SDIO v3.0 (including DDR50 mode at 50
MHz and SDR104 mode at 208 MHz, 4-bit and 1-bit) interfaces.
■Backward compatible with SDIO v2.0 host interfaces.
■PCIe2 mode complies with PCI Express base specification
revision 3.0 compliant Gen1 interface for ×1 lane and power
management base specification.
■Integrated ARMCR4 processor with tightly coupled memory for
complete WLAN subsystem functionality and minimizing the
need to wake-up the applications processor for standard WLAN
functions. This allows for further minimization of power
consumption, while maintaining the ability to field upgrade with
future features. On-chip memory includes 800KB SRAM and
704 KB ROM.
Bluetooth Key Features
■Complies with Bluetooth Core Specification v5.0 with provi-
sions for supporting future specifications.
❐QDID:121361
❐Declaration ID: D040197
■Bluetooth Class 1 or Class 2 transmitter operation.
■Supports extended synchronous connections (eSCO), for
enhanced voice quality by allowing for retransmission of
dropped packets.
■Adaptive frequency hopping (AFH) for reducing radio
frequency interference.
■Interface support, host controller interface (HCI) using a
high-speed UART interface and PCM for audio data.
■Low power consumption improves battery life of handheld
devices.
■Supports multiple simultaneous Advanced Audio Distribution
Profiles (A2DP) for stereo sound.
■Automatic frequency detection for standard crystal and TCXO
values.
General Features
■Supports battery voltage range from 3.0 V to 5.25 V supplies
with internal switching regulator.
■Programmable dynamic power management
■6 Kbit OTP for storing board parameters.
■GPIOs: 15
■140-ball WLBGA package (4.47 mm × 5.27 mm, 0.4 mm pitch).
■Security:
❐WPA and WPA2 (Personal) support for powerful encryption
and authentication
❐AES and TKIP in hardware for faster data encryption and
IEEE 802.11i compatibility
❐Reference WLAN subsystem provides Cisco Compatible Ex-
tensions (CCX, CCX 2.0, CCX 3.0, and CCX 4.0)
❐Reference WLAN subsystem provides Wi-Fi Protected Setup
(WPS)
■Worldwide regulatory support: Global products supported with
worldwide homologated design.
Figure 1. Functional Block Diagram
FEM or
T/R
Switch
VIO VBAT
5 GHz WLAN Tx
5 GHz WLAN Rx
2.4 GHz WLAN Tx
2.4 GHz WLAN/BT Rx
Bluetooth Tx
WLAN
Host I/F
Bluetooth
Host I/F
WL_REG_ON
SDIO
PCIe
BT_REG_ON
UART
BT_DEV_WAKE
BT_HOST_WAKE
CBF
I2S
PCM
COEX
External
Coexistence I/F
FEM or
Optional
T/R
Switch
UART
CYW43455
2
2. The PCIe interface is not brought up on CYW43455 and Cypress's firmware and drivers do not support this interface.

Document Number: 002-15051 Rev. *O Page 3 of 118
CYW43455
Contents
1. CYW43455 Overview......................................... 5
1.1 Overview ............................................................. 5
1.2 Standards Compliance ........................................6
2. Power Supplies and Power Management ....... 7
2.1 Power Supply Topology ...................................... 7
2.2 CYW43455 PMU Features .................................. 7
2.3 WLAN Power Management ............................... 10
2.4 PMU Sequencing ..............................................10
2.5 Power-Off Shutdown ......................................... 11
2.6 Power-Up/Power-Down/Reset Circuits ............. 11
3. Frequency References ................................... 12
3.1 Crystal Interface and Clock Generation ............ 12
3.2 External Frequency Reference ......................... 13
3.3 Frequency Selection .........................................14
3.4 External 32.768 kHz Low-Power Oscillator ....... 15
4. Bluetooth Subsystem Overview .................... 16
4.1 Features ............................................................ 16
4.2 Bluetooth Radio ................................................. 17
5. Bluetooth Baseband Core.............................. 19
5.1 Bluetooth 4.0 Features ......................................19
5.2 Bluetooth 4.2 Features ......................................19
5.3 Bluetooth Low Energy ....................................... 19
5.4 Bluetooth 5.0 ..................................................... 19
5.5 Link Control Layer ............................................. 20
5.6 Test Mode Support ............................................ 20
5.7 Bluetooth Power Management Unit .................. 21
5.8 Adaptive Frequency Hopping ............................ 24
5.9 Advanced Bluetooth/WLAN Coexistence .......... 25
5.10 Fast Connection (Interlaced Page and Inquiry
Scans) ............................................................... 25
6. Microprocessor and Memory Unit for
Bluetooth ......................................................... 26
6.1 RAM, ROM, and Patch Memory ........................ 26
6.2 Reset ................................................................. 26
7. Bluetooth Peripheral Transport Unit............. 27
7.1 SPI Interface ..................................................... 27
7.2 SPI/UART Transport Detection ......................... 27
7.3 PCM Interface ................................................... 27
7.4 UART Interface ................................................. 35
7.5 I2S Interface ...................................................... 36
8. WLAN Global Functions................................. 39
8.1 WLAN CPU and Memory Subsystem ............... 39
8.2 One-Time Programmable Memory .....................39
8.3 GPIO Interface ...................................................39
8.4 External Coexistence Interface ..........................40
8.5 UART Interface ..................................................41
8.6 JTAG/SWD Interface ..........................................41
9. WLAN Host Interfaces .................................... 42
9.1 SDIO v3.0 ...........................................................42
9.2 SDIO Pins ..........................................................42
9.3 PCI Express Interface ........................................44
9.4 Transaction Layer Interface ...............................45
10.Wireless LAN MAC and PHY.......................... 47
10.1 IEEE 802.11ac MAC ..........................................47
10.2 IEEE 802.11ac PHY ...........................................50
11. WLAN Radio Subsystem ............................... 51
11.1 Receiver Path .....................................................51
11.2 Transmit Path .....................................................51
11.3 Calibration ..........................................................51
12.Ball Map and Pin Descriptions ...................... 53
12.1 Ball Map .............................................................53
12.2 Pin List by Pin Number .......................................54
12.3 Pin List by Pin Name ..........................................56
12.4 Pin Descriptions .................................................58
12.5 WLAN GPIO Signals and Strapping Options .....63
12.6 I/O States ...........................................................66
13.DC Characteristics.......................................... 70
13.1 Absolute Maximum Ratings ...............................70
13.2 Environmental Ratings .......................................70
13.3 Electrostatic Discharge Specifications ...............70
13.4 Recommended Operating Conditions and DC
Characteristics ...................................................71
14.Bluetooth RF Specifications .......................... 73
15.WLAN RF Specifications................................ 79
15.1 Introduction ........................................................79
15.2 2.4 GHz Band General RF Specifications ..........79
15.3 WLAN 2.4 GHz Receiver Performance
Specifications .....................................................80
15.4 WLAN 2.4 GHz Transmitter Performance
Specifications .....................................................83
15.5 WLAN 5 GHz Receiver Performance
Specifications .....................................................84
15.6 WLAN 5 GHz Transmitter Performance
Specifications .....................................................88

Document Number: 002-15051 Rev. *O Page 4 of 118
CYW43455
15.7 General Spurious Emissions Specifications ...... 89
16.Internal Regulator Electrical Specifications. 94
16.1 Core Buck Switching Regulator ........................ 94
16.2 3.3V LDO (LDO3P3) ......................................... 95
16.3 2.5V LDO (BTLDO2P5) ..................................... 96
16.4 CLDO ................................................................ 97
16.5 LNLDO .............................................................. 98
16.6 PCIe LDO .......................................................... 99
17.System Power Consumption ....................... 100
17.1 WLAN Current Consumption ........................... 100
17.2 Bluetooth Current Consumption ...................... 102
18.Interface Timing and AC Characteristics.... 103
18.1 SDIO Timing .................................................... 103
18.2 SDIO High-Speed Mode Timing ...................... 104
18.3 PCI Express Interface Parameters .................. 110
18.4 JTAG Timing ................................................... 111
18.5 SWD Timing .................................................... 112
19.Power-Up Sequence and Timing................. 113
19.1 Sequencing of Reset and Regulator Control
Signals .............................................................113
20.Package Information .................................... 115
20.1 Package Thermal Characteristics ....................115
20.2 Junction Temperature Estimation and PSIJT
Versus THETAJC ..............................................115
20.3 Environmental Characteristics .........................115
21.Mechanical Information................................ 116
22.Ordering Information.................................... 118
23.Additional Information ................................. 118
23.1 Acronyms and Abbreviations ...........................118
23.2 References .......................................................118
23.3 IoT Resources ..................................................118
Document History Page ............................................... 119
Sales, Solutions, and Legal Information .................... 121

Document Number: 002-15051 Rev. *O Page 5 of 121
CYW43455
1. CYW43455 Overview
1.1 Overview
The Cypress CYW43455 single-chip device provides the highest level of integration for IoT applications handheld wireless systems,
with integrated IEEE 802.1 a/b/g/n/ac MAC/baseband/radio and, Bluetooth 5.0 + EDR (Enhanced Data Rate). It provides a small
form-factor solution with minimal external components to drive down cost for mass volumes and allows for handheld device flexibility
in size, form, and function. Comprehensive power management circuitry and software ensure the system can meet the needs of highly
mobile devices that require minimal power consumption and reliable operation.
Figure 2 shows the interconnect of all the major physical blocks in the CYW43455 and their associated external interfaces, which are
described in greater detail in the following sections5 .
Figure 2. CYW43455 Block Diagram
WLANBT
RX/TX
LCU
BLE
APU
BlueRF
UART
PCM
I2 S
USB
Port Control
GPI O
Timers
WD
Pause
AHB2APB
Registers
DMA
JTAG Master
AHB Bus Matrix
RAM
ROM
ARMCM3
WLAN
Master Slave
Modem
BT RF
NIC-301 AXI Backplane
TCM
RAM 800 KB
ROM 704 KB
AXI2ANB
AHB2AXI
WLAN BT Access
WLAN RAM Sharing
ARMCR4
Chip Common
(OTP) AXI2APB
PCIE
SDIOD
DOT11MAC (D11)GCI Coex I/F
1×1 IEEE 802.11ac PHY (Rev. 4)
Shared LNA
Control and Other
Coex I/F
2.4 GHz/5 GHz
TINY Radio
WL_HOST_WAKE
UART
WL_DEV_WKAE
JTAG
Other GPI Os
SDIO 3.0
PCIE
RF
Switch
Controls
XTAL
32 kHz
External
LPO
BT_HOST_WAKE
BT_DEV_WAKE
UART
USB 1.1
PCM
I2S
Other GPIOs
PMU
VBAT
WL_REG_ON
BT_REG_ON
GCI
SECI UART and GCI GPIOs
BT PA
CLB
Shared
2.4 LNA
2.4 GHz
PA
WLAN:
5GHz:iPA,iLNA,eLG,eTR
2GHz:iPA,iLNA,eLG,iTR
BT:
SharedLNA,iTR eTR
5 GHz
PA
LNA
L
L
Diplexer
LNA
5 GHz
PA Dri ver
3
3. The PCIe interface is not brought up on CYW43455 and Cypress's firmware and drivers do not support this interface.

Document Number: 002-15051 Rev. *O Page 6 of 121
CYW43455
1.2 Standards Compliance
The CYW43455 supports the following standards:
■Bluetooth 2.1 + EDR
■Bluetooth 3.0
■Bluetooth 4.2 (Bluetooth Low Energy)
■Bluetooth 5.0 compliant
■IEEE 802.11ac single-stream mandatory and optional requirements for 20, 40, and 80 MHz channels
■IEEE 802.11n (Handheld Device Class, Section 11)
■IEEE 802.11a
■IEEE 802.11b
■IEEE 802.11g
■IEEE 802.11d
■IEEE 802.11h
■IEEE 802.11i
■Security:
❐WEP
❐WPA Personal
❐WPA2 Personal
❐WMM
❐WMM-PS (U-APSD)
❐WMM-SA
❐AES (hardware accelerator)
❐TKIP (hardware accelerator)
❐CKIP (software support)
■Proprietary protocols:
❐CCXv2
❐CCXv3
❐CCXv4
❐CCXv5
❐WFAEC
■IEEE 802.15.2 Coexistence Compliance (on-silicon solution compliant with IEEE 3-wire requirements)
The CYW43455 supports the following future drafts/standards:
■IEEE 802.11r (fast roaming between APs)
■IEEE 802.11w (secure management frames)
■IEEE 802.11 Extensions:
❐IEEE 802.11e QoS Enhancements (as per the WMM specification is already supported)
❐IEEE 802.11h 5 GHz Extensions
❐IEEE 802.11i MAC Enhancements
❐IEEE 802.11k Radio Resource Measurement

Document Number: 002-15051 Rev. *O Page 7 of 121
CYW43455
2. Power Supplies and Power Management
2.1 Power Supply Topology
One Buck regulator, multiple LDO regulators, and a power management unit (PMU) are integrated into the CYW43455. All regulators
are programmable via the PMU. These blocks simplify power supply design for Bluetooth, and WLAN functions in embedded designs.
A single VBAT (3.0 V to 5.25 V6.0 V DC max.) and VIO supply (1.8 V to 3.3 V) can be used, with all additional voltages being provided
by the regulators in the CYW43455.
Two control signals, BT_REG_ON and WL_REG_ON, are used to power-up the regulators and take the respective section out of
reset. The CBUCK CLDO and LNLDO power-up when any of the reset signals are deasserted. All regulators are powered down only
when both BT_REG_ON and WL_REG_ON are deasserted. The CLDO and LNLDO may be turned off/on based on the dynamic
demands of the digital baseband.
The CYW43455 allows for an extremely low power-consumption mode by completely shutting down the CBUCK, CLDO, and LNLDO
regulators. When in this state, the LPLDO1 (which is the low-power linear regulator that is supplied by the system VIO supply) provides
the CYW43455 with all required voltage, further reducing leakage currents.
2.2 CYW43455 PMU Features
■VBAT to 1.35 Vout (170 mA nominal, 600 mA maximum) Core-Buck (CBUCK) switching regulator
■VBAT to 3.3 Vout (200 mA nominal, 450 mA–850 mA maximum) LDO3P3
■VBAT to 2.5 Vout (15 mA nominal, 70 mA maximum) BTLDO2P5
■1.35 V to 1.2 Vout (100 mA nominal, 150 mA maximum) LNLDO
■1.35 V to 1.2 Vout (80 mA nominal, 200 mA maximum) CLDO with bypass mode for deep-sleep
■1.35 V to 1.2 Vout (35 mA nominal, 55 mA maximum) LDO for PCIE 4
■Additional internal LDOs (not externally accessible)
■PMU internal timer auto-calibration by the crystal clock for precise wake-up timing from extremely low power-consumption mode.
Figure 3 and Figure 4 show the regulators and a typical power topology7.
4. The PCIe interface is not brought up on CYW43455 and Cypress's firmware and drivers do not support this interface.

Document Number: 002-15051 Rev. *O Page 8 of 121
CYW43455
Figure 3. Typical Power (Page 1 of 2)
WLAN/BT/CLB/Top, Always ON
WL Subcore
BT Digital
WL RF – XTAL
BT RF
LNLDO
100 mA
Internal LNLDO
10 mA
Internal VCOLDO
80 mA
Internal LNLDO
80 mA
Internal LNLDO
80 mA
WL RF - LOGEN
WL RF – LNA
WL RF – AFE and TIA
WL RF – TX
CORE BUCK
REGULATOR
CBUCK
Max 600 mA
Avg 170 mA
LPLDO1
3 mA
VBAT
VDDIO 1.1V
1.35V
1.3V- 1.2V- 0.95V
(AVS)
1.2V
1.2V
1.2V
1.2V
2.2 µH
0806
0603
4.7 µF
0402
4.7 µF
0402
2.2 µF
0402
1.2V
WL RF – RFPLL PFD and MMD
XTAL LDO
30 mA
1.2V
1 µF
0402
PCIE PLL, RXTX
WL_REG_ON
BT_REG_ON
WL BBPLL/DFLL
WL VDDM (SRAMs + AOS)
WL PHY
WL OTP
BT VDDM
CLDO
Max 200 mA
Avg 80 mA
(bypass in
deep sleep)
PCIe LDO
Max 55 mA
Avg 35 mA
(bypass/off in
deepsleep) 0.47 µF
0201
1.2V
Internal LNLDO
10 mA WL RF – ADC REF
1.2V
WL RF - TX MIXER and PA (not all versions)
GND
0.1
µF
0201
Shaded areas are internal to the device.
No power switch
Power switch
CYW43455
5
5. The PCIe interface is not brought up on CYW43455 and Cypress's firmware and drivers do not support this interface.

Document Number: 002-15051 Rev. *O Page 9 of 121
CYW43455
Figure 4. Typical Power Topology (Page 2 of 2)
2.5V Internal LNLDO
8 mA WL RF – CP
BTLDO2P5
Max 70 mA
Avg 15 mA
BT CLASS 1 PA
LDO3P3
Spike 800 mA
Max 450 mA
Avg 200 mA
WL RF – PAD (2.4 GHz, 5 GHz)
WL OTP 3.3V
VDDIO_RF
VBAT 3.3V
4.7 µF
0402
2.5V
WL RF – PA (2.4 GHz, 5 GHz)
WL RF – VCO
2.5V Internal LNLDO
25 mA
2.5V
2.2 µF
0402
2.5V Internal LNLDO
10 mA WL RF – RX, TX, NMOS miniPMU LDOs
2.5V
10 pF
0201
2.5V
Shaded areas are internal to the device.
No power switch
Power switch No dedicated power switch, but
internal power-down modes and
block-specific power switches.
CYW43455