Cypress CYW43455 User manual

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CYW43455
Single-Chip 5G WiFi IEEE 802.11n/ac MAC/
Baseband/ Radio with Integrated Bluetooth 5.0
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 002-15051 Rev. *O Revised March 22, 2019
The Cypress CYW43455 single-chip device provides the highest level of integration for Internet of Things applications and handheld
wireless system with integrated single-stream IEEE 802.11ac MAC/baseband/radio and, Bluetooth 5.0.
In IEEE 802.11ac mode, the WLAN operation supports rates of MCS0–MCS9 (up to 256 QAM) in 20 MHz, 40 MHz, and 80 MHz
channels for data rates of up to 433.3 Mbps. All rates specified in the IEEE 802.11a/b/g/n are supported. Included on-chip are 2.4 GHz
and 5 GHz transmit amplifiers and receive low-noise amplifiers. Optional external PAs and LNAs are also supported.
The WLAN section supports the following host interface options: an SDIO v3.0 interface that can operate in 4b or 1b mode, a
high-speed 4-wire UART, and a PCIe1Gen1 (3.0 compliant) interface. The Bluetooth section supports a high-speed 4-wire UART
interface.
Using advanced design techniques and process technology to reduce active and idle power, the CYW43455 is designed to address
the needs of mobile devices that require minimal power consumption and compact size. It includes a power management unit which
simplifies the system power topology and allows for direct operation from a mobile platform battery while maximizing battery life.
The CYW43455 implements highly sophisticated enhanced collaborative coexistence hardware mechanisms and algorithms, which
ensure that WLAN and Bluetooth collaboration is optimized for maximum performance. In addition, coexistence support for external
radios (such as LTE cellular and GPS) is provided via an external interface. As a result, enhanced overall quality for simultaneous
voice, video, and data transmission on a handheld system is achieved.
Cypress Part Numbering Scheme
Cypress is converting the acquired IoT part numbers from Broadcom to the Cypress part numbering scheme. Due to this conversion,
there is no change in form, fit, or function as a result of offering the device with Cypress part number marking. The table provides
Cypress ordering part number that matches an existing IoT part number.
Table 1. Mapping Table for Part Number between Broadcom and Cypress
Features
IEEE 802.11x Key Features
■IEEE 802.11ac compliant.
■Support for TurboQAM® (MCS0–MCS8 86 Mbps and MCS0–
MCS9 96 Mbps) HT20, 20 MHz channel bandwidth.
■Single-stream spatial multiplexing up to 433.3 Mbps data rate.
■Supports 20, 40, and 80 MHz channels with optional SGI (256
QAM modulation).
■Full IEEE 802.11a/b/g/n legacy compatibility with enhanced
performance.
■Supports explicit IEEE 802.11ac transmit beamforming.
■TX and RX low-density parity check (LDPC) support for
improved range and power efficiency.
■On-chip power amplifiers and low-noise amplifiers for both
bands.
■Support for optional front-end modules (FEM) with external PAs
and LNAs.
■Supports optional integrated T/R switch for 2.4 GHz band.
■Supports RF front-end architecture with a single dual-band
antenna shared between Bluetooth and WLAN for lowest
system cost.
■Shared Bluetooth and WLAN receive signal path eliminates the
need for an external power splitter while maintaining excellent
sensitivity for both Bluetooth and WLAN.
■Internal fractional-n PLL allows support for a wide range of
reference clock frequencies.
■Supports IEEE 802.15.2 external coexistence interface to
optimize bandwidth utilization with other co-located wireless
technologies such as LTE or GPS.
Broadcom Part Number Cypress Part Number
BCM43455 CYW43455
BCM43455XKUBG CYW43455XKUBG
BCM43455HKUBG CYW43455HKUBG
BCM4329 CYW4329
BCM4330 CYW4330
1. The PCIe interface is not brought up on CYW43455 and Cypress's firmware and drivers do not support this interface.

Document Number: 002-15051 Rev. *O Page 2 of 118
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■Supports standard SDIO v3.0 (including DDR50 mode at 50
MHz and SDR104 mode at 208 MHz, 4-bit and 1-bit) interfaces.
■Backward compatible with SDIO v2.0 host interfaces.
■PCIe2 mode complies with PCI Express base specification
revision 3.0 compliant Gen1 interface for ×1 lane and power
management base specification.
■Integrated ARMCR4 processor with tightly coupled memory for
complete WLAN subsystem functionality and minimizing the
need to wake-up the applications processor for standard WLAN
functions. This allows for further minimization of power
consumption, while maintaining the ability to field upgrade with
future features. On-chip memory includes 800KB SRAM and
704 KB ROM.
Bluetooth Key Features
■Complies with Bluetooth Core Specification v5.0 with provi-
sions for supporting future specifications.
❐QDID:121361
❐Declaration ID: D040197
■Bluetooth Class 1 or Class 2 transmitter operation.
■Supports extended synchronous connections (eSCO), for
enhanced voice quality by allowing for retransmission of
dropped packets.
■Adaptive frequency hopping (AFH) for reducing radio
frequency interference.
■Interface support, host controller interface (HCI) using a
high-speed UART interface and PCM for audio data.
■Low power consumption improves battery life of handheld
devices.
■Supports multiple simultaneous Advanced Audio Distribution
Profiles (A2DP) for stereo sound.
■Automatic frequency detection for standard crystal and TCXO
values.
General Features
■Supports battery voltage range from 3.0 V to 5.25 V supplies
with internal switching regulator.
■Programmable dynamic power management
■6 Kbit OTP for storing board parameters.
■GPIOs: 15
■140-ball WLBGA package (4.47 mm × 5.27 mm, 0.4 mm pitch).
■Security:
❐WPA and WPA2 (Personal) support for powerful encryption
and authentication
❐AES and TKIP in hardware for faster data encryption and
IEEE 802.11i compatibility
❐Reference WLAN subsystem provides Cisco Compatible Ex-
tensions (CCX, CCX 2.0, CCX 3.0, and CCX 4.0)
❐Reference WLAN subsystem provides Wi-Fi Protected Setup
(WPS)
■Worldwide regulatory support: Global products supported with
worldwide homologated design.
Figure 1. Functional Block Diagram
FEM or
T/R
Switch
VIO VBAT
5 GHz WLAN Tx
5 GHz WLAN Rx
2.4 GHz WLAN Tx
2.4 GHz WLAN/BT Rx
Bluetooth Tx
WLAN
Host I/F
Bluetooth
Host I/F
WL_REG_ON
SDIO
PCIe
BT_REG_ON
UART
BT_DEV_WAKE
BT_HOST_WAKE
CBF
I2S
PCM
COEX
External
Coexistence I/F
FEM or
Optional
T/R
Switch
UART
CYW43455
2
2. The PCIe interface is not brought up on CYW43455 and Cypress's firmware and drivers do not support this interface.

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Contents
1. CYW43455 Overview......................................... 5
1.1 Overview ............................................................. 5
1.2 Standards Compliance ........................................6
2. Power Supplies and Power Management ....... 7
2.1 Power Supply Topology ...................................... 7
2.2 CYW43455 PMU Features .................................. 7
2.3 WLAN Power Management ............................... 10
2.4 PMU Sequencing ..............................................10
2.5 Power-Off Shutdown ......................................... 11
2.6 Power-Up/Power-Down/Reset Circuits ............. 11
3. Frequency References ................................... 12
3.1 Crystal Interface and Clock Generation ............ 12
3.2 External Frequency Reference ......................... 13
3.3 Frequency Selection .........................................14
3.4 External 32.768 kHz Low-Power Oscillator ....... 15
4. Bluetooth Subsystem Overview .................... 16
4.1 Features ............................................................ 16
4.2 Bluetooth Radio ................................................. 17
5. Bluetooth Baseband Core.............................. 19
5.1 Bluetooth 4.0 Features ......................................19
5.2 Bluetooth 4.2 Features ......................................19
5.3 Bluetooth Low Energy ....................................... 19
5.4 Bluetooth 5.0 ..................................................... 19
5.5 Link Control Layer ............................................. 20
5.6 Test Mode Support ............................................ 20
5.7 Bluetooth Power Management Unit .................. 21
5.8 Adaptive Frequency Hopping ............................ 24
5.9 Advanced Bluetooth/WLAN Coexistence .......... 25
5.10 Fast Connection (Interlaced Page and Inquiry
Scans) ............................................................... 25
6. Microprocessor and Memory Unit for
Bluetooth ......................................................... 26
6.1 RAM, ROM, and Patch Memory ........................ 26
6.2 Reset ................................................................. 26
7. Bluetooth Peripheral Transport Unit............. 27
7.1 SPI Interface ..................................................... 27
7.2 SPI/UART Transport Detection ......................... 27
7.3 PCM Interface ................................................... 27
7.4 UART Interface ................................................. 35
7.5 I2S Interface ...................................................... 36
8. WLAN Global Functions................................. 39
8.1 WLAN CPU and Memory Subsystem ............... 39
8.2 One-Time Programmable Memory .....................39
8.3 GPIO Interface ...................................................39
8.4 External Coexistence Interface ..........................40
8.5 UART Interface ..................................................41
8.6 JTAG/SWD Interface ..........................................41
9. WLAN Host Interfaces .................................... 42
9.1 SDIO v3.0 ...........................................................42
9.2 SDIO Pins ..........................................................42
9.3 PCI Express Interface ........................................44
9.4 Transaction Layer Interface ...............................45
10.Wireless LAN MAC and PHY.......................... 47
10.1 IEEE 802.11ac MAC ..........................................47
10.2 IEEE 802.11ac PHY ...........................................50
11. WLAN Radio Subsystem ............................... 51
11.1 Receiver Path .....................................................51
11.2 Transmit Path .....................................................51
11.3 Calibration ..........................................................51
12.Ball Map and Pin Descriptions ...................... 53
12.1 Ball Map .............................................................53
12.2 Pin List by Pin Number .......................................54
12.3 Pin List by Pin Name ..........................................56
12.4 Pin Descriptions .................................................58
12.5 WLAN GPIO Signals and Strapping Options .....63
12.6 I/O States ...........................................................66
13.DC Characteristics.......................................... 70
13.1 Absolute Maximum Ratings ...............................70
13.2 Environmental Ratings .......................................70
13.3 Electrostatic Discharge Specifications ...............70
13.4 Recommended Operating Conditions and DC
Characteristics ...................................................71
14.Bluetooth RF Specifications .......................... 73
15.WLAN RF Specifications................................ 79
15.1 Introduction ........................................................79
15.2 2.4 GHz Band General RF Specifications ..........79
15.3 WLAN 2.4 GHz Receiver Performance
Specifications .....................................................80
15.4 WLAN 2.4 GHz Transmitter Performance
Specifications .....................................................83
15.5 WLAN 5 GHz Receiver Performance
Specifications .....................................................84
15.6 WLAN 5 GHz Transmitter Performance
Specifications .....................................................88

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15.7 General Spurious Emissions Specifications ...... 89
16.Internal Regulator Electrical Specifications. 94
16.1 Core Buck Switching Regulator ........................ 94
16.2 3.3V LDO (LDO3P3) ......................................... 95
16.3 2.5V LDO (BTLDO2P5) ..................................... 96
16.4 CLDO ................................................................ 97
16.5 LNLDO .............................................................. 98
16.6 PCIe LDO .......................................................... 99
17.System Power Consumption ....................... 100
17.1 WLAN Current Consumption ........................... 100
17.2 Bluetooth Current Consumption ...................... 102
18.Interface Timing and AC Characteristics.... 103
18.1 SDIO Timing .................................................... 103
18.2 SDIO High-Speed Mode Timing ...................... 104
18.3 PCI Express Interface Parameters .................. 110
18.4 JTAG Timing ................................................... 111
18.5 SWD Timing .................................................... 112
19.Power-Up Sequence and Timing................. 113
19.1 Sequencing of Reset and Regulator Control
Signals .............................................................113
20.Package Information .................................... 115
20.1 Package Thermal Characteristics ....................115
20.2 Junction Temperature Estimation and PSIJT
Versus THETAJC ..............................................115
20.3 Environmental Characteristics .........................115
21.Mechanical Information................................ 116
22.Ordering Information.................................... 118
23.Additional Information ................................. 118
23.1 Acronyms and Abbreviations ...........................118
23.2 References .......................................................118
23.3 IoT Resources ..................................................118
Document History Page ............................................... 119
Sales, Solutions, and Legal Information .................... 121

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1. CYW43455 Overview
1.1 Overview
The Cypress CYW43455 single-chip device provides the highest level of integration for IoT applications handheld wireless systems,
with integrated IEEE 802.1 a/b/g/n/ac MAC/baseband/radio and, Bluetooth 5.0 + EDR (Enhanced Data Rate). It provides a small
form-factor solution with minimal external components to drive down cost for mass volumes and allows for handheld device flexibility
in size, form, and function. Comprehensive power management circuitry and software ensure the system can meet the needs of highly
mobile devices that require minimal power consumption and reliable operation.
Figure 2 shows the interconnect of all the major physical blocks in the CYW43455 and their associated external interfaces, which are
described in greater detail in the following sections5 .
Figure 2. CYW43455 Block Diagram
WLANBT
RX/TX
LCU
BLE
APU
BlueRF
UART
PCM
I2 S
USB
Port Control
GPI O
Timers
WD
Pause
AHB2APB
Registers
DMA
JTAG Master
AHB Bus Matrix
RAM
ROM
ARMCM3
WLAN
Master Slave
Modem
BT RF
NIC-301 AXI Backplane
TCM
RAM 800 KB
ROM 704 KB
AXI2ANB
AHB2AXI
WLAN BT Access
WLAN RAM Sharing
ARMCR4
Chip Common
(OTP) AXI2APB
PCIE
SDIOD
DOT11MAC (D11)GCI Coex I/F
1×1 IEEE 802.11ac PHY (Rev. 4)
Shared LNA
Control and Other
Coex I/F
2.4 GHz/5 GHz
TINY Radio
WL_HOST_WAKE
UART
WL_DEV_WKAE
JTAG
Other GPI Os
SDIO 3.0
PCIE
RF
Switch
Controls
XTAL
32 kHz
External
LPO
BT_HOST_WAKE
BT_DEV_WAKE
UART
USB 1.1
PCM
I2S
Other GPIOs
PMU
VBAT
WL_REG_ON
BT_REG_ON
GCI
SECI UART and GCI GPIOs
BT PA
CLB
Shared
2.4 LNA
2.4 GHz
PA
WLAN:
5GHz:iPA,iLNA,eLG,eTR
2GHz:iPA,iLNA,eLG,iTR
BT:
SharedLNA,iTR eTR
5 GHz
PA
LNA
L
L
Diplexer
LNA
5 GHz
PA Dri ver
3
3. The PCIe interface is not brought up on CYW43455 and Cypress's firmware and drivers do not support this interface.

Document Number: 002-15051 Rev. *O Page 6 of 121
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1.2 Standards Compliance
The CYW43455 supports the following standards:
■Bluetooth 2.1 + EDR
■Bluetooth 3.0
■Bluetooth 4.2 (Bluetooth Low Energy)
■Bluetooth 5.0 compliant
■IEEE 802.11ac single-stream mandatory and optional requirements for 20, 40, and 80 MHz channels
■IEEE 802.11n (Handheld Device Class, Section 11)
■IEEE 802.11a
■IEEE 802.11b
■IEEE 802.11g
■IEEE 802.11d
■IEEE 802.11h
■IEEE 802.11i
■Security:
❐WEP
❐WPA Personal
❐WPA2 Personal
❐WMM
❐WMM-PS (U-APSD)
❐WMM-SA
❐AES (hardware accelerator)
❐TKIP (hardware accelerator)
❐CKIP (software support)
■Proprietary protocols:
❐CCXv2
❐CCXv3
❐CCXv4
❐CCXv5
❐WFAEC
■IEEE 802.15.2 Coexistence Compliance (on-silicon solution compliant with IEEE 3-wire requirements)
The CYW43455 supports the following future drafts/standards:
■IEEE 802.11r (fast roaming between APs)
■IEEE 802.11w (secure management frames)
■IEEE 802.11 Extensions:
❐IEEE 802.11e QoS Enhancements (as per the WMM specification is already supported)
❐IEEE 802.11h 5 GHz Extensions
❐IEEE 802.11i MAC Enhancements
❐IEEE 802.11k Radio Resource Measurement

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CYW43455
2. Power Supplies and Power Management
2.1 Power Supply Topology
One Buck regulator, multiple LDO regulators, and a power management unit (PMU) are integrated into the CYW43455. All regulators
are programmable via the PMU. These blocks simplify power supply design for Bluetooth, and WLAN functions in embedded designs.
A single VBAT (3.0 V to 5.25 V6.0 V DC max.) and VIO supply (1.8 V to 3.3 V) can be used, with all additional voltages being provided
by the regulators in the CYW43455.
Two control signals, BT_REG_ON and WL_REG_ON, are used to power-up the regulators and take the respective section out of
reset. The CBUCK CLDO and LNLDO power-up when any of the reset signals are deasserted. All regulators are powered down only
when both BT_REG_ON and WL_REG_ON are deasserted. The CLDO and LNLDO may be turned off/on based on the dynamic
demands of the digital baseband.
The CYW43455 allows for an extremely low power-consumption mode by completely shutting down the CBUCK, CLDO, and LNLDO
regulators. When in this state, the LPLDO1 (which is the low-power linear regulator that is supplied by the system VIO supply) provides
the CYW43455 with all required voltage, further reducing leakage currents.
2.2 CYW43455 PMU Features
■VBAT to 1.35 Vout (170 mA nominal, 600 mA maximum) Core-Buck (CBUCK) switching regulator
■VBAT to 3.3 Vout (200 mA nominal, 450 mA–850 mA maximum) LDO3P3
■VBAT to 2.5 Vout (15 mA nominal, 70 mA maximum) BTLDO2P5
■1.35 V to 1.2 Vout (100 mA nominal, 150 mA maximum) LNLDO
■1.35 V to 1.2 Vout (80 mA nominal, 200 mA maximum) CLDO with bypass mode for deep-sleep
■1.35 V to 1.2 Vout (35 mA nominal, 55 mA maximum) LDO for PCIE 4
■Additional internal LDOs (not externally accessible)
■PMU internal timer auto-calibration by the crystal clock for precise wake-up timing from extremely low power-consumption mode.
Figure 3 and Figure 4 show the regulators and a typical power topology7.
4. The PCIe interface is not brought up on CYW43455 and Cypress's firmware and drivers do not support this interface.

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Figure 3. Typical Power (Page 1 of 2)
WLAN/BT/CLB/Top, Always ON
WL Subcore
BT Digital
WL RF – XTAL
BT RF
LNLDO
100 mA
Internal LNLDO
10 mA
Internal VCOLDO
80 mA
Internal LNLDO
80 mA
Internal LNLDO
80 mA
WL RF - LOGEN
WL RF – LNA
WL RF – AFE and TIA
WL RF – TX
CORE BUCK
REGULATOR
CBUCK
Max 600 mA
Avg 170 mA
LPLDO1
3 mA
VBAT
VDDIO 1.1V
1.35V
1.3V- 1.2V- 0.95V
(AVS)
1.2V
1.2V
1.2V
1.2V
2.2 µH
0806
0603
4.7 µF
0402
4.7 µF
0402
2.2 µF
0402
1.2V
WL RF – RFPLL PFD and MMD
XTAL LDO
30 mA
1.2V
1 µF
0402
PCIE PLL, RXTX
WL_REG_ON
BT_REG_ON
WL BBPLL/DFLL
WL VDDM (SRAMs + AOS)
WL PHY
WL OTP
BT VDDM
CLDO
Max 200 mA
Avg 80 mA
(bypass in
deep sleep)
PCIe LDO
Max 55 mA
Avg 35 mA
(bypass/off in
deepsleep) 0.47 µF
0201
1.2V
Internal LNLDO
10 mA WL RF – ADC REF
1.2V
WL RF - TX MIXER and PA (not all versions)
GND
0.1
µF
0201
Shaded areas are internal to the device.
No power switch
Power switch
CYW43455
5
5. The PCIe interface is not brought up on CYW43455 and Cypress's firmware and drivers do not support this interface.

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Figure 4. Typical Power Topology (Page 2 of 2)
2.5V Internal LNLDO
8 mA WL RF – CP
BTLDO2P5
Max 70 mA
Avg 15 mA
BT CLASS 1 PA
LDO3P3
Spike 800 mA
Max 450 mA
Avg 200 mA
WL RF – PAD (2.4 GHz, 5 GHz)
WL OTP 3.3V
VDDIO_RF
VBAT 3.3V
4.7 µF
0402
2.5V
WL RF – PA (2.4 GHz, 5 GHz)
WL RF – VCO
2.5V Internal LNLDO
25 mA
2.5V
2.2 µF
0402
2.5V Internal LNLDO
10 mA WL RF – RX, TX, NMOS miniPMU LDOs
2.5V
10 pF
0201
2.5V
Shaded areas are internal to the device.
No power switch
Power switch No dedicated power switch, but
internal power-down modes and
block-specific power switches.
CYW43455

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2.3 WLAN Power Management
The CYW43455 has been designed with the stringent power consumption requirements of mobile devices in mind. All areas of the
chip design are optimized to minimize power consumption. Silicon processes and cell libraries were chosen to reduce leakage current
and supply voltages. Additionally, the CYW43455 integrated RAM is a high Vt memory with dynamic clock control. The dominant
supply current consumed by the RAM is leakage current only. Additionally, the CYW43455 includes an advanced WLAN power
management unit (PM) sequencer. The PMU sequencer provides significant power savings by putting the CYW43455 into various
power management states appropriate to the current environment and activities that are being performed. The power management
unit enables and disables internal regulators, switches, and other blocks based on a computation of the required resources and a
table that describes the relationship between resources and the time needed to enable and disable them. Power-up sequences are
fully programmable. Configurable, free-running counters (running at 32.768 kHz LPO clock) in the PMU sequencer are used to turn
on/turn off individual regulators and power switches. Clock speeds are dynamically changed (or gated altogether) for the current mode.
Slower clock speeds are used wherever possible.
The CYW43455 WLAN power states are described as follows:
■Active mode— All WLAN blocks in the CYW43455 are powered up and fully functional with active carrier sensing and frame trans-
mission and receiving. All required regulators are enabled and put in the most efficient mode based on the load current. Clock
speeds are dynamically adjusted by the PMU sequencer.
■Doze mode—The radio, analog domains, and most of the linear regulators are powered down. The rest of the CYW43455
remains powered up in an IDLE state. All main clocks (PLL, crystal oscillator or TCXO) are shut down to reduce active power to
the minimum. The 32.768 kHz LPO clock is available only for the PMU sequencer. This condition is necessary to allow the PMU
sequencer to wake-up the chip and transition to Active mode. In Doze mode, the primary power consumed is due to leakage cur-
rent.
■Deep-sleep mode—Most of the chip including both analog and digital domains and most of the regulators are powered off. Logic
states in the digital core are saved and preserved into a retention memory in the always-ON domain before the digital core is pow-
ered off. Upon a wake-up event triggered by the PMU timers, an external interrupt or a host resume through the PCIe6 bus, logic
states in the digital core are restored to their pre-deep-sleep settings to avoid lengthy HW reinitialization.
■Power-down mode—The CYW43455 is effectively powered off by shutting down all internal regulators. The chip is brought out of
this mode by external logic re-enabling the internal regulators.
2.4 PMU Sequencing
The PMU sequencer is used to minimize system power consumption. It enables and disables various system resources based on a
computation of required resources and a table that describes the relationship between resources and the time required to enable and
disable them.
Resource requests may derive from several sources: clock requests from cores, the minimum resources defined in the ResourceMin
register, and the resources requested by any active resource request timers. The PMU sequencer maps clock requests into a set of
resources required to produce the requested clocks.
Each resource is in one of four states:
■enabled
■disabled
■transition_on
■transition_off
The timer contains 0 when the resource is enabled or disabled and a non-zero value in the transition states. The timer is loaded with
the time_on or time_off value of the resource when the PMU determines that the resource must be enabled or disabled. That timer
decrements on each 32.768 kHz PMU clock. When it reaches 0, the state changes from transition_off to disabled or transition_on to
enabled. If the time_on value is 0, the resource can transition immediately from disabled to enabled. Similarly, a time_off value of 0
indicates that the resource can transition immediately from enabled to disabled. The terms enable sequence and disable sequence
refer to either the immediate transition or the timer load-decrement sequence.
6. The PCIe interface is not brought up on CYW43455 and Cypress's firmware and drivers do not support this interface.

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CYW43455
During each clock cycle, the PMU sequencer performs the following actions:
■Computes the required resource set based on requests and the resource dependency table.
■Decrements all timers whose values are non zero. If a timer reaches 0, the PMU clears the ResourcePending bit for the resource
and inverts the ResourceState bit.
■Compares the request with the current resource status and determines which resources must be enabled or disabled.
■Initiates a disable sequence for each resource that is enabled, no longer being requested, and has no powered up dependents.
■Initiates an enable sequence for each resource that is disabled, is being requested, and has all of its dependencies enabled.
2.5 Power-Off Shutdown
The CYW43455 provides a low-power shutdown feature that allows the device to be turned off while the host, and any other devices
in the system, remain operational. When the CYW43455 is not needed in the system, VDDIO_RF and VDDC are shut down while
VDDIO remains powered. This allows the CYW43455 to be effectively off while keeping the I/O pins powered so that they do not draw
extra current from any other devices connected to the I/O.
During a low-power shutdown state, provided VDDIO remains applied to the CYW43455, all outputs are tristated, and most inputs
signals are disabled. Input voltages must remain within the limits defined for normal operation. This is done to prevent current paths
or create loading on any digital signals in the system, and enables the CYW43455 to be fully integrated in an embedded device and
take full advantage of the lowest power-savings modes.
When the CYW43455 is powered on from this state, it is the same as a normal power-up and the device does not retain any information
about its state from before it was powered down.
2.6 Power-Up/Power-Down/Reset Circuits
The CYW43455 has two signals (see Ta b le 2 ) that enable or disable the Bluetooth and WLAN circuits and the internal regulator blocks,
allowing the host to control power consumption. For timing diagrams of these signals and the required power-up sequences, see
Section 19.: “Power-Up Sequence and Timing”.
Table 2. Power-Up/Power-Down/Reset Control Signals
Signal Description
WL_REG_ON This signal is used by the PMU (with BT_REG_ON) to power-up the WLAN section. It is also
OR-gated with the BT_REG_ON input to control the internal CYW43455 regulators. When
this pin is high, the regulators are enabled and the WLAN section is out of reset. When this
pin is low, the WLAN section is in reset. If BT_REG_ON and WL_REG_ON are both low, the
regulators are disabled. This pin has an internal 200 k pull-down resistor that is enabled by
default. It can be disabled through programming.
BT_REG_ON This signal is used by the PMU (with WL_REG_ON) to decide whether or not to power down
the internal CYW43455 regulators. If BT_REG_ON and WL_REG_ON are low, the regulators
will be disabled. This pin has an internal 200 k pull-down resistor that is enabled by default.
It can be disabled through programming.

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3. Frequency References
An external crystal is used for generating all radio frequencies and normal operation clocking. As an alternative, an external frequency
reference may be used. In addition, a low-power oscillator (LPO) is provided for lower power mode timing.
3.1 Crystal Interface and Clock Generation
The CYW43455 can use an external crystal to provide a frequency reference. The recommended configuration for the crystal oscillator
including all external components is shown in Figure 5. Consult the reference schematics for the latest configuration.
Figure 5. Recommended Oscillator Configuration
A fractional-N synthesizer in the CYW43455 generates the radio frequencies, clocks, and data/packet timing, enabling it to operate
using a wide selection of frequency references.
The recommended default frequency reference is a 37.4 MHz crystal. The signal characteristics for the crystal interface are listed in
Tab l e 3.
Note: Although the fractional-N synthesizer can support alternative reference frequencies, frequencies other than the default require
support to be added in the driver, plus additional extensive system testing. Contact Cypress for further details.
WRF_XTAL_XON
WRF_XTAL_XOP
C
C
37.4 MHz
x ohms
27 pF
27 pF
Note: A reference schematic is available for further details.
Contact your Broadcom FAE.

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3.2 External Frequency Reference
As an alternative to a crystal, an external precision frequency reference can be used, provided that it meets the Phase Noise require-
ments listed in Tab l e 3.
If used, the external clock should be connected to the WRF_XTAL_XOP pin through an external 1000 pF coupling capacitor, as shown
in Figure 6. The internal clock buffer connected to this pin will be turned OFF when the CYW43455 goes into sleep mode. When the
clock buffer turns ON and OFF there will be a small impedance variation. Power must be supplied to the WRF_XTAL_VDD1P35 pin.
Figure 6. Recommended Circuit to Use With an External Reference Clock
Table 3. Crystal Oscillator and External Clock—Requirements and Performance
Parameter Conditions/Notes Crystal1External Frequency Ref-
erence2 3
Min. Typ. Max. Min. Typ. Max. Units
Frequency 2.4G and 5G bands,
IEEE 802.11ac operation
35 – 52 – 52 – MHz
Frequency 5G Band,
IEEE 802.11n operation only
19 – 52 35 – 52 MHz
2.4G band IEEE 802.11n operation,
and both bands legacy IEEE
802.11a/b/g operation only
Between 19 MHz and 52 MHz 4, 5
Frequency tolerance over
the lifetime of the
equipment, including
temperature6
Without trimming –20 – 20 –20 – 20 ppm
Crystal load capacitance – – 16 – – – – pF
ESR – – – 60 – – – Ω
Drive level External crystal must be able to
tolerate this drive level.
200 – – – – – μW
Input impedance (WRF_X-
TAL_XOP)
Resistive – – – 30k 100k – Ω
Capacitive – – 7.5 – – 7.5 pF
WRF_XTAL_XOP
Input low level
DC-coupled digital signal – – – 0 – 0.2 V
WRF_XTAL_XOP
Input high level
DC-coupled digital signal – – – 1.0 – 1.26 V
WRF_XTAL_XOP
input voltage
(see Figure 6)
IEEE 802.11a/b/g operation only – – – 400 – 1200 mVp-p
WRF_XTAL_XOP
input voltage
(see Figure 6)
IEEE 802.11n/ac AC-coupled analog
input
––– 1––V
p-p
Duty cycle 37.4 MHz clock – – – 40 50 60 %
Phase Noise7
(IEEE 802.11b/g)
37.4 MHz clock at 10 kHz offset – – – – – –129 dBc/Hz
37.4 MHz clock at 100 kHz offset – – – – – –136 dBc/Hz
Reference
Clock
NC
1000 pF
WRF_XTAL_XOP
WRF_XTAL_XON
4345XCT-DS1X15_f_009_1

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3.3 Frequency Selection
Any frequency within the ranges specified for the crystal and TCXO reference may be used. These include not only the standard
handset reference frequencies of 19.2, 19.8, 24, 26, 33.6, 37.4, 38.4, and 52 MHz, but also other frequencies in this range, with
approximately 80 Hz resolution. The CYW43455 must have the reference frequency set correctly in order for any of the UART or PCM
interfaces to function correctly, since all bit timing is derived from the reference frequency.
Note: The fractional-N synthesizer can support many reference frequencies. However, frequencies other than the default require
support to be added in the driver plus additional, extensive system testing. Contact Cypress for further details.
The reference frequency for the CYW43455 may be set in the following ways:
■Set the xtalfreq=xxxxx parameter in the nvram.txt file (used to load the driver) to correctly match the crystal frequency.
■Auto-detect any of the standard handset reference frequencies using an external LPO clock.
For applications such as handsets and portable smart communication devices, where the reference frequency is one of the standard
frequencies commonly used, the CYW43455 automatically detects the reference frequency and programs itself to the correct
reference frequency. In order for auto frequency detection to work correctly, the CYW43455 must have a valid and stable 32.768 kHz
LPO clock that meets the requirements listed in Table 4 and is present during power-on reset.
Phase Noise7
(IEEE 802.11a)
37.4 MHz clock at 10 kHz offset – – – – – –137 dBc/Hz
37.4 MHz clock at 100 kHz offset – – – – – –144 dBc/Hz
Phase Noise7
(IEEE 802.11n, 2.4 GHz)
37.4 MHz clock at 10 kHz offset – – – – – –134 dBc/Hz
37.4 MHz clock at 100 kHz offset – – – – – –141 dBc/Hz
Phase Noise7
(IEEE 802.11n, 5 GHz)
37.4 MHz clock at 10 kHz offset – – – – – –142 dBc/Hz
37.4 MHz clock at 100 kHz offset – – – – – –149 dBc/Hz
Phase Noise7
(IEEE 802.11ac, 5 GHz)
37.4 MHz clock at 10 kHz offset – – – – – –148 dBc/Hz
37.4 MHz clock at 100 kHz offset – – – – – –155 dBc/Hz
1. (Crystal) Use WRF_XTAL_XON and WRF_XTAL_XOP.
2. See “External Frequency Reference” for alternative connection methods.
3. For a clock reference other than 37.4 MHz, 20 × log10(f/ 37.4) dB should be added to the limits, where f = the reference clock frequency in MHz.
4. BT_TM6 should be tied low for a 52 MHz clock reference. For other frequencies, BT_TM6 should be tied high. Note that 52 MHz is not an
auto-detected frequency using the LPO clock.
5. The frequency step size is approximately 80 Hz resolution.
6. It is the responsibility of the equipment designer to select oscillator components that comply with these specifications.
7. Assumes that external clock has a flat phase noise response above 100 kHz.
Table 3. Crystal Oscillator and External Clock—Requirements and Performance (continued)
Parameter Conditions/Notes Crystal1External Frequency Ref-
erence2 3
Min. Typ. Max. Min. Typ. Max. Units

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3.4 External 32.768 kHz Low-Power Oscillator
The CYW43455 uses a secondary low frequency clock for low-power-mode timing. An external 32.768 kHz precision oscillator is
required.
Table 4. External 32.768 kHz Sleep Clock Specifications
Parameter LPO Clock Units
Nominal input frequency 32.768 kHz
Frequency accuracy ±200 ppm
Duty cycle 30–70 %
Input signal amplitude 200–3300 mV, p-p
Signal type Square-wave or sine-wave –
Input impedance1
1. When power is applied or switched off.
>100k
<5
Ω
pF
Clock jitter (during initial start-up) <10,000 ppm

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4. Bluetooth Subsystem Overview
The CYW43455 is a Bluetooth 5.0 + EDR-compliant and, baseband processor with 2.4 GHz transceiver.
The CYW43455 is the optimal solution for any Bluetooth voice and/or data application. The Bluetooth subsystem presents a standard
host controller interface (HCI) via a high-speed UART and PCM for audio. The CYW43455 incorporates all Bluetooth 5.0 mandatory
features include secure simple pairing, sniff subrating, and encryption pause and resume.
The CYW43455 Bluetooth radio transceiver provides enhanced radio performance to meet the most stringent mobile phone
temperature applications and the tightest integration into mobile handsets and portable devices. It provides full radio compatibility to
operate simultaneously with GPS, WLAN, and cellular radios.
The Bluetooth transmitter also features a Class 1 power amplifier with Class 2 capability.
4.1 Features
Primary CYW43455 Bluetooth features include:
■Bluetooth 5,0 complaint and qualified
■Fully supports Bluetooth Core Specification version 4.2 + EDR features:
❐Adaptive frequency hopping (AFH)
❐Quality of service (QoS)
❐Extended synchronous connections (eSCO)—voice connections
❐Fast connect (interlaced page and inquiry scans)
❐Secure simple pairing (SSP)
❐Sniff subrating (SSR)
❐Encryption pause resume (EPR)
❐Extended inquiry response (EIR)
❐Data packet length extension
❐Link supervision timeout (LST)
❐Secure connections
■UART baud rates up to 4 Mbps
■Supports all Bluetooth 4.2 + HS packet types
■Supports maximum Bluetooth data rates over HCI UART
■Multipoint operation with up to seven active slaves
❐Maximum of seven simultaneous active ACL links
❐Maximum of three simultaneous active SCO and eSCO connections with scatternet support
■Trigger Cypress fast connect (TBFC)
■Narrowband and wideband packet loss concealment
■Scatternet operation with up to four active piconets with background scan and support for scatter mode
■High-speed HCI UART transport support with low-power out-of-band BT_DEV_WAKE and BT_HOST_WAKE signaling (see Host
Controller Power Management)
■Channel quality driven data rate and packet type selection
■Standard Bluetooth test modes
■Extended radio and production test mode features
■Full support for power savings modes
❐Bluetooth clock request
❐Bluetooth standard sniff
❐Deep-sleep modes and software regulator shutdown
■Supports a low-power crystal, which can be used during power save mode for better timing accuracy.

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4.2 Bluetooth Radio
The CYW43455 has an integrated radio transceiver that has been optimized for use in 2.4 GHz Bluetooth wireless systems. It has
been designed to provide low-power, low-cost, robust communications for applications operating in the globally available 2.4 GHz
unlicensed ISM band. It is fully compliant with the Bluetooth Radio Specification and EDR specification and meets or exceeds the
requirements to provide the highest communication link quality of service.
4.2.1 Transmit
The CYW43455 features a fully integrated zero-IF transmitter. The baseband transmit data is GFSK-modulated in the modem block
and upconverted to the 2.4 GHz ISM band in the transmitter path. The transmitter path consists of signal filtering, I/Q upconversion,
output power amplifier, and RF filtering. The transmitter path also incorporates /4-DQPSK for 2 Mbps and 8-DPSK for 3 Mbps to
support EDR. The transmitter section is compatible to the Bluetooth Low Energy specification. The transmitter PA bias can also be
adjusted to provide Bluetooth class 1 or class 2 operation.
4.2.2 Digital Modulator
The digital modulator performs the data modulation and filtering required for the GFSK, /4-DQPSK, and
8-DPSK signal. The fully digital modulator minimizes any frequency drift or anomalies in the modulation characteristics of the trans-
mitted signal and is much more stable than direct VCO modulation schemes.
4.2.3 Digital Demodulator and Bit Synchronizer
The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency tracking and
bit-synchronization algorithm.
4.2.4 Power Amplifier
The fully integrated PA supports Class 1 or Class 2 output using a highly linearized, temperature-compensated design. This provides
greater flexibility in front-end matching and filtering. Due to the linear nature of the PA combined with some integrated filtering, external
filtering is required to meet the Bluetooth and regulatory harmonic and spurious requirements. For integrated mobile handset appli-
cations in which Bluetooth is integrated next to the cellular radio, external filtering can be applied to achieve near thermal noise levels
for spurious and radiated noise emissions. The transmitter features a sophisticated on-chip transmit signal strength indicator (TSSI)
block to keep the absolute output power variation within a tight range across process, voltage, and temperature.
4.2.5 Receiver
The receiver path uses a low-IF scheme to downconvert the received signal for demodulation in the digital demodulator and bit
synchronizer. The receiver path provides a high degree of linearity, an extended dynamic range, and high-order on-chip channel
filtering to ensure reliable operation in the noisy 2.4 GHz ISM band. The front-end topology with built-in out-of-band attenuation
enables the CYW43455 to be used in most applications with minimal off-chip filtering. For integrated handset operation, in which the
Bluetooth function is integrated close to the cellular transmitter, external filtering is required to eliminate the desensitization of the
receiver by the cellular transmit signal.
4.2.6 Digital Demodulator and Bit Synchronizer
The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency tracking and bit
synchronization algorithm.
4.2.7 Receiver Signal Strength Indicator
The radio portion of the CYW43455 provides a receiver signal strength indicator (RSSI) signal to the baseband, so that the controller
can take part in a Bluetooth power-controlled link by providing a metric of its own receiver signal strength to determine whether the
transmitter should increase or decrease its output power.

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4.2.8 Local Oscillator Generation
A local oscillator (LO) generation provides fast frequency hopping (1600 hops/second) across the 79 maximum available channels.
The LO generation subblock employs an architecture for high immunity to LO pulling during PA operation. The CYW43455 uses an
internal RF and IF loop filter.
4.2.9 Calibration
The CYW43455 radio transceiver features an automated calibration scheme that is fully self contained in the radio. No user interaction
is required during normal operation or during manufacturing to provide the optimal performance. Calibration optimizes the perfor-
mance of all the major blocks within the radio to within 2% of optimal conditions, including gain and phase characteristics of filters,
matching between key components, and key gain blocks. This takes into account process variation and temperature variation.
Calibration occurs transparently during normal operation during the settling time of the hops and calibrates for temperature variations
as the device cools and heats during normal operation in its environment.

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5. Bluetooth Baseband Core
The Bluetooth Baseband Core (BBC) implements all of the time critical functions required for high-performance Bluetooth operation.
The BBC manages the buffering, segmentation, and routing of data for all connections. It also buffers data that passes through it,
handles data flow control, schedules SCO/ACL TX/RX transactions, monitors Bluetooth slot usage, optimally segments and packages
data into baseband packets, manages connection status indicators, and composes and decodes HCI packets. In addition to these
functions, it independently handles HCI event types, and HCI command types.
The following transmit and receive functions are also implemented in the BBC hardware to increase reliability and security of the
TX/RX data before sending over the air:
■Symbol timing recovery, data deframing, forward error correction (FEC), header error control (HEC), cyclic redundancy check
(CRC), data decryption, and data dewhitening in the receiver.
■Data framing, FEC generation, HEC generation, CRC generation, key generation, data encryption, and data whitening in the
transmitter.
5.1 Bluetooth 4.0 Features
The BBC supports all Bluetooth 4.0 features, with the following benefits:
■Dual-mode Bluetooth Low Energy (BT and BLE operation)
■Extended Inquiry Response (EIR): Shortens the time to retrieve the device name, specific profile, and operating mode.
■Encryption Pause Resume (EPR): Enables the use of Bluetooth technology in a much more secure environment.
■Sniff Subrating (SSR): Optimizes power consumption for low duty cycle asymmetric data flow, which subsequently extends battery
life.
■Secure Simple Pairing (SSP): Reduces the number of steps for connecting two devices, with minimal or no user interaction
required.
■Link Supervision Time Out (LSTO): Additional commands added to HCI and Link Management Protocol (LMP) for improved link
time-out supervision.
■QoS enhancements: Changes to data traffic control, which results in better link performance. Audio, human interface device
(HID), bulk traffic, SCO, and enhanced SCO (eSCO) are improved with the erroneous data (ED) and packet boundary flag (PBF)
enhancements.
5.2 Bluetooth 4.2 Features
The BBC supports all Bluetooth 4.2 features, with the following benefits:
■Dual-mode classic Bluetooth and classic low energy (BT and BLE) operation
■Low-energy physical layer
■Low-energy link layer
■Enhancements to HCI for low energy
■Low-energy direct test mode
■128 AES-CCM secure connection for both BT and BLE
■LE Data Packet Length Extension
■LE Secure Connections
Note: The CYW43455 is compatible with the Bluetooth Low Energy operating mode, which provides a dramatic reduction in the power
consumption of the Bluetooth radio and baseband. The primary application for this mode is to provide support for low data rate
devices, such as sensors and remote controls.
5.3 Bluetooth Low Energy
The CYW43455 supports the Bluetooth Low Energy operating mode.
5.4 Bluetooth 5.0
CYW43455 is qualified for and supports the mandatory features of the Bluetooth 5.0 specification.