DAQ system PCIe-AIO14 User manual

PCIe-AIO14 User’s Manual (Rev 1.2)
i
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PCIe-AIO14
User’s Manual
Windows, Windows XP, Windows 7, Windows 8 and Windows 10 are trademarks of Microsoft. We acknowledge t
hat the trademarks or service names of all other organizations mentioned in this document as their own property.
Information furnished by DAQ system is believed to be accurate and reliable. However, no responsibility is assumed by DAQ
system for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or copyrights of DAQ system.
The information in this document is subject to change without notice and no part of this document may be copied or
reproduced without the prior written consent.
Copyrights 2005 DAQ system Co., LTD. All rights reserved.

PCIe-AIO14 User Manual (Rev 1.2)
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Contents
1. Introduction
1.1 Function
1.2 Block Diagram
2. Features
3. Hardware
3.1 Board Switch Setup
3.2 I/O Connector(J1, J2)
3.3 Digital I/O Connector(J8)
3.4 Analog Signal MUX
3.5 Digital I/O
4. Installation
4.1 Confirm Contents
4.2 Installation Sequence
4.3 Device Verification
5. Software
5.1 Operation Mode
5.2 Normal Mode Operation Sequence
5.3 Trigger Mode Operation
5.4 Sample Program
Referrence

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1. Introduction
The PCIe-AIO14 board is a PCI Express interface board with dedicated analog inputs.
The 16-channel analog signal is multiplexed by port control, and the signal is variably sampled
and converted by two ADCs.
1.1 Function
-PCI Express x1
-32-Channel 16-Bit ADC
2 low power SAR ADC
16-channel analog signal multiplex input for each ADC
10V Differential Signal input Level
10~2Msps Variable Sampling Setup
-32-Ch Software Trigger
-24-Bit Digital Input Output
Input / output shielding by photo coupler
24-Bit Digital Input
24-Bit Digital Output
1.2 Block Diagram
PCI Master
PCI Express
BUS
Local Bus
Address
Data(Mem,I/O)
SAR ADC
External
Interface
IO Decoder
PCIe-AIO14 INTERNAL BLOCK
MEM Decoder
BUS Mux 16-Ch Differential
Multiplexer
16-Ch Differential
Multiplexer
Digital IN/OUT
Isolator
AIN_A
AIN_B
DMA Engine
SAR ADC
[Fig 1-1. Internal block diagram]

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2. Features
[Table 1-1. PCIe-AIO14 Features]
List
Support Features
Interface
PCI Express x1
PCI Local Bus 32-Bit, 66-Mhz
VHDCI 68-pin connector or 40-pin connector
Analog Input
Channel : 2 Differential Single ADC,
Multiplex Input: 16-channel analog signal multiplex input for
each ADC
Resolution: 16-bit
Sampling Rate: 10~2Msps(1 Channel))
Signal Type: Differential
Digital I/O
Bit: Inpit 24-Bit, Output 24-Bit
Isolator: Photo Coupler TLP291-4 or Compatible
Input Signal: 12~24V, under 10kHz
Output Signal: Open Collector, under 10kHz, 12~24V
Board Size
152.4x101.1mm(PCB)
Operation Temperature
Range
Operating Humidity Range
(non-condensing)
Software
Kernel mode Driver/User mode DLL
OS
Windows XP SP2/7/8/10 32-bit, 64-bit, 4GB RAM
Components
PCIe-AIO14 board , Installation CD(with Sample Program)

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3. Hardware
This section explains how to install PCIe-AIO14 board in PC or other operation equipment. The
following explains the board switch settings before installation, input connector description, and
board installation.
3.1 Board Switch Setup
Explain the jumper and switch selection on the board.
J7
J1
J2
[Fig 3-1. Connector, Switch Layout]
3.1.1 Board Number Setup Switch(J7)
It is a switch for setting the number of the board. Up to 4 boards can be operated on one
system, and board numbers can not be used in duplicate.
SW1
1 2 Board #
OFF OFF 0
ON OFF 1
OFF ON 2
ON ON 3
2 1 ON
OFF
[Fig 3-2. Board Number Setup Switch]

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3.2 I/O Connector(J1, J2)
The PCIe-AIO14 board with 32-channel analog differential signal input has two VHDCI (Very
High Density Cable Interconnect) 68-pin connectors, each receiving 16 signals. The 16-bit signal
is one ADC input signal. Each connector is connected to a 4-bit digital input and output signal.
VHDCI-68
35
34
68
1
[Fig 3-3. VHDCI-68 Connector]
3.2.1 Connector J1
The 16-bit analog differential input signals (AINP, AINN, AGND) from 0 to 15 are connected to
the 4-bit digital input and output signal. The applicable connector is HDRA-E68LFDT (Honda) or
compatible product.
[Table 3-1. J1 Connector Description]
Pin#
Description
Pin#
Description
1
Reserved
35
Reserved
2
Analog Ground, AGND
36
Reserved
3
#30 Input(-), AINN30
37
Analog Ground, AGND
4
#30 Input(+), AINP30
38
Digital Input, DIN_COM0
5
#28 Input (-), AINN28
39
Analog Ground, AGND
6
#28 Input (+), AINP28
40
Digital Input, DIN0
7
#26 Input (-), AINN26
41
Analog Ground, AGND
8
#26 Input (+), AINP26
42
Digital Input, DIN1
9
#24 Input (-), AINN24
43
Analog Ground, AGND
10
#24 Input (+), AINP24
44
Digital Input, DIN2
11
#22 Input (-), AINN22
45
Analog Ground, AGND
12
#22 Input (+), AINP22
46
Digital Input, DIN3
13
#20 Input (-), AINN20
47
Analog Ground, AGND
14
#20 Input (+), AINP20
48
Digital Ground, GND
15
#18 Input (-), AINN18
49
Analog Ground, AGND
16
#18 Input (+), AINP18
50
Digital Output,
DOUT_COM0
17
#16 Input (-), AINN16
51
Analog Ground, AGND
18
#16 Input (+), AINP16
52
Digital Output, DOUT0

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19
#14 Input (-), AINN14
53
Analog Ground, AGND
20
#14 Input (+), AINP14
54
Digital Output, DOUT1
21
#12 Input (-), AIN12
55
Analog Ground, AGND
22
#12 Input (+), AINP12
56
Digital Output, DOUT2
23
#10 Input (-), AINN10
57
Analog Ground, AGND
24
#10 Input (+), AIN10
58
Digital Output, DOUT3
25
#8 Input (-), AINN8
59
Analog Ground, AGND
26
#8 Input (+), AINP8
60
Digital Ground, GND
27
#6 Input (-), AINN6
61
Analog Ground, AGND
28
#6 Input (+), AINP6
62
Digital Ground, GND
29
#4 Input (-), AINN4
63
Analog Ground, AGND
30
#4 Input (+), AINP4
64
Digital Ground, GND
31
#2 Input (-), AINN2
65
Analog Ground, AGND
32
#2 Input (+), AINP2
66
Reserved
33
#0 Input (-), AINN0
67
Analog Ground, AGND
34
#0 Input (+), AINP0
68
Reserved
Please inquire about the availability of analog input cable and terminal block board when
you purchase the product.
3.2.2 Connector J2
The 16-bit analog differential input signals (AINP, AINN, AGND) from 16 to 31 are connected to
the 4-bit digital input and output signal. The applicable connector is HDRA-E68LFDT (Honda) or
compatible product.
[Table 3-2. J2 Connector Description]
Pin#
Description
Pin#
Description
1
Reserved
35
Reserved
2
Analog Ground, AGND
36
Reserved
3
#31 Input (-), AINN31
37
Analog Ground, AGND
4
#31 Input (+), AINP31
38
Digital Input, DIN_COM1
5
#29 Input (-), AINN29
39
Analog Ground, AGND
6
#29 Input (+), AINP29
40
Digital Input, DIN4
7
#27 Input (-), AINN27
41
Analog Ground, AGND
8
#27 Input (+), AINP27
42
Digital Input, DIN5
9
#25 Input (-), AINN25
43
Analog Ground, AGND
10
#25 Input (+), AINP25
44
Digital Input, DIN6

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11
#23 Input (-), AINN23
45
Analog Ground, AGND
12
#23 Input (+), AINP23
46
Digital Input, DIN7
13
#21 Input (-), AINN21
47
Analog Ground, AGND
14
#21 Input (+), AINP21
48
Digital Ground, GND
15
#19 Input (-), AINN19
49
Analog Ground, AGND
16
#19 Input (+), AINP19
50
Digital Output,
DOUT_COM1
17
#17 Input (-), AINN17
51
Analog Ground, AGND
18
#17 Input (+), AINP17
52
Digital Output, DOUT4
19
#15 Input (-), AINN15
53
Analog Ground, AGND
20
#15 Input (+), AINP15
54
Digital Output, DOUT5
21
#13 Input (-), AINN13
55
Analog Ground, AGND
22
#13 Input (+), AINP13
56
Digital Output, DOUT6
23
#11 Input (-), AINN11
57
Analog Ground, AGND
24
#11 Input (+), AINP11
58
Digital Output, DOUT7
25
#9 Input (-), AINN9
59
Analog Ground, AGND
26
#9 Input (+), AINP9
60
Digital Ground, GND
27
#7 Input (-), AINN7
61
Analog Ground, AGND
28
#7 Input (+), AINP7
62
Digital Ground, GND
29
#5 Input (-), AINN5
63
Analog Ground, AGND
30
#5 Input (+), AINP5
64
Digital Ground, GND
31
#3 Input (-), AINN3
65
Analog Ground, AGND
32
#3 Input (+), AINP3
66
Reserved
33
#1 Input (-), AINN1
67
Analog Ground, AGND
34
#1 Input (+), AINP1
68
Reserved
Please inquire about the availability of analog input cable and terminal block board when
you purchase the product.
3.2.3 Analog Signal Wiring
To reduce the influence of noise, crosstalk, etc., analog signal is applied to differential signal
connection. Make cables with the following specifications.
Set AINP and AINN to Twisted Paired.
The core wires use thick strands if possible.
Cable length should be less than 1m and cable as short as possible.
Make sure that there are no unused wires in the cable. Connect unused signals to ground.
Use shielded cables to shield the wires.

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3.2.4 Digital I/O Connector(J8)
BOX HEADER 40-pin J8 connector has 16 DIN8 to DIN23 digital input signals and 16 DOUT8
to DOUT23 digital output signals. Applicable connector is HIF3F-40PA-2.54DS (Hirose) or
compatible product.
[Table 3-3. J8 Connector Description]
Pin#
Description
Pin#
Description
1
Digital Input, DIN8
2
Digital Input, DIN9
3
Digital Input, DIN10
4
Digital Input, DIN11
5
Digital Input, DIN12
6
Digital Input, DIN13
7
Digital Input, DIN14
8
Digital Input, DIN15
9
Digital Input, DIN16
10
Digital Input, DIN17
11
Digital Input, DIN18
12
Digital Input, DIN19
13
Digital Input, DIN20
14
Digital Input, DIN21
15
Digital Input DIN22
16
Digital Input, DIN23
17
Digital Input, DIN_COM2
18
Digital Ground, GND
19
Digital Ground,, GND
20
Digital Output,
DOUT_COM2
21
Digital Output, DOUT8
22
Digital Output, DOUT9
23
Digital Output, DOUT10
24
Digital Output, DOUT11
25
Digital Output, DOUT12
26
Digital Output, DOUT13
27
Digital Output, DOUT14
28
Digital Output, DOUT15
29
Digital Output, DOUT16
30
Digital Output, DOUT17
31
Digital Output, DOUT18
32
Digital Output, DOUT19
33
Digital Output, DOUT20
34
Digital Output, DOUT21
35
Digital Output, DOUT22
36
Digital Output, DOUT23
37
+12V_EXT
38
Reserved
39
Reserved
40
Reserved
The PC case bracket fixing cable is available, so please contact us when you purchase the
product.

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3.3 Ananlog Signal MUX
Multichannel data acquisition is implemented by multiplexing time-division
multiplexed (MUX) for 16 signal inputs into one ADC
AINP0
AINP30
16 to 1
MUX
Analog F/E,
ADC1
AINN0
AINN30
16 to 1
MUX
AIN_A
16 to 1
MUX
Analog F/E,
ADC2
16 to 1
MUX
AIN_B
AINP2
AINP28
AINN2
AINN28
AINP1
AINP31
AINN1
AINN31
AINP3
AINP29
AINN3
AINN29
AGND AGND
[Fig 3-4. Analog Signal MUX]
When one channel block is composed of a plurality of data channel selections, the interchannel
acquisition interval is a maximum sampling rate of 2Msps supported by the chip, and the interval
between blocks becomes the set sampling rate.
Figure 3-5 shows that when MUX channels are changed and collected when 'CH0', 'CH1',
'CH7', 'CH8' channel setting and 'Sampling Rate' value are set to '100000' (100ksps) Timing.
- AIN0/1 AD 󱑅󲡉󳈅 󲋭󲪦 - AIN2/3 AD 󱑅󲡉󳈅 󲋭󲪦 - AIN14/15 AD 󱑅󲡉󳈅 󲋭󲪦 - AIN16/17 AD 󱑅󲡉󳈅 󲋭󲪦 - AIN0/1 AD 󱑅󲡉󳈅 󲋭󲪦 - AIN2/3 AD 󱑅󲡉󳈅 󲋭󲪦 - AIN14/15 AD 󱑅󲡉󳈅 󲋭󲪦 - AIN16/17 AD 󱑅󲡉󳈅 󲋭󲪦 - AIN0/1 AD 󱑅󲡉󳈅 󲋭󲪦 - AIN2/3 AD 󱑅󲡉󳈅 󲋭󲪦 - AIN14/15 AD 󱑅󲡉󳈅 󲋭󲪦 - AIN16/17 AD 󱑅󲡉󳈅 󲋭󲪦 - AIN0/1 AD 󱑅󲡉󳈅 󲋭󲪦
- 󲴙󱇥 CH 0, 1, 7, 8 󲇵󳆲(󲴙󱇥 󱻩󱤲), 󲆭󳗡󱪖󱣝󲡉󳎍 100Ksps 󲇹󲣪󲠭 󰶒󲞅
󲎱󰳙
1/2Msps = 500nsec1/100Ksps = 10usec
[Fig 3-5. Data Collection MUX Timing]

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3.4 Digital I/O Circuit
Digital input and output circuits that support 24-bit inputs and outputs, respectively,
support shielded external interfaces by applying photocouplers.
3.4.1 Digital Input Circuit
When the ground is connected to the DIN_COM pin and the 'HI' input signal is input to the DIN
signal, the internal signal becomes 'LO' to sense the signal input.
DIN0 BIN0
BINx
+3.3V
+3.3V
2.4K
DINx
2.4K
DIN_COM
[Fig 3-6. Digital Input Circuit]
3.4.2 Digital Output Circuit
Apply the BOUT signal to 'LO'. Since current can be passed between the collector and the
emitter, a circuit can be constructed between the DOUT and DOUT_COM pins and controlled.
BOUT0
DOUT0
BOUTx
DOUTx
+3.3V
DOUT_COM
22
22
330
+3.3V
330
[Fig 3-7. Digital Output Circuit]

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4. Installation
This section explains how to install PCIe-AIO14 board in PC and confirm the device.
4.1 Confirm Contents
Before installing the board, make sure that there is no abnormality in the components.
-PCIe-AIO14 Board
-Installation CD (Driver/Manual/API/Sample Program etc)
4.2 Installation Sequence
The board should be used in Windows XP SP2 over, Windows 7, Windows 8 and Windows 10.
First, turn off the PC, insert the PCIe-AIO14 board into the PCI slot, and then power on the PC. The
following describes the process of installing the device in Windows XP.
When the "Welcome to the Found New Hardware Wizard" window opens, select it as shown below
and click the "Next" button.
[Fig 4-1. New Hardware Wizard Start]

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A window like the one below will appear and select "Install from a list or specific location" and
click the "Next" button.
[Fig 4-2. Software Installation Selection]
In the window shown below, locate the CD or specific location where the driver is located and
click the "Next" button.
[Fig 4-3. Driver Location Select]

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When the "Hardware Installation" window appears and the following list of installed boards
appears, click the "Continue" button.
[Fig 4-4. Show the board you are installing]
The "Completing the Found New Hardware Wizard" window appears and click the "Finish" button
to finish.
[Fig 4-5. Terminate driver installation]

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4.3 Device Verification
When the board installation is complete, check that the device is assigned to the OS. Control
Panel - System - System Properties - Device Manager Select / Execute in order. Under Device
Manager - Multifunction Adapters, make sure that the "PCIe-AIO14" device is shown as shown.
[Fig 4-6. Devie Manager]

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5. Software
It implements a library (API) for easy access to various functions of the PCIe-AIO14 board, and
provides a sample program to the user.
5.1 Operation Mode
Appropriate API functions should be used depending on the operation such as the method of
storing data collection samples in internal memory, the method of reading buffer data in the
application, the use of trigger function, etc.
Acquisition data storage consists of a continuous mode, which operates as a ring buffer format
in succession from the beginning of the memory to the end address (Over-Writing), and a single
mode in which data is written from the beginning to the end and the acquisition function is
stopped.
How to read buffered data in the App can be read by a certain number of samples or by data
blocks.
The trigger mode stores samples before and after the software trigger occurs and stops the
acquisition function.
[Figure 5-1] shows the function corresponding to the operation order for each mode.
[Fig 5-1. Operation sequence and function]

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5.2 Normal Mode Operation Sequence
5.2.1 Device Initialization
OpenDAQDevice
Windows handle allocation from the system, device initialization
5.2.2 Measurement time setting
ADC_SetSamplingRate
AD Sampling Rate Setup
5.2.3 Start measurement
ADC_Run
Initialize logic variables, Start data collection and create a data memory buffer
5.2.4 Checking the measurement status
ADC_GetBufferedCount, ADC_GetBlockState
Number of data buffering samples in continuous mode, read / write memory Buffer pointer
check
5.2.5 Read measurement data
ADC_ReadBufferedData, ADC_GetBlockData,
Data collection. Repeat measurement status check and data read
5.2.6 End of measurement
ADC_Stop
Stop collecting AD data and release the data memory buffer
5.2.7 Device Release
CloseDAQDevice
Return Windows handle to system

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5.3 Trigger Mode Operation Sequence
5.3.1 Device Initialization
OpenDAQDevice
Windows handle allocation from the system, device initialization
5.3.2 Measurement time setting
ADC_SetSamplingRate
ADC Sampling Rate Setup
5.3.3 Trigger Setup
ADC_SetTriggerLevel, ADC_SetTriggerVolt
Trigger channel, Trigger slope, Trigger level value setting and trigger motion control
5.3.4 Start measurement
ADC_Run, ADC_TriggerRun
Initialize logic variables, start data acquisition and data memory buffers, and start trigger
operation
5.3.5 Checking the Trigger Status
ADC_GetTriggerState
Trigger occurrence, trigger occurrence value, and trigger occurrence pointer
5.3.6 Reading Trigger Data
ADC_GetTriggerData
Trigger data collection of selected analog channels
5.3.7 End of measurement
ADC_Stop, ADC_TriggerStop
Stop AD data collection and release data memory buffers, disable triggering
5.3.8 Device Release
CloseDAQDevice
Return Windows handle to system

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5.4 Sample Program
It implements a library (API) for easy access to various functions of the PCIe-AIO14 board, and
provides a sample program to the user.
3 41 2 5
6 7
8
9
11
12
10
13
14
15
16
17 18
19
20 21 22
23
24 25
26 27 28
29 30
31
32 33 34
35
36
37
38
39
40
41 42
43
44
45
46
47
48
[Fig 5-2. Program execution (continuous mode)]
5.4.1 Program UI Description
[󳔱5-1. Sample Program Fuction Description]
Num
Control
Description
1
Device
Select PCIe-AIO14 among the devices. By using the dedicated
library (API), the setting value is not affected, but the default
value is PCIe-AIO14 (4).
2
Board Sel.
Select the device sequence number. As described in Section
3.1.1, the switch setting value and the board selection number of
the API must be matched so that normal operation is possible.
3
Device Open
Get the PCIe-AIO14 device handle value from the Windows OS.
When you run the program, it automatically searches for
devices.
4
Device Close
Returns the device handle value to the OS and stops using the
device.
5
Version
Displays the hardware logic version and DLL version.
6
CHx
Select the channel number you want to sample. And becomes
one channel block.

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7
Ch. Value
The selected channel value is represented by HEX. Bit 0 is set
to "CH0" and bit 15 is set to "CH15". Since "CH0" selection is
AIN0, AIN1 is selected, and "CH15" selection is AIN30 and
AIN31 because channel selection is for two ADCs.
8
Ch. Counts
Number of selected channels. A channel twice as many as the
7th bit set number is selected.
9
Sampling Rate
(10~2Msps)
Set the ADC data sampling frequency (SPS). The setting range
is a maximum of 2,000,000 (2Msps) at a minimum of 10sps, and
decreases by a multiple of the set value according to the number
of channel selections. See Section 5.4.6.
10
Samples
Samples per channel
11
Blocks
The data block having the number of samples of the selected
channel data
12
Buffer Size
The buffer size is calculated by the input buffer variable. Buffer
Size = number of channels (8 times) x number of samples (10) x
number of data blocks (11).
13
Read Length
The number of samples read from the API when reading
collected data.
14
WR Ptr.
Buffer write pointer
15
RD Ptr.
Buffer read pointer
16
Sample/sec
Number of samples per second per channel block
17
Save
Open the file in folder 19, file name.
18
…
Folder search and file name selection, input
19
“C:\\data.txt”
Storage path and file name, selected in 18, the file path entered
is displayed. The default path is "C: \\ data.txt".
20
Single Buf/
Continuous Buf
Select the storage buffering method of the acquisition sample of
the normal mode measurement. Single mode, continuous mode.
21
Start/Stop
Start the normal mode data collection with the 'Start' button.
Buffering that does not support the trigger function collects data
from the device inside the library, and the application periodically
reads the data of the library and displays it on the graph.
Reading method is different according to 20 buffering method.
22
ReadEn
Read control data from the library buffer. Read data in the check
state and display it on the graph.
23
Run
Checks if a trigger has occurred on the selected channel and
reads and stops the status if it occurs. When the trigger occurs,