DAQ system PCIe-FRM24 User manual

PCIe-FRM24 Users Manual (Rev 1.3)
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PCIe-FRM24
User’s Manual
Windows, Windows2000, Windows NT and Windows XP are trademarks of Microsoft. We acknowledge that the
trademarks or service names of all other organizations mentioned in this document as their own property.
Information furnished by DAQ system is believed to be accurate and reliable. However, no responsibility is assumed by DAQ
system for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or copyrights of DAQ system.
The information in this document is subject to change without notice and no part of this document may be copied or
reproduced without the prior written consent.
Copyrights 2005 DAQ system, All rights reserved.

PCIe-FRM24 Users Manual (Rev 1.3)
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-- Contents --
1. Introduction
2. PCIe-FRM24 Functions
2.1 FPGABlock Diagram
2.2 Encoder Trigger Controller
3. PCIe-FRM24 Board Description
3.1 PCB Layout
3.2 Description of the functional blocks
3.3 Connector Pin-out
3.3.1 J4(MDR26) Connecter
3.3.2 J2(MDR26) Connecter
3.3.3 J1 Connecter
3.3.4 J5 Connecter
3.3.2 J7 Connecter
3.3.5 SW1
4. Installation
4.1 Hardware Installation
4.1.1 Package Contents
4.1.2 Installation Sequence
4.2 Software Driver Installation
5. Sample Program
5.1 FrmTest
5.2 FrameView
Appendix
A.1 General Specification
A.2 Physical Dimension
Reference

PCIe-FRM24 Users Manual (Rev 1.3)
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1. Introduction
The PCIe-FRM24 is a board having the function of processing the frame data received from
Camera-link camera and saving the image frame data in the system‟s main memory. It supports full
Camera Link configuration, and Area Scan Camera, Line Scan Camera, Monochrome Camera Link
Camera.
The operation of the board is controlled by program API, figure [1-1] shows connection of the
system (usually PC).
[Figure 1-1. PCIe-FRM24 Board Usage]
As shown in Figure [1-1], the PCIe-FRM24 is inserted into any available PCI Express slot in your
PC. It receives Image Frame from camera via Camera-Link Standard Interface. And, received data
transmit to the API through PCI Express x4 interface.

PCIe-FRM24 Users Manual (Rev 1.3)
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[Figure 1-2. Picture of PCIe-FRM24 board real operation]
Figure [1-2] shows physical connection of the board to the Camera-Link Camera. At the left side, there
are two Camera-Link connector and received image data (max. 680Mbyte).

PCIe-FRM24 Users Manual (Rev 1.3)
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[Features of the PCIe-FRM24]
Support Base Configuration Camera Link
Support Full/Medium Configuration Camera Link
Support Line Scan & Area Scan Camera
PCI Express 4x Interface
Acquisition pixel clock rates up to 85MHz
Video data rate of up to maximum 680Mbytes/sec
UART(Data bit 8, 1 start, 1 stop, No parity, 9600/19200/38400/57600/115200bps) Rx/Tx
External Device Interface : 4 TTL Digital Input/Output, and 2 TTL trigger Input Signals
and 4-pair RS-422
User Environment : Windows 2000 SP4, Windows XP SP1
Convenient Windows Application Programming Interface(DLL)
[Application]
Image Acquisition (Pattern, Particle etc.)
Inspection Equipment (Sensor, Semiconductor, Device etc.)
Security Solution
Black and White, Color Image Display
Medical Image Capture (X-ray, Supersonic etc.)

PCIe-FRM24 Users Manual (Rev 1.3)
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2. PCIe-FRM24 Functions
2.1 Block Diagram
As shown in the following figure, main control of the board is performed in FPGA Core Logic.
Primary functions are receiving the image frame data, camera control signal and external Line
Trigger I/O.
You can control these functions using API provided by DAQ system through PCI Express 4x
interface.
PCI Target
/ Master
PCI Express
4x BUS Local Bus
Address
Data(Mem,I/O)
Reserved
(0x00 ?0x5F)
Reserved
(0x70 ?0xAF)
UART
(0x60)
Camera Link(LVDS)
(0xC0)
Interrupt controller
DIO
(0xD0)
Ext. Address, Data, Control
Local BUS
Interrupt
Controller
(0xb0)
INT sources in Chip
IO Decoder
MEM Decoder
To each IO
Module
PCIe-FRM24 INTERNAL BLOCK - FPGA
DPRAM
From Ext.
CLOCK syn.
MEM Decoder
BUS Mux
Reserved
(0xE0 ?0xFF)
[Figure 2-1. Functional Block Diagram]
The core logic program of the FPGA is loaded by JTAG. It saves a program at the FPGAProgram
Logic and loads when power-up.

PCIe-FRM24 Users Manual (Rev 1.3)
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2.2 Encoder Trigger Controller
PCIe-FRM24 has 4 pair isolated photo-coupler input signals and 6 TTL level signals for
external digital I/O (Motion Controller, Digital I/O board etc.). It can control a camera.
[Figure 2-2. Encoder Trigger Control]
[Figure 2-3] shows the Photo-coupler circuit. The output current has to be used under 10mA.
EA, EB, EZ,
REV EA+, EB+, EZ+,
REV+
EA-, EB-, EZ-,
REV-
680
[Figure 2-3. Photo-coupler Circuit]
Caution) As Trigger Control can change according to kinds of Motion Controller or Camera,
when you want use this function, contact to DAQ system

PCIe-FRM24 Users Manual (Rev 1.3)
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3. PCIe-FRM24 Board Description
In this chapter, the primary functions of the PCIe-FRM24 board are described briefly. For more
information, refer to the device specification
3.1 PCIe-FRM24 Layout
[Figure 3-1. PCIe-FRM24 PCB Layout]
The board has five LEDs to indicate the operation status.
LED1 ~ LED4 turns on when PCI Express Lane (4 differential signal) is normal state.
LED5 turns on when power is applied to the board and the initialization ends up.
LED7 turns on when frame data is transferring. (When frame data is requested)
LED8turns on when frame data is transferring. (When frame data is acquired)

PCIe-FRM24 Users Manual (Rev 1.3)
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3.2 Description of the functional blocks
(1) MDR-26 Connecter : J2, J4
Camera Link Base (J2), medium/Full (J4) Signal Connector
(2) LVDS Link : U12, U15, U18
Receive Image frame
(3) FPGA : U16
All of the board functions are controlled by the Logic program of the FPGA.
(4) PCI Express Chipset: U8
It „s a PCI Express Bridge.
(5) Line Trigger : J7
It is supposed to I/O circuit for external devices.
(6) Regulator : U6, U7, U10, U11, U13, U20
This block is for supplying the power to the board.
.

PCIe-FRM24 Users Manual (Rev 1.3)
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3.3 Connecter Pin-out
The PCIe-FRM24 board is equipped with MDR 26 Pin connector J2, J4 for Camera Link
connection and 26pin Box Header connecter for external Trigger I/O.
Figure [3-2] shows the bracket of the board and connector.
3
10
9
8
7
6
1
2
5
4
19
18
17
16
15
14
13
12
1124
23
22
21
20
26
25
3
10
9
8
7
6
1
2
5
4
19
18
17
16
15
14
13
12
1124
23
22
21
20
26
25
[Figure 3-2. PCIe-FRM24 Front View]

PCIe-FRM24 Users Manual (Rev 1.3)
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3.3.1 J4(MDR26) Connecter
Figure [3-3] shows the board‟s J4 connector pin-map when you use the Full Configuration
Camera Link. All of the pin functions are based on the Camera link standard, so please refer
to the Camera link standard document for more description and information.
3
10
9
8
7
6
1
2
5
4
19
18
17
16
15
14
13
12
1124
23
22
21
20
Inner shield Inner shield
26
25
Z0-
TERMI+
YCLK-
Y3-
Y2-
Y1-
Y0-
Inner shield
Frame Grabber
Z0+
TERMI-
YCLK+
Y3+
Y2+
Y1+
Y0+
Inner shield
Z3+
ZCLK+
Z2+
Z1+
Z3-
ZCLK-
Z2-
Z1-
[Figure 3-3. PCIe-FRM24 J4 Connector Pin-out]

PCIe-FRM24 Users Manual (Rev 1.3)
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[Table 1. J4 Connecter Description]
Pin
Signal Name
Description
Remark
1
Inner Shield
Cable shield
2
Z3+-
Camera link LVDS receive data11+
3
ZCLK+
Camera link LVDS receive clock+
4
Z2+-
Camera link LVDS receive data10+
5
Z1-
Camera link LVDS receive data9+
6
Z0+
Camera link LVDS receive data8+
7
TERMI-
Serial to Camera-
8
Y3+
Camera link LVDS receive data7 +
9
YCLK+
Camera link LVDS receive clock +
10
Y2+
Camera link LVDS receive data6 +
11
Y1+
Camera link LVDS receive data5 +
12
Y0+
Camera link LVDS receive data4 +
13
Inner Shield
14
Inner Shield
15
Z3-
Camera link LVDS receive data11-
16
ZCLK-
Camera link LVDS receive clock-
17
Z2-
Camera link LVDS receive data10-
18
Z1-
Camera link LVDS receive data9-
19
Z0-
Camera link LVDS receive data8-
20
TERMI+
Serial to Camera+
21
Y3-
Camera link LVDS receive data7-
22
YCLK-
Camera link LVDS receive clock-
23
Y2-
Camera link LVDS receive data6-
24
Y1-
Camera link LVDS receive data5-
25
Y0-
Camera link LVDS receive data4-
26
Inner Shield
(Note) For more information, refer to Camera Link Standard Specification.

PCIe-FRM24 Users Manual (Rev 1.3)
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3.3.2 J2(MDR26) Connecter
Figure [3-4] shows the board‟s J2 connector pin-map when you use the Base Configuration
Camera Link. All of the pin functions are based on the Camera link standard, so please refer
to the Camera link standard document for more description and information.
3
10
9
8
7
6
1
2
5
4
19
18
17
16
15
14
13
12
1124
23
22
21
20
Inner shield Inner shield
26
25
SerTFG-
SerTC+
Xclk-
X3-
X2-
X1-
X0-
Inner shield
Frame Grabber
SerTFG+
SerTC-
Xclk+
X3+
X2+
X1+
X0+
Inner shield
CC4-
CC3+
CC2-
CC1+
CC4+
CC3-
CC2+
CC1-
[Figure 3-4. PCIe-FRM24 J2 Connector Pin-out]

PCIe-FRM24 Users Manual (Rev 1.3)
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[Table 2. J2 Connecter Description]
Pin
Signal Name
Description
Remark
1
Inner Shield
Cable shield
2
CC4+-
Camera Control output 4+
Refer to Figure 3-5
3
CC3-
Camera Control output 3-
Refer to Figure 3-5
4
CC2+-
Camera Control output 2+
Refer to Figure 3-5
5
CC1-
Camera Control output 1-
Refer to Figure 3-5
6
DRRX+
Serial to Frame grabber +
7
DRTX-
Serial to Camera-
8
RxIN3+
Camera link LVDS receive data3 +
9
RxCLKIN+
Camera link LVDS receive clock +
10
RxIN2+
Camera link LVDS receive data2 +
11
RxIN1+
Camera link LVDS receive data1 +
12
RxIN0+
Camera link LVDS receive data0 +
13
Inner Shield
14
Inner Shield
15
CC4-
Camera Control output 4-
Refer to Figure 3-5
16
CC3+
Camera Control output 3+
Refer to Figure 3-5
17
CC2-
Camera Control output 2-
Refer to Figure 3-5
18
CC1+
Camera Control output 1+
Refer to Figure 3-5
19
DRRX-
Serial to Frame grabber-
20
DRTX+
Serial to Camera+
21
RxIN3-
Camera link LVDS receive data3-
22
RxCLKIN-
Camera link LVDS receive clock-
23
RxIN2-
Camera link LVDS receive data2-
24
RxIN1-
Camera link LVDS receive data1-
25
RxIN0-
Camera link LVDS receive data0-
26
Inner Shield
(Note) For more information, refer to Camera Link Standard Specification.

PCIe-FRM24 Users Manual (Rev 1.3)
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CCx+
CCx-
Camera Control
Above picture is a Camera Control output circuit from PCIe-FRM24 board to Camera for the
specific control of the Camera-link Cable.
The PCIe-FRM24 board has four differential digital outputs. Each output is mapped by Digital
output. Below picture display that each bit position set.
CC1+
CC1-
CC_D0
CC2+
CC2-
CC_D1
CC3+
CC3-
CC_D2
CC4+
CC4-
CC_D3
[Figure 3-5. Camera Control LVDS Digital Output Circuit]
3.3.3 J1 Connector (2Pin Header, 2.54mm)
3.3V external DC power connector. It is a power source for FPGA installation and is not
normally used.
3.3.4 J5 Connector
J5 is a Joint Test Action Group (JTAG) connector used to update the FPGA program on the
board. It does not use when operating the board normally.

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3.3.5 J7 Connector
J7 is an I / O connector that provides four pairs of isolated photo-coupler input signals, four
TTL inputs, and two TTL output signal lines..
1
2
3
4
95
6 8
7
10
11
12
13
14 20 24
2321
22
19
18
17
16
15
J7
26
25
[Fig 3-5. J7 Connector (Top View)]
[Table 3. J7 PIN-OUT Description]
No.
Name
Description
1
N.C.
No Connection
2
N.C.
No Connection
3
EA+
Encoder A+ (Positive) Phase
4
EA-
Encoder A- (Negative) Phase
5
EB+
Encoder B+ (Positive) Phase
6
EB-
Encoder B-(Negative) Phase
7
EZ+
Encoder Z+ (Positive) Phase
8
EZ-
Encoder Z- (Negative) Phase
9
REV+
Direction (Positive) Signal
10
REV-
Direction (Negative) Signal
11
PAGE_TRIGGER_IN
TTL Input
12
N.C.
No Connection
13
LINE_TRIGGER_START
TTL Input
14
N.C.
No Connection
15
DIGITAL_OUT
TTL Output
16
N.C.
No Connection
17
DIGITAL_IN
TTL Input
18
N.C.
No Connection
19
LINE_TRIGGER_IN
TTL Input
20
GND
Ground
21
LINE_TRIGGER_OUT
TTL Output
22
GND
Ground
23
N.C.
No Connection
24
GND
Ground

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25
+3.3V
Board Power (+3.3V)
26
GND
Ground
3.3.6 SW1
The PCIe-FRM24 board is designed of four maximum PCIe-FRM24 boards at the same
time so as usable. Distribution of each board sets it up through 4 pin switch (SW1) in a board.
1
ON
OFF
SW1
2
[Figure 3-6. SW2 Switch]
[Table 3. SW1 Description]
1
2
Description
OFF
OFF
Board No. 0
ON
OFF
Board No. 1
OFF
ON
Board No. 2
ON
ON
Board No. 3

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4. Installation
4.1 Hardware Installation
In addition to the user‟s Manual, the package includes the following items. If any of these items
is missing or damaged, contact DAQ system.
After unpacking, inspect the board carton to make sure there are no damages on the board.
4.1.1 Package Contents
①PCIe-FRM24 Board
②CD (Driver/Manual/API/Sample Source etc.)
-Document Folder : Manual and Catalog
-Driver Folder : pcie_frm24.sys, pcie-frm24.inf
-Sample Folder : SampleApplication and DLL
-TestApp Folder : FrmTest.exe
4.1.2 Installation Process
①Turn off the PC power.
②Remove the computer cover using the instructions from the computer manual.
③Insert the board empty PCI Express slot as soon as possible to close the CPU.
④Remove the blank metal plate located at the back of the selected slot. Keep the removed
screw to fasten the board after installation.
⑤You should try number 3 in case of multi-board.

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4.2 Software Driver Installation
To install your PCIe-FRM24 board in your PC, follow the steps described in the document
“How to install PCI DAQ Board” provided by DAQ System. If the document is missing, you can
get it from www.daqsystem.com. The PCIe-FRM24 board is completely Plug & Play. There are
no switches or jumpers to set. Therefore you can install it easily.
- Your OS requirement : Windows 2000 SP4 or Windows XP SP1 above
The PCIe-FRM24 connects to Express Card Port. After that you can show the below picture of
“Welcome to found New Hardware Search Wizard” window.
If new hardware is found, Wizard will ask you to install the corresponding driver. For installation
of the driver, select the item “Install from a list or specific location (Advanced)” and click
“Next” as in the figure.

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Select “Search for the best driver in these locations”. Check “Search removable media (floppy,
CD-ROM)”. Check “include this location in the search”. Click “Browse” button. Select the folder
where the drivers are located. Click “OK”. Click “Next”.
The necessary files are “pcie_frm24.inf” and “pcie_frm24.sys” in the driver polder.