DAQ system PCIe-FRM24 User manual

PCIe-FRM24 Users Manual (Rev 1.3)
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PCIe-FRM24
User’s Manual
Windows, Windows2000, Windows NT and Windows XP are trademarks of Microsoft. We acknowledge that the
trademarks or service names of all other organizations mentioned in this document as their own property.
Information furnished by DAQ system is believed to be accurate and reliable. However, no responsibility is assumed by DAQ
system for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or copyrights of DAQ system.
The information in this document is subject to change without notice and no part of this document may be copied or
reproduced without the prior written consent.
Copyrights 2005 DAQ system, All rights reserved.

PCIe-FRM24 Users Manual (Rev 1.3)
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-- Contents --
1. Introduction
2. PCIe-FRM24 Functions
2.1 FPGABlock Diagram
2.2 Encoder Trigger Controller
3. PCIe-FRM24 Board Description
3.1 PCB Layout
3.2 Description of the functional blocks
3.3 Connector Pin-out
3.3.1 J4(MDR26) Connecter
3.3.2 J2(MDR26) Connecter
3.3.3 J1 Connecter
3.3.4 J5 Connecter
3.3.2 J7 Connecter
3.3.5 SW1
4. Installation
4.1 Hardware Installation
4.1.1 Package Contents
4.1.2 Installation Sequence
4.2 Software Driver Installation
5. Sample Program
5.1 FrmTest
5.2 FrameView
Appendix
A.1 General Specification
A.2 Physical Dimension
Reference

PCIe-FRM24 Users Manual (Rev 1.3)
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1. Introduction
The PCIe-FRM24 is a board having the function of processing the frame data received from
Camera-link camera and saving the image frame data in the system‟s main memory. It supports full
Camera Link configuration, and Area Scan Camera, Line Scan Camera, Monochrome Camera Link
Camera.
The operation of the board is controlled by program API, figure [1-1] shows connection of the
system (usually PC).
[Figure 1-1. PCIe-FRM24 Board Usage]
As shown in Figure [1-1], the PCIe-FRM24 is inserted into any available PCI Express slot in your
PC. It receives Image Frame from camera via Camera-Link Standard Interface. And, received data
transmit to the API through PCI Express x4 interface.

PCIe-FRM24 Users Manual (Rev 1.3)
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[Figure 1-2. Picture of PCIe-FRM24 board real operation]
Figure [1-2] shows physical connection of the board to the Camera-Link Camera. At the left side, there
are two Camera-Link connector and received image data (max. 680Mbyte).

PCIe-FRM24 Users Manual (Rev 1.3)
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[Features of the PCIe-FRM24]
Support Base Configuration Camera Link
Support Full/Medium Configuration Camera Link
Support Line Scan & Area Scan Camera
PCI Express 4x Interface
Acquisition pixel clock rates up to 85MHz
Video data rate of up to maximum 680Mbytes/sec
UART(Data bit 8, 1 start, 1 stop, No parity, 9600/19200/38400/57600/115200bps) Rx/Tx
External Device Interface : 4 TTL Digital Input/Output, and 2 TTL trigger Input Signals
and 4-pair RS-422
User Environment : Windows 2000 SP4, Windows XP SP1
Convenient Windows Application Programming Interface(DLL)
[Application]
Image Acquisition (Pattern, Particle etc.)
Inspection Equipment (Sensor, Semiconductor, Device etc.)
Security Solution
Black and White, Color Image Display
Medical Image Capture (X-ray, Supersonic etc.)

PCIe-FRM24 Users Manual (Rev 1.3)
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2. PCIe-FRM24 Functions
2.1 Block Diagram
As shown in the following figure, main control of the board is performed in FPGA Core Logic.
Primary functions are receiving the image frame data, camera control signal and external Line
Trigger I/O.
You can control these functions using API provided by DAQ system through PCI Express 4x
interface.
PCI Target
/ Master
PCI Express
4x BUS Local Bus
Address
Data(Mem,I/O)
Reserved
(0x00 ?0x5F)
Reserved
(0x70 ?0xAF)
UART
(0x60)
Camera Link(LVDS)
(0xC0)
Interrupt controller
DIO
(0xD0)
Ext. Address, Data, Control
Local BUS
Interrupt
Controller
(0xb0)
INT sources in Chip
IO Decoder
MEM Decoder
To each IO
Module
PCIe-FRM24 INTERNAL BLOCK - FPGA
DPRAM
From Ext.
CLOCK syn.
MEM Decoder
BUS Mux
Reserved
(0xE0 ?0xFF)
[Figure 2-1. Functional Block Diagram]
The core logic program of the FPGA is loaded by JTAG. It saves a program at the FPGAProgram
Logic and loads when power-up.

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2.2 Encoder Trigger Controller
PCIe-FRM24 has 4 pair isolated photo-coupler input signals and 6 TTL level signals for
external digital I/O (Motion Controller, Digital I/O board etc.). It can control a camera.
[Figure 2-2. Encoder Trigger Control]
[Figure 2-3] shows the Photo-coupler circuit. The output current has to be used under 10mA.
EA, EB, EZ,
REV EA+, EB+, EZ+,
REV+
EA-, EB-, EZ-,
REV-
680
[Figure 2-3. Photo-coupler Circuit]
Caution) As Trigger Control can change according to kinds of Motion Controller or Camera,
when you want use this function, contact to DAQ system

PCIe-FRM24 Users Manual (Rev 1.3)
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3. PCIe-FRM24 Board Description
In this chapter, the primary functions of the PCIe-FRM24 board are described briefly. For more
information, refer to the device specification
3.1 PCIe-FRM24 Layout
[Figure 3-1. PCIe-FRM24 PCB Layout]
The board has five LEDs to indicate the operation status.
LED1 ~ LED4 turns on when PCI Express Lane (4 differential signal) is normal state.
LED5 turns on when power is applied to the board and the initialization ends up.
LED7 turns on when frame data is transferring. (When frame data is requested)
LED8turns on when frame data is transferring. (When frame data is acquired)

PCIe-FRM24 Users Manual (Rev 1.3)
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3.2 Description of the functional blocks
(1) MDR-26 Connecter : J2, J4
Camera Link Base (J2), medium/Full (J4) Signal Connector
(2) LVDS Link : U12, U15, U18
Receive Image frame
(3) FPGA : U16
All of the board functions are controlled by the Logic program of the FPGA.
(4) PCI Express Chipset: U8
It „s a PCI Express Bridge.
(5) Line Trigger : J7
It is supposed to I/O circuit for external devices.
(6) Regulator : U6, U7, U10, U11, U13, U20
This block is for supplying the power to the board.
.

PCIe-FRM24 Users Manual (Rev 1.3)
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3.3 Connecter Pin-out
The PCIe-FRM24 board is equipped with MDR 26 Pin connector J2, J4 for Camera Link
connection and 26pin Box Header connecter for external Trigger I/O.
Figure [3-2] shows the bracket of the board and connector.
3
10
9
8
7
6
1
2
5
4
19
18
17
16
15
14
13
12
1124
23
22
21
20
26
25
3
10
9
8
7
6
1
2
5
4
19
18
17
16
15
14
13
12
1124
23
22
21
20
26
25
[Figure 3-2. PCIe-FRM24 Front View]