DAQ system PCIe-FRM24 User manual

PCIe-FRM24_C
User Manual
Version 1.2
ⓒ2005 DAQ SYSTEM Co., Ltd. All rights reserved.
Microsoft®is a registered trademark; Windows®, Windows NT®, Windows XP®, Windows 7®, Windows 8®, Windows 10®
All other trademarks or intellectual property mentioned herein belongs to their respective owners.
Information furnished by DAQ SYSTEM is believed to be accurate and reliable, However, no responsibility is assumed by DAQ SYSTEM for its use, nor
for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under
any patent or copyrights of DAQ SYSTEM.
The information in this document is subject to change without notice and no part of this document may be copied or reproduced without the prior
written consent.

PCIE-FRM24_C User’s Manual
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Contents
1. Introduction -------------------------------------------------------------------------- 3
1-1 Product Features ------------------------------------------------------------------------- 4
1-2 Product Application ------------------------------------------------------------------------- 4
2. PCIe-FRM24_C Board Function
2-1 Block Diagram ------------------------------------------------------------------------ 5
2-2 Camera Link ------------------------------------------------------------------------ 6
2-3 Camera Link Cable & Connector ----------------------------------------------------------- 9
2-4 Camera Link & PCIE-FRM24_C ------------------------------------------------------------ 10
2-5 Encoder Trigger Controller ----------------------------------------------------------- 12
3. PCIe-FRM24_C Board Description
3-1 PCIe-FRM24_C Board Layout -------------------------------------------------------------- 14
3-2 Device Features ------------------------------------------------------------------- 15
3-3 Connector Pin out
3-3-1 J1 Connector ----------------------------------------------------------------- 17
3-3-2 J2 Switch ----------------------------------------------------------------- 17
3-3-3 J3(MDR) Connector ----------------------------------------------------------------- 18
3-3-4 J4 Connector -------------------------------------------------------------------- 20
3-3-5 J5 Connector --------------------------------------------------------------------- 22
3-3-6 J6 Connector ----------------------------------------------------------------------- 21
3-3-7 J7(MDR) Connector ----------------------------------------------------------------- 22
4. Installation
4-1 Product Contents ----------------------------------------------------------------------- 24
4-2 Installation Process ------------------------------------------------------------------------ 25

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5. Sample Program ---------------------------------------------------------------------- 29
5-1 Image Display Function ----------------------------------------------------------------------- 29
5-2 Image Option Function ----------------------------------------------------------------------- 33
5-3 DIO Function ----------------------------------------------------------------------- 35
5-4 CC/Trig Function ----------------------------------------------------------------------- 36
5-5 UART Function ----------------------------------------------------------------------- 40
5-6 Grabber Pattern Function ------------------------------------------------------------------ 41
5-7 Set Hsync/DE Function --------------------------------------------------------------------- 43
Appendix
A-1 Board Size --------------------------------------------------------------------- 44
A-2 Repair Regulations --------------------------------------------------------------------- 45
References ------------------------------------------------------------------------ 46

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1. Introduction
PCIe-FRM24_C is an upgrade board of the company's PCIe-FRM24_C. It is an image acquisition
device that applies GEN2 PCI Express, which is twice as fast as the existing PCI Express, and supports
cameras compatible with Full configuration Camera Link. PCIe-FRM24_C acquires images in real time
and transfers them directly to system memory. The easy installation method and fast image transfer
make it a suitable device to meet the needs of the industry with low cost and high efficiency.
The sample program provided by the DQ system is provided in the form of a source so that the API
provided to use the board can be tested briefly, so the user can modify it and use it. Refer to Chapter
5 Sample Program for detailed explanation.
The MDR 26-pin connector can be connected to a Camera Link compatible camera, and the Mini-
Circular connector can supply the camera's power (12V). In addition, it has the function of external
control by providing 8 Digital Inputs and 8 Digital Outputs. Refer to 3-3 Connector Pin-Out for
detailed explanation.
This is a board that transmits the captured image frame to the PC through the PCI Express 1x
interface method in conjunction with the standard Camera-link camera. The operation of the board is
controlled by the program API, and the figure below shows the interlocking operation of the board.
Camera-Link
Camera
Full
PCI Express
GEN x4
MDR-26 Camera-Link
Connecter
Base
[Figure 1-1 PCIe-FRM24_C Board Usage]
In [Figure 1-1], PCIe-FRM24_C is installed in the PCI Express slot in the PC and receives from the
camera through the image frame through the Camera-Link standard interface. It is responsible for
transmitting the received data to the application program through the PCI Express GEN2 4x interface.

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1-1 Product Features
Items
Description
Remark
Hardware
PC Interface
PCI Express GEN2 4x
Data rate of up to maximum
2Gbytes/sec
Operation Power
PC Power
+3.3V (Max 1.1A)
+12V (Max 1A).
Video Interface
Base/Medium/Full Camera Link
2 MDR 26pin connector
Feature
Area/Line Scan Camera
Pixel Clock : 20 ~ 85MHz
On-board Memory
512MB
Communication
UART(Data bit 8, 1 start, 1 stop, No
parity, 9600/19200/38400/57600
/115200bps)
Simultaneous use of
boards
Max. 4
Software
OS
Windows 2000/XP/7/8/10 (32/64bit)
API
Windows Client DLL API
Development
Support
Sample Program
VC++
Environmental conditions
Operating temperature
range
0 ~ 60℃
Storage temperature
range
-20 ~ 80℃
Humidity range
5 ~ 95%
Non-condensing
Board size
139.75mm X 96.5mm
PCB Board Size
1-2 Product Applications
Image recognition (Pattern, particle, etc.)
Inspection equipment (Sensor, Semiconductor, Device etc.)
Security Solution
Black and White, Color Image Display
Medical Image Capture (X-ray, Supersonic etc.)

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2. PCIe-FRM24_C Board Function
2-1 Block Diagram
As shown in the figure below, in the case of PCIe-FRM24_C, FPGA Core Logic is in charge of
overall control. Main functions include Frame Data reception, UART data transmission/reception
for this, Camera Control signal and external trigger.
These functions are performed using API in PC through PCI Express GEN2 4x interface.
PCI Target
/ Master
PCI Express
4x BUS Local Bus
Address
Data(Mem,I/O)
Reserved
(0x00 –0x5F)
Reserved
(0x70 –0xAF)
UART
(0x60)
Camera Link(LVDS)
(0xC0)
Interrupt controller
DIO
(0xD0)
Ext. Address, Data, Control
Local BUS
Interrupt
Controller
(0xb0)
INT sources in Chip
IO Decoder
MEM Decoder
To each IO
Module
PCIe-FRM24_C INTERNAL BLOCK - FPGA
DPRAM
From Ext.
CLOCK syn.
MEM Decoder
BUS Mux
Reserved
(0xE0 –0xFF)
[Figure 2-1. PCIe-FRM24_C Block Diagram]
The FPGA core logic is programmed using JTAG, and the logic program is saved in FPGA
Program Logic and loaded when power is applied.

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2-2 Camera Link
Camera Link is a communication interface developed for use in vision applications. In the past,
camera manufacturers and frame grabber manufacturers used their own standard connectors and
cables. This caused a lot of confusion and cost increase for users. In order to resolve this
confusion, increasing data rate, and confusion in data transmission, the specifications of the
Camera Link interface are the specifications of cable or connector assembly, transmission speed
and It was made with regulations such as transmission method.
Many digital video solutions currently use LVDS (Low Voltage Differential Signal) communication
defined by RS-644. RS-644 LVDS has become the Camera Link standard by improving the existing
RS-422 method, which had inconvenient cables and limited transmission speed. LVDS can transmit
data at high speed by using a differential signal with a low voltage swing. Compared to the
existing single-ended signal using one line, the differential signal transmits the signal using two
complementary lines. This transmission structure has the characteristics of large-scale common-
phase voltage rejection, low power consumption, and excellent noise immunity, which is
impossible with single-ended systems that only reference ground for data transmission.
The camera link has several configurations according to the amount of data to be transmitted.
In case of Base Configuration, it is composed of 28 bits including 24-bit pixel data, Data Valid,
Frame Valid Line Valid, 3-bit video sync signal line of Line Valid, and Line Valid, and one reserved
signal line, and can transmit 2.04 Gbit/s (256 MB/s). Medium Configuration can transmit a 48-bit
video signal at 4.08Gbit/s (510Mb/s), and Full Configuration can transmit a 64-bit video signal at
5.44Gbit/s (680MB/s). Camera Link requires two cables to carry more than the Medium
specification.
The transceiver stage converts this 28/48/64 bit CMOS/TTL data into 4/8/12 LVDS data streams.
The converted signal is transmitted to the MDR cable according to the Transmit Clock, and the
receiver on the other side converts these 4/8/12 LVDS data into a 28/48/64 bit CMOS/TTL parallel
signal according to the Receive Clock. This channel link technology is being used as a low-cost
chipset that is easy to learn and portable, so that it can be used immediately.
Camera Link interface includes Base Configuration, Medium Configuration, and Full
Configuration. Base Configuration uses four RS-644 LVDS pairs for transmitter/receiver and camera
control as shown in [Figure 2-2], and two RS-644 LVDS pairs for communication between camera
and frame grabber. . The data transmitted serially through the 26-Pin MDR Cable is changed to
28-bit parallel image data at the Receive end of the frame grabber and used.

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[Figure 2-2. Base Camera Link Block Diagram]

PCIE-FRM24_C User’s Manual
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[Figure 2-3. Full Camera Link Block Diagram]

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2-3 Camera Link Cable & Connector
Camera Link The connection between the camera and the PCIe-FRM24_C board uses a 26 Pin
MDR (Mini D Ribbon) cable. The camera link cable consists of a twin-axial shielded cable and two
MDR 26-male plugs. [Figure 2-4] below is a commonly used camera link cable.
[Figure 2-5] is a 26-Pin Male MDR Connecter located at both ends of the cable, and [Figure 2-
6] is a 26-Pin Female MDR Connector, located at the camera or frame grabber. As shown in the
figure, the pin numbers are cross-connected, so that the transmitter and receiver terminals of the
camera and frame grabber signal lines are cross-connected.
[Figure 2-4. MDR-26 Camera Link Straight Cable]
[Figure 2-5. MDR-26 Cable Pin Map]
[Figure 2-6. MDR-26 Connector Pin Map Opposite Connector)]

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2-4 Camera Link & PCIe-FRM24_C
PCIe-FRM24_C supports Camera Link Base/Medium/Full Configuration. Base Configuration
consists of 4 LVDS signal lines serializing 28-bit parallel signals including 24 data bits and 4 enable
signals Frame Valid, Line Valid, Data Valid, and a spare, and 1 LVDS signal line for synchronizing
with the camera. , Asynchronous serial communication including 4 CC (Camera Control) signals
and 2 LVDS lines for communicating with the camera transmits a total of 11 LVDS signal lines
through one MDR cable. To use Medium/Full Configuration, another MDR cable is used and it has
a total of 64bit wide video path.
The transmitted signal is parallelized (Frame Valid, Line Valid, Data Valid, and a spare) of 12
video LVDS serial signals into 64-bit parallel video signals and control signals for each
specification (Frame Valid, Line Valid, Data Valid, and a spare) through the Channel Link chip in
PCIe-FRM24_C Deserilize). Also, one LVDS to synchronize the signal between the camera and PCIe-
FRM24_C makes a clock signal, and the remaining cameras control signals and communication
signals are converted into general TTL signal levels and used.
CCx+
CCx-
Camera Control
The figure shows the Camera Control output circuit that can send the control signal from the
PCIe-FRM24_C board to the Camera through the Camera-link cable. A total of 4 digital outputs
are output through the differential method. Each output is mapped to a digital output and
becomes an output. Each bit position is shown in [Figure 2-7] below.
CC1+
CC1-
CC_D0
CC2+
CC2-
CC_D1
CC3+
CC3-
CC_D2
CC4+
CC4-
CC_D3
[Figure 2-7. Camera Control LVDS Digital Output Circuit]

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The figure below shows the circuit that uses the serial input signal input through the Camera-
link cable as a general input on the PCIe-FRM24_C board.
[Figure 2-8. Serial Communication LVDS Digital Output Circuit
PCIe-FRM24_C supports Base Configuration including the following bit allocation.
1, 2 ,or 3 Pixels (or Taps) at 8 Bits/Pixel
1 or 2 Pixels (or Taps) at 10 Bits/Pixel
1 or 2 Pixels (or Taps) at 12 Bits/Pixel
1 Pixel (or Tap) at 14 Bits/Pixel
1 Pixel (or Tap) at 16 Bits/Pixel
24 Bits RGB
PCIe-FRM24_C supports Medium Configuration including the following bit allocation.
4 Pixels (or Taps) at 8 Bits/Pixel
3 or 4 Pixels (or Taps) at 10 Bits/Pixel
3 or 4 Pixels (or Taps) at 12 Bits/Pixel
30 Bits RGB
36 Bits RGB
PCIe-FRM24_C supports Full Configuration including the following bit allocation.
8 Pixels (or Taps) at 8 Bits/Pixel

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2-5 Encoder Trigger Controller
The PCIe-FRM24_C board is an external digital input/output device (Motion Controller, Digital
I/O board, etc.) that can control the camera using 4 pairs of Isolated Photo-coupler input signals
and 6 TTL level signal lines isolated by photo-couplers.
The PCIe-FRM24_C can use an external trigger when using a line scan camera.
The figure below shows the trigger input/output signal input through connector J4 on the board
and the C.C (Camera Control) signal, which is a commonly used camera link control signal.
PCIe-FRM24_C
CC1
CC2
CC3
CC4
Page_Trigger_In
Line_Trigger_In
Line_Trigger_Out
FPGA Core
Logic Camera
Motion Controller
Or
Digital I/O External
Trigger
[Figure 2-9. CC Control]
The PCIe-FRM24_C board uses 4 pairs of isolated photo-coupler input signal lines insulated by
a photo-coupler to receive an external motor signal and use it as a trigger signal. The photo-
coupler circuit is shown below. The output current must be used within 10mA.
EA, EB, EZ,
REV EA+, EB+, EZ+,
REV+
EA-, EB-, EZ-,
REV-
680
[Figure 2-10. Photo-coupler Circuit]
Note) Trigger control may vary depending on the type of motion controller or camera,
so please inquire with DAQ system when using it.

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A rotary encoder is used to detect the rotational direction and speed of a rotating object such
as an electronic volume or motor. When the rotating shaft is turned, two pulse signals that can
discriminate left and right come out in proportion to the speed. It is divided into single phase,
A/B phase and A/B/Z phase, and the resolution is determined according to the number of pulses
indicating how many A/Bs are generated in one rotation.
PCIe-FRM24_C
OUT
TTL(3.3V)
Line Drive
Encoder
Encoder IN
Line Driver
PHOTO
FPGA Core Logic Camera
Motion Controller
Or
Digital I/O
A, B phase : Forward movement A, B phase : Backward movement
A Phase
B Phase
A Phase
B Phase
[Figure 2-11. Encoder A/B Phase Clockwise/Counter Clockwise]
A and B operates the difference of 90 degree as shown in the figure above.
When "B" is low and "A" is high, it move counter-wise direction
When "B" is high and "A" is high, it move count counter-wise direction.
Z also used as a trigger because Z shows the one on the wheel once.
[Figure 2-12. Encoder Z Phase (Phase)]

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3. PCIE-FRM24_C Board Description
Each important board function is briefly described. For detailed function information, please refer to
the parts specification.
3-1 PCIE-FRM24_C Board Layout
[Figure 3-1. PCIe-FRM24_C Layout]
There are several LEDs on the board, and the description of each is as follows.
D12 : Blinks when GEN2 is recognized
D14 : Blinks when x1 device is recognized
D16 : Blinks when x2 device is recognized
D15 : DDR Out DE
D17 : DDR Out Vsync
D19 : Indicates output Vsync

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3-2 Device Features
(1) MDR-26 Connecter : J3, J7
Camera Link Base (J7), medium/Full (J3) Signal Connector
(2) LVDS Link : U7, U10, U14
Receive an image frame.
(3) FPGA : U13
All of the board functions are controlled by the Logic program of the FPGA.
(4) DDR Memory : REF1, REF2
It has 256MB of image buffer memory.
(5) Line Trigger Connecter : J4
Configure input/output circuits for connection with external devices.
(6) Regulator : U8, U13
It supplies the power used by the board.
(7) Differential Line Driver : U18
Differential CC (Camera Control) signal line is used by changing it into a single signal.

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3-3 Connector Pin-out
This section describes the connectors and jumpers used in PCIe-FRM24_C. As for main
connectors, there are MDR 26pin connectors J3 and J7 connectors for Camera Link connection, and
26pin Box Header connector for external trigger I/O connection.
[Figure 3-2] shows the bracket that interfaces with the board and the connection connector.
3
10
9
8
7
6
1
2
5
4
19
18
17
16
15
14
13
12
1124
23
22
21
20
26
25
3
10
9
8
7
6
1
2
5
4
19
18
17
16
15
14
13
12
1124
23
22
21
20
26
25
[Figure 3-2. PCIe-FRM24_C Front View]

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3-3-1 J1 Connector
J1 is a JTAG (Joint Test Action Group) connector and is used to update the FPGA program
on the board. Do not use when operating the board normally.
3-3-2 J2 Switch
PCIE-FRM24_C board is designed to use up to 4 PCIe-FRM24_C boards simultaneously in
one system (PC). Each board classification can be set through the 4-pin DIP switch in the
board.
1
ON
OFF
2
[Figure 3-3. J2 Switch]
[Table 1. J2 Switch]
1
2
Description
OFF
OFF
Board No. 0
ON
OFF
Board No. 1
OFF
ON
Board No. 2
ON
ON
Board No. 3

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3-3-3 J3(MDR26) Connector
The figure below shows the pin map of the J3 connector of the board used when
Medium/Full Configuration Camera Link is used. All pin specifications are input/output based
on the Camera Link standard, so please refer to the Camera Link standard document for
details.
3
10
9
8
7
6
1
2
5
4
19
18
17
16
15
14
13
12
1124
23
22
21
20
Inner shield Inner shield
26
25
Z0-
TERMI+
YCLK-
Y3-
Y2-
Y1-
Y0-
Inner shield
Frame Grabber
Z0+
TERMI-
YCLK+
Y3+
Y2+
Y1+
Y0+
Inner shield
Z3+
ZCLK+
Z2+
Z1+
Z3-
ZCLK-
Z2-
Z1-
[Figure 3-3. PCIe-FRM24_C J3 Connector Pin-out]

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[Table 2. J3 Connector]
Pin No
Name
Description
Remark
1
Inner Shield
Cable shield
2
Z3+-
Camera link LVDS receive data11+
3
ZCLK+
Camera link LVDS receive clock+
4
Z2+-
Camera link LVDS receive data10+
5
Z1-
Camera link LVDS receive data9+
6
Z0+
Camera link LVDS receive data8+
7
TERMI-
Serial to Camera-
8
Y3+
Camera link LVDS receive data7 +
9
YCLK+
Camera link LVDS receive clock +
10
Y2+
Camera link LVDS receive data6 +
11
Y1+
Camera link LVDS receive data5 +
12
Y0+
Camera link LVDS receive data4 +
13
Inner Shield
14
Inner Shield
15
Z3-
Camera link LVDS receive data11-
16
ZCLK-
Camera link LVDS receive clock-
17
Z2-
Camera link LVDS receive data10-
18
Z1-
Camera link LVDS receive data9-
19
Z0-
Camera link LVDS receive data8-
20
TERMI+
Serial to Camera+
21
Y3-
Camera link LVDS receive data7-
22
YCLK-
Camera link LVDS receive clock-
23
Y2-
Camera link LVDS receive data6-
24
Y1-
Camera link LVDS receive data5-
25
Y0-
Camera link LVDS receive data4-
26
Inner Shield
(Note) For more information, refer to Camera Link Standard Specification.