DAQ PCI-FRM01 User guide

Application Note (AN241)
PCI-FRM01 Register Level Application Guide
2005 DAQ system, all rights reserved. http://www.daqsystem.com
PCI-FRM01 Register Level
Application Guide (Ver1.1)
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Copyrights 2005 DAQ system, All rights reserved.

Application Note (AN241)
PCI-FRM01 Register Level Application Guide
2005 DAQ system, all rights reserved. http://www.daqsystem.com
-- Contents --
1. PCI BUS Address Space
2. PCI-FRM01 Functional Block Diagram
3. I/O Address Usage
4. Memory Address Usage
5. UART Usage
6. Interrupt Controller Usage
7. LVDS(Camera Link) Interface Usage
8. DIO(Digital Input/Output) Usage
References

Application Note (AN241)
PCI-FRM01 Register Level Application Guide
2005 DAQ system, all rights reserved. http://www.daqsystem.com
1. PCI BUS Address Space
As it uses CPU of the x86 system which we use mainly, it can classify greatly it to memory and I/O
area. In order to support Plug & Play in case of PCI bus that has a special configuration. It can make
the resource and device state control register etc.
Memory
Area
I/O Area Configuration
Area
4G
64K
64DWORD
The PCI-FRM01 use a memory and I/O that have been assigned to system for operation, the
contents are as follows that they required.
Address Area
Requirements
Remark
Memory
Maximum 64MByte
I/O
256 Byte
Configuration
128 Byte

Application Note (AN241)
PCI-FRM01 Register Level Application Guide
2005 DAQ system, all rights reserved. http://www.daqsystem.com
2. PCI-FRM01 Functional Block Diagram
The address area assigned by the system in the PCI-FRM01 division is shown in the figure below.
Most peripheral control and status register is in the I/O area, only SDR SRAM is in the memory area.
The configuration area can not be used in the most application because of only using resources for the
system boot time.
PCI Target
PCI BUS
Local Bus
Address
Data(Mem,I/O)
Reserved
(0x00 ?0x5F)
Reserved
(0x70 ?0xAF)
UART
(0x60)
Camera Link(LVDS)
(0xC0)
Interrupt controller
DIO
(0xD0)
Ext. Address, Data, Control
Local BUS
Interrupt
Controller
(0xb0)
INT sources in Chip
IO Decoder
MEM Decoder
To each IO
Module
PCI-FRM01 INTERNAL BLOCK - FPGA
DPRAM
From Ext.
CLOCK syn.
MEM Decoder
BUS Mux
Reserved
(0xE0 ?0xFF)
PCI-FRM01 of the figure shows the function block, which features the dotted area is reserved for
future feature additions.

Application Note (AN241)
PCI-FRM01 Register Level Application Guide
2005 DAQ system, all rights reserved. http://www.daqsystem.com
3. I/O Address Usage
The below table indicates the base address of the peripheral device that is located I/O area address.
The table below the I / O area is located at the address indicates the base address of the peripheral
device. All I / O registers are 32-bit input / output processing.
Reserved area for future use00h-5Fh
Description
I/O Address
Offset Base
Reserved
Function
60h
70h-AFh
Universal asynchronous receiver transmitter (RS232C)
Reserved area for future use
UART
Reserved
Frame grabber LVDS interfaceC0h
D0h
E0h-FFh
Photo-coupler isolated Digital input/Output
Reserved area for future use
Camera Link
DIO
Reserved
Comment
B0h Interrupt controllerInterrupt

Application Note (AN241)
PCI-FRM01 Register Level Application Guide
2005 DAQ system, all rights reserved. http://www.daqsystem.com
4. Memory Address Usage
SDR SRAM for future enhancements can be used.
SDR SDRAM 64M Byte0h - 4000000h
Description
Memory Address
Space
Undefined
Model
Reserved
Comment
UART (0x60)
LVDS (0xC0)
DIO (0xD0)
Interrupt (0xB0)
Reserved FFh
00h
Reserved
64M Byte
000000h
3FFFFFFh
Memory region I/O region
Reserved
Reserved

Application Note (AN241)
PCI-FRM01 Register Level Application Guide
2005 DAQ system, all rights reserved. http://www.daqsystem.com
5. UART Usage
The PCI-FRM01 has UART (9600BPS, 1 stop, 1 start, 8 data bit, no parity).
UART
Transmit Data(Write) / Received Data(Read)60h
Description
I/O Address
Offset
Function
64h
68h
6Ch
Baud generator x”82"
Control Register
Status Register
Data Buffer
Register
Baud
Control
Status
(1) Data Buffer
(2) Baud rate generator
40Mhz
Initial Value : x”82”
(3) Control
01831
Reserved
UART Control Register Bit Position & Usage 234567
RETE
Bit
Name
Description
Default Value
0
RE
Receiver Interrupt Enable
‘0’
1
TE
Transmitter Interrupt Enable
‘0’
31 - 2
Reserved
For future use
All ‘0’
(4) STATUS
831
Reserved
UART STATUS Register Bit Position & Usage
PEFE RIRBTITB
01234567
Bit
Name
Description
Default Value
0
RI
Receive Interrupt
‘0’
1
RB
Receive Busy
‘0’
2
PE
Parity Error(Unused)
‘0’

Application Note (AN241)
PCI-FRM01 Register Level Application Guide
2005 DAQ system, all rights reserved. http://www.daqsystem.com
3
FE
Frame Error
‘0’
4
TI
Transmit Interrupt
‘0’
5
TB
Transmit Busy
‘0’
31 - 2
Reserved
For future use
All ‘0’

Application Note (AN241)
PCI-FRM01 Register Level Application Guide
2005 DAQ system, all rights reserved. http://www.daqsystem.com
6. Interrupt Controller Usage
PCI-FRM01 has interrupt controller to handle the hardware interrupt for each I/O device.
When you use these interrupts, eliminating the use of polling overhead of the process can be reduced.
INTERRUPT
Interrupt Status Register (Read Only)B0h
Description
I/O Address
Offset
Function
B4h
B8h
BCh
Interrupt Status Clear (Write Only)
Interrupt Enable Register (Read/Write)
Interrupt Source Indicatior(Read Only)
INT_STA
Register
INT_SEL
INT_EN
INT_SRC
To control 82C55 ports, first the mode have to set up through the control register. To all setup, most
significant bit(MSB) is set to high “1” and write to the control register. If the MSB is “0”, it will be
command of PORTC. (For more information, refer 82C55 manual)
When the first time power is applied, all ports will be the input and operation modes will be 0.
(1) INT_STA (Interrupt Status)
Indicates the current interrupt device that requires. To appear in the status register will have to make
the handle. When the write operation, status bits are cleared.
15 01234567891011121314
G Status S0
31
Reserved
INTERRUPT Status Register Bit Position & meaning
S14
16
Bit
Name
Description
Default Value
0
Reserved
‘0’
1
Reserved
‘0’
2
Reserved
‘0’
3
Reserved
‘0’
4
Reserved
‘0’
5
Reserved
‘0’
6
UART
Differential RS232C interface
‘0’
7
Reserved
‘0’
8
Reserved
‘0’
9
Reserved
‘0’
10
Reserved
‘0’

Application Note (AN241)
PCI-FRM01 Register Level Application Guide
2005 DAQ system, all rights reserved. http://www.daqsystem.com
11
Interrupt
Reserved
‘0’
12
LVDS
Reserved
‘0’
13
Reserved
‘0’
14
Reserved
‘0’
15
Global
When any of the above interrupt sources need
the processing, it will be changed '1'.
‘0’
31-16
Reserved
For future use
All ‘0’
For more information, refer AD5324 manual.
(2) INT_SEL
Select the Level Trigger and Edge Trigger of Interrup Input.
01234567891011121314
Status Clear C0
31
Reserved
INTERRUPT Clear Register Bit Position & meaning
C14
16 15
R
If it is “0”, it is a Level Trigger. If it is “1”, it is a Rising Edge Trigger.
(3) INT_EN
Each interrupt source is to enable the interrupt.
15 01234567891011121314
G Enable E0
31
Reserved
INTERRUPT Enable Register Bit Position & meaning
E14
16
If each bit is ‘1’, the device interrupt for corresponding bit will be enabled.
The bit 15 is Global Interrupt Enable. This bit is set to '1' to enable all interrupts.
(4) INT_SRC
INT_STA appear on the register, the interrupt request output of the device is latched at the rising
edge of the signal. Thus, it is not Level Trigger, it is an indication of Edge Triggere.
So, it can be cleared and requested the interrupt. On the other hand, in the INT_SRN, it represents
current output signal state of the current device.
01234567891011121314
Interrupt Source S0
31
Reserved
INTERRUPT Source Indicator Bit Position & meaning
S14
15

Application Note (AN241)
PCI-FRM01 Register Level Application Guide
2005 DAQ system, all rights reserved. http://www.daqsystem.com
7. LVDS(Camera Link) Interface Usage
LVDS(Low Voltage Differential Signal) Interface control
LVDS
LVDS Data registerC0h
Description
I/O Address
Offset
Function
C4h
C8h
CCh
LVDS Command register
LVDS Internal counter register
LVDS Status register
LVDS_DATA
Register
LVDS_CMD
LVDS_CNT
LVDS_STA
01234567891011121314
Data
LVDS Data Register Bit Position & meaning
D31
1516171819202122232425262728293031
D0
0123431
Reserved
LVDS Command Register Bit Position & meaning 5
DI ERS
Bit
Name
Description
Default
Value
0
Enable
Used for simulation
‘0’
1
Reset
‘0’
2
Data
Enable
‘0’
3
Interrupt
Enable
‘0’
4
Start
‘0’
15 01234567891011121314
Line Counter
LVDS Internal counter Register Bit Position & meaning
L15
16171819202122232425262728293031
Pixel Counter P0P15 L0

Application Note (AN241)
PCI-FRM01 Register Level Application Guide
2005 DAQ system, all rights reserved. http://www.daqsystem.com
LF DRIRH
01234567891011121314
PC AddressLVDS Address
LVDS Status Register Bit Position & meaning
A10V
16171819202122232425262728293031 15
A0
Bit
Name
Description
Default
Value
10-0
PC address
Dual port ram address
11
Done
‘0’
12
Data
Ready
‘0’
13
Lvalid
‘0’
14
Fvalid
‘0’
15
Interrupt
‘0’
27-16
LVDS
address
Dual port ram address
28
Reserved
29
Data
ready
‘0’
30
Hsync
‘0’
31
Vsync
‘0’

Application Note (AN241)
PCI-FRM01 Register Level Application Guide
2005 DAQ system, all rights reserved. http://www.daqsystem.com
8. DIO(Digital Input/Output) Usage
The PCI-FRM01 has 16 Input port and 8 Output port at the Photo-coupler isolated DIO(Digital
Input/Output) function.
DIO
4Bit Photo-coupler output, 4Bit LVDS output PortD0h
Description
I/O Address
Offset
Function
D4h
D8h
DCh
6Bit Photo-coupler input , 10Bit LVDS input Port
For future use
For future use
Out Port
Register
In Port
Reserved
Reserved
01
Used
431
Reserved
DIO Out Port Register Bit Position & Usage 234567
Bits 3-0 are the Photo-coupler isolated Digital outputs, bits 7-4 are the LVDS outputs. Please refer to
the manual for the circuit configuration.
0
Used
1631
Reserved
DIO In Port Register Bit Position & Usage 2345 16789101112131415
Bits 5-0 are the Photo-coupler isolated Digital Inputs, bits 15-8 are the LVDS Inputs. Please refer to
the manual for the circuit configuration.

Application Note (AN241)
PCI-FRM01 Register Level Application Guide
2005 DAQ system, all rights reserved. http://www.daqsystem.com
References
1. Specifications of the Camera Link Interface Standard for Digital Cameras and Frame Grabbers
-- PULNix America, Inc.
2. Channel Link Design Guide
-- National Semiconductor
3. PCI-EK01(A/B) User’s Manual
-- DAQ system
4. DS90CR285/286 chip manual
-- National Semiconductor
5. PCI-FRM01 User’s manual
-- DAQ system