DAQ SB3-FRM13 K Series User manual

USB3-FRM13_K Users Manual (Rev 1.0)
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USB3-FRM13_K
User’s Manual
Windows, Windows2000, Windows NT and Windows XP are trademarks of Microsoft. We acknowledge that the
trademarks or service names of all other organizations mentioned in this document as their own property.
Information furnished by DAQ system is believed to be accurate and reliable. However, no responsibility is assumed by DAQ
system for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or copyrights of DAQ system.
The information in this document is subject to change without notice and no part of this document may be copied or
reproduced without the prior written consent.
Copyrights 2005 DAQ system, All rights reserved.

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-- Contents –
1. Introduction
2. USB3-FRM13_K Function
2.1 Block Diagram
2.2 Camera Link
2.3 Camera Link and USB3-FRM13_K
2.4 Camera Link Cable
2.5 PoCL
2.6 Area Trigger Mode
3. USB3-FRM13_K Board Description
3.1 USB3-FRM13_K Layout
3.2 Functional Blocks
3.3 Connector Pin-out
3.3.1 CN1 Connecter
3.3.3 J1(MDR26) Connecter
3.3.4 J2(MDR26) Connecter
3.3.5 J3 Connecter
3.3.6 J8 Connecter
3.3.2 SW1 Switch
4. Installation
4.1 Package Contents
4.2 Installation Sequence
5. Sample Program
5.1 Image Functions
5.2 Multi-board Functions
5.3 Status Functions
5.4 I2C Read/Write Functions
5.5 Trigger Configure Functions for Line Scan Camera
Appendix
A.1 General Specification
A.2 Physical Dimension
Reference

USB3-FRM13_K Users Manual (Rev 1.0)
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1. Introduction
USB3-FRM13_K is an image acquisition board to support Full configuration camera Link compatible
cameras. Acquire images in real time and directly transferred to the system memory. Easy installation
and fast image transfer is a suitable device to meet the needs of the industry's low-cost, high-efficiency.
DAQ system provides a sample program to use the board briefly so you can test the API provided
insource form, so the user can be used to modify. Please refer to Chapter 5 for a detailed description of
this sample program.
Mini MDR 26-pin connector connects to Camera Link compatible camera. The bottom connector(J8)
connects to Base Camera Link Configuration. The upper connector(J4) connects to Full/Medium
Camera Link Configuration with bottom connector. In addition, by providing four pairs RS-422 signal
lines and Line/Area Trigger signals of 6 TTL level, have the ability to control the external. Please refer
to Chapter 3.3 for a detailed description of this connectors.
The image frames that took in conjunction with a standard Camera-link send to PC by Super
Speed(5Gbps) USB3.0 interface method. The board operation is controlled by the program API, the
figure below shows a picture of the interlocking action of the board.
[Figure 1-1. USB3-FRM13_K Board Usage]

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[USB3-FRM13_K Features]
Supports Camera Link Base Configuration Camera
Supports Camera Link Medium/Full Configuration Camera
Support Area Scan Camera, Line Scan Camera
USB 3.0 Specification (10x faster than USB2.0)
256MByte Image Buffer
Acquisition pixel clock rates up to 85MHz
Pixel Clock : 20 ~ 85MHz
Supports 1 ~ 10tap 85Mhz
Power by USB-B type connecter or Single 5V operation
Fully Plug-and-Play
UART(Data8 bit, 1 start, 1 stop, No parity, 600/19200/38400/57600/115200bps)
Rx/Tx
External Device Interface : 4 TTL Digital Input/Output, and 2 TTL trigger Input
Signals and 4-pair RS-422
O.S : Windows XP SP1, Windows 7
Convenient Windows Application Programming Interface(DLL)
[Application]
Image Acquisition (Pattern, Particle etc.)
Inspection Equipment (Sensor, Semiconductor, Device etc.)
Security Solution
Black and White, Color Image Display
Medical Image Capture

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2. USB3-FRM13_K Function
2.1 Block Diagram
As shown in the following figure, main control of the board is performed in FPGA Core Logic.
The primary functions are writing to the DDR#1, DDR#2 memory after receiving the frame data
from two Mini MDR-26, and sent to PC by the request. These functions are performed by using
API through USB 3.0 Interface at the PC.
[Figure 2-1. USB3-FRM13_K Block Diagram]
Programming FPGA Core Logic is performed via the JTAG interface. The logic program of the
FPGA is saved in a flash ROM, it is located on the board and loaded at the power-up time.

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2.2 Camera Link
Camera Link is a communication interface for use in a vision application development. In the
past, the camera manufacturer and Frame Grabber manufacturers use their own standard
connectors and cables. This has caused a lot of confusion and increased costs to users. In order to
eliminate this confusion and increase the data rate and data transmission trouble, the specifications
of Camera Link interface have been made to the regulations of cable or connector assembly
specifications, transfer speed, transfer method at the meeting of camera makers and Frame grabber
manufacturers.
Currently, many digital video solution use the LVDS (Low Voltage Differential Signal)
communication as defined RS-644. LVDS is a way to improve the existing RS-422 that had
intractable cable and transmission speed limit. RS-644 LVDS was the Camera Link standard. The
LVDS can be transferred the data at high speed using low voltage swing differential signal
Differential Signal. This is compared with the existing single-ended signal (Single-ended Signal)
using one of the lines, the differential signal transmits the signal using two complementary lines.
Such a transfer is characterized by excellent noise immunity, low power consumption, large in-
phase voltage transmission to refer only to the data transfer on the ground, however Single-ended
system is impossible.
Camera Link has multiple configuration with depending on the amount of data to be transferred.
Base Configuration consists of 28 bits, including a 24-bit pixel data and 3-bit video sync signal
lines of the Data Valid, Frame Line Valid, Line Valid, one reserved signal line, and can transmit
2.04Gbit / s (256MB / s). Medium Configuration can be transmitted the 48bit video signal to
4.08Gbit/s(510Mb/s), Full Configuration can be transmitted the 64bit video signal to
5.44Gbit/s(680MB/s). In particular, the Deca configuration allows 6.8 Gbit /s. It can transfer at
(850MB/s). Camera Link requires two cables to transfer more than Medium Specifications.
Transmitter part is converted to LVDS data stem’s 4/8/12 from 28/48/64 bit CMOS / TTL data
only. Converted signal is transmitted to MDR Cable in accordance with the Transmit Clock signal,
the opposite Receiver will be converted into parallel LVDS data of 28/48/64 bits of CMOS / TTL
according to the Receive Clock signal from 4/8/12 LVDS data. This Channel Link technology can
immediately take advantage of the low cost chip-set because easy to learn and easy to transplant.
Camera Link Interface includes Base Configuration, Medium Configuration, Full Configuration.
Base Configuration is used 4 RS-644 LVDS pairs for controlling the Transmitter/Receiver and
Camera like Figure 2-2, is used for communication between the camera and the frame grabber.
Transferred the data from serial 26-Pin MDR Cable, is used to change 28-bit parallel image data at

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the Receiver part of Frame Grabber.
[Figure 2-2. Base Camera Link Block Diagram]

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[Figure 2-3. Full Camera Link Block Diagram]

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2.3 Camera Link Cable & Connecter
The connection between the camera link cameras and USB3-FRM13_K board uses the 26 Pin
Mini MDR (Mini D Ribbon) cable. Camera Link cable consists of twin-axial shielded cable and 2
Mini MDR 26-male plug. The bottom of Figure 2-4 Camera Link cable is typically used.
26-Pin Mini MDR Connecter is located at the end of the cable as like Figure 2-5, Figure 2-6 is 26-
Pin Mini MDR Connecter, placed at the Camera or Frame Grabber. As shown in the figure, Pin
numbers are cross-linked to each other, Transmitter and Receiver of Camera and Frame Grabber
signals are connected cross each other.
[Figure 2-4. Mini MDR-26 Camera Link Straight Cable]
[Figure 2-5. Mini MDR-26 Cable Pin Map]
[Figure 2-6. Mini MDR-26 Connecter Pin Map (Opposite Connector)]

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2.4 Camera Link and USB3-FRM13_K
USB3-FRM13_K supports Camera Link Base/Medium/Full Configuration. Base Configuration,
24 data bits and four enable signals Frame Valid, Line Valid, Data Valid and a spare, including 28-
bit parallel signals serialized four LVDS signal lines and one LVDS signal line to fit the camera
and synchronous LVDS signal lines including four CC (Camera Control) signal and full 11
includes two asynchronous serial communication to communicate with the camera LVDS lines, is
transmitted through one MDR cable. In order to use the MDR Medium / Full Configuration is
used other cable and has a total 64bit wide video path. Deca Configuration has 80bit wide video
path.
The transmitted signal is parallelized to 64-bit parallel image signal and Frame Valid, Line Valid,
Data Valid, and a spare for each specification from 12 image LVDS serial signal through channel
link chip of USB3-FRM13_K.
CCx+
CCx-
Camera Control
Above picture is a Camera Control output circuit from USB3-FRM13_K board to Camera for the
specific control of the Camera-link Cable.
The USB3-FRM13_K board has four differential digital outputs. Each output is mapped by
Digital output. Below picture[Figure 2-7] display that each bit position set.
CC1+
CC1-
CC_D0
CC2+
CC2-
CC_D1
CC3+
CC3-
CC_D2
CC4+
CC4-
CC_D3
[Figure 2-7. Camera Control LVDS Digital Output Circuit]

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The serial input signal through the Camera-link cable is used for general input circuit from
USB3-FRM13_K board.
[Figure 2-8. Serial Communication LVDS Digital Output Circuit]
2.5 PoCL
PoCL (Power over Camera Link) is to transmit the power to the cable such as the data transfer
cable to the camera. [Figure 2-9] shows the connection with theUSB3-FRM13_K and the
camera.
(a) Base Configuration PoCL Connection
(b) Full Configuration PoCL Connection
Camera Link Signals Power, Other Control Signals
[Figure 2-9. PoCL Connections]
This concept is similar the USB-powered devices to receive power from a power source such
as a Repeater or Frame Grabber. PoCL has an advantage of reducing the number of interfaces
required by the back of the camera. That is, using the four drain of the Camera Link cable wires

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(4 ground), the power cable can be removed from the camera. Not only it does not have any
effect the quality of data from the camera, but also it is very helpful in reducing the cost and size
of the system to remove the power source terminal.
[Figure 2-10. Connection without Power Cable]
Implementation of PoCL that is, power transfer is used by setting the Camera Link 1, 13, 14,
26 pins as [table 1,] and 1 and 26pins are used as the power(+ 12V). It can supply current of
330mAfor 12V, it can supply current of 400mAfor 10V as standard on 4W(watt),
For USB3-FRM13_K, PoCL function can be implemented in the Base Configuration
Connector. It is available for Base / Full Configuration camera.
[Table 1. Camera Link Connection for PoCL]
Pin
Camera Link Connector
PoCL Connector
1
Inner Shield
Power (nominal 12V DC)
26
Inner Shield
Power (nominal 12V DC)
13
Inner Shield
Power Return
14
Inner Shield
Power Return
13 12 11 10 9 8 6 5 4 3 2 17
26 25 24 23 22 21 19 18 17 16 15 1420
Power Lines
Power Return Lines
[Figure 2-11. PoCL Connector Pin Out]

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123 4 5 6 8 9 10 11 12 137
14 15 16 17 18 19 21 22 23 24 25 2620
Power Lines
Power Return Lines
[Figure 2-12. PoCL Cable Pin out]
In order to use a PoCL, generally it requires a transformation of the Frame Grabber (power
supply section) or a dedicated cable. Frame Grabber conversion is divided into the power by
changing the design of the product to include a power supply "safe power" or "dedicated power".
Difference between the two, in the case of of "safe power" is to add some of the sensor circuit in
order to detect the possible PoCL camera –it does not detect the camera and cable, there is no
power supply. "Dedicated power" is always supplied a power, but use a fuse in order to supply
the equipment that do not receive support.
[Table 2. Compatibility Table]
Frame Grabber
Camera
Cable
Operability
Switchable PoCL
Frame Grabber
Conventional
Conventional
OK
PoCL
OK
PoCL
Conventional
NOK
PoCL
OK
Dedicated PoCL
Frame Grabber
Conventional
Conventional
NOK
PoCL
NOK
PoCL
Conventional
NOK
PoCL
OK
Conventional
Frame Grabber
Conventional
Conventional
OK
PoCL
OK
PoCL
Conventional
NOK
PoCL
NOK

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2.6 Area scan camera Trigger Mode
External trigger setting ofArea scan cameras use a 11 pin of the J11 connector.
It can be set to level mode and Edge mode.
LEVEL Mode --- When Trigger input signal (TRIGGER IN) becomes H level, the image frames
start the input operation. When Trigger input signal is high after the image input
end operation, the image is continuously input.
TRIGGER_IN
FVAL(LVAL)
Camera
Output
Input Image
Frame 0 Frame 1 Frame 2 Frame 3 Frame 4
Frame 1 Frame 2 Frame 4
t
Start Frame
When FVAL valid
Detect Level
[Figure 2-13. Level Mode Timing]
EDGE Mode ---When the Trigger input signal (TRIGGER_IN) detects a change from L level to
H level, it starts the image input operation. When the Trigger input signal is
changed to the H level at the L after the image input operation is finished, it starts
again image input operation.
TRIGGER_IN
FVAL(LVAL)
Camera
Output
Input Image
Frame 0 Frame 1 Frame 2 Frame 3 Frame 4
Frame 1 Frame 4
t
Start Frame
When FVAL vaild
Detect Edge
[Figure 2-14. Edge Mode Timing]

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3. USB3-FRM13_K Description
In this chapter, the primary functions of the board are described briefly. For more information, refer to
the device specification.
3.1 USB3-FRM13_K Layout
[Figure 3-1. USB3-FRM13_K Layout]
The board has 6 LEDs to indicate the operation status.
D1 : turns on when power is applied to the board and the initialization ends up.
D2 : turns on when Horizontal synchronization signal detects. (Hsync)
It is a display for confirming the Hsync.
D3 : turns on when the Vertical Synchronization (Vsync) indicates a value divided by 1/16.
It is a display for confirming the Vsync.
D4 : turns on when power(3.3V) is applied to the board..
D6, 9, 12: For Test.

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3.2 Functional Blocks
(1) MDR-26 Connecter : J1, J2
Camera Link Base (J1), medium/Full (J2) Signal Connector
(2) LVDS Link : U2, U3, U4
It is protected a circuit that the interface of high voltage higher than 3.3V CMOS Logic is
exchanged to normal 3.3V Logic Level.
(3) FPGA : U6
All of the functions are controlled by the logic program of the FPGA.
(4) Regulator : U14, U20, U21
The Regulator is for supplying the power (3.3V) to the board.
(5) USB 3.0 Interface Chipset : U10
This block supports USB3.0 Super Speed interface.
(6) DDR Memory : REF1, REF2
After save the data in a frame unit, transfer to PC through FPGA.

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3.3 Connector Pin-out
The board has several connectors and jumpers to set. The USB3-FRM13_K board is equipped
with two main connecters, USB3 B-type connector for USB connection and Camera Link
connecter for Base/Medium/Full Camera Link connection. The board has several Jumpers for
external I/O and Image acquisition.
3.3.1 CN1 Connecter
The USB3-FRM13_K has a USB-B type connector for high speed USB connection.
[Figure 3-2] and [Table 1] shows the CN1 connector and its pin description.
USB B type
Connector
12
3 4
10 11
56789
[Figure 3-2. CN1 Connecter (USB3.0 standard powered-B type Front View)]
[Table 3. USB3.0 Standard Powered-B Connecter]
Pin
Signal Name
Description
Remark
1
VBus
+5V Power
+5V Power
2
USB D-
USB2.0 data (Negative)
USB2.0 Signal
3
USB D+
USB2.0 data (Positive)
USB2.0 Signal
4
GND
Ground for Power Return
USB Power GND
5
StdA_SSTX-
Super Speed Transmitter(Negative)
USB3.0 Signal
6
StdA_SSTX+
Super Speed Transmitter(Positive)
USB3.0 Signal
7
GND_DRAIN
Ground for Signal Return
USB Power GND
8
StdA_SSRX+
Super Speed Receiver(Positive)
USB3.0 Signal
9
StdA_SSRX-
Super Speed Receiver(Negative)
USB3.0 Signal
10
DPWR
Power Provided by Device
USB Power GND
11
DGND
Ground return for DPWR
USB Power GND

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3.3.2 J1(MDR26) Connecter
Figure [3-3] shows the board’s J1 connector pin-map.
All of the pin functions are based on the Camera link standard, so please refer to the Camera
link standard document for more description and information.
3
10
9
8
7
6
1
2
5
4
19
18
17
16
15
14
13
12
1124
23
22
21
20
PoCL(+12V) Inner shield
26
25
SerTFG-
SerTC+
Xclk-
X3-
X2-
X1-
X0-
PoCL(+12V)
Frame Grabber
SerTFG+
SerTC-
Xclk+
X3+
X2+
X1+
X0+
Inner shield
CC4-
CC3+
CC2-
CC1+
CC4+
CC3-
CC2+
CC1-
[Figure 3-3. USB3-FRM13_K J1 Connector Pin-out]

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[Table 4. J1 Connector Description]
Pin
Signal Name
Description
Remark
1
PoCL_Pin
Power over Camera Link(+12V)
2
CC4-
Camera Control output 4-
3
CC3+
Camera Control output 3+
4
CC2--
Camera Control output 2-
5
CC1+
Camera Control output 1+
6
SerTFG+
Serial to Frame grabber +
7
SerTC-
Serial to Camera-
8
X3+
Camera link LVDS receive data3 +
9
Xclk+
Camera link LVDS receive clock +
10
X2+
Camera link LVDS receive data2 +
11
X1+
Camera link LVDS receive data1 +
12
X0+
Camera link LVDS receive data0 +
13
Inner Shield
14
Inner Shield
15
CC4+
Camera Control output 4+
16
CC3-
Camera Control output 3-
17
CC2+
Camera Control output 2+
18
CC1-
Camera Control output 1-
19
SerTFG-
Serial to Frame grabber-
20
SerTC+
Serial to Camera+
21
X3-
Camera link LVDS receive data3-
22
Xclk-
Camera link LVDS receive clock-
23
X2-
Camera link LVDS receive data2-
24
X1-
Camera link LVDS receive data1-
25
X0-
Camera link LVDS receive data0-
26
PoCL_Pin
Power over Camera Link(+12V)
(Note) For more information, refer to Camera Link Standard Specification.

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3.3.3 J2(MDR26) Connecter
Figure [3-4] shows the board’s J2 connector pin-map.
All of the pin functions are based on the Camera link standard, so please refer to the Camera
link standard document for more description and information.
3
10
9
8
7
6
1
2
5
4
19
18
17
16
15
14
13
12
1124
23
22
21
20
Inner shield Inner shield
26
25
Z0-
TERMI+
YCLK-
Y3-
Y2-
Y1-
Y0-
Inner shield
Frame Grabber
Z0+
TERMI-
YCLK+
Y3+
Y2+
Y1+
Y0+
Inner shield
Z3+
ZCLK+
Z2+
Z1+
Z3-
ZCLK-
Z2-
Z1-
[Figure 3-4. USB3-FRM13_K J4 Connector Pin-out]