Datum bc630AT User manual

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bc630AT
Real Time Clock Module
User’s Guide
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Datum Inc bc630AT Real Time Clock Module 1-1
CHAPTER ONE
INTRODUCTION
1.0 GENERAL
The bc630AT Real Time Clock Operation and Technical Manual provides the following information:
•General Introduction.
•Installation and Setup Details.
•Operation and Software Interface Details.
•I/O Signal Information.
•Theory of Operation.
•Programming Examples.
•Drawing Set.
1.1 KEY FEATURES
The salient features of the bc630AT Real Time Clock include:
•Real Time Clock operation with microsecond precision.
•Decodes commonly used time code formats: IRIG B, IRIG A, NASA 36 and 2137.
•Master/Slave operation allows digital synchronization of multiple bc630AT's.
•Time base can be synchronized to external 1PPS or 1, 5, 10 MHz reference frequency.
•Continues to provide time, 'flywheels', during loss of the external time code source.
•Battery backed Real Time Clock maintains settable time during power loss and can be
synchronized to an external time code.
•Battery backed control values allow one-time setup.
•Supports external event time capture input.
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CHAPTER ONE
1-2bc630AT Real Time Clock Module Datum Inc
•Provides a rate programmable heartbeat pulse/interrupt (1-2000 Hz) synchronized to the time
source.
•Provides programmable propagation delay compensation.
•It's 16 byte I/O block can be located on any one of 48 I/O blocks in the 100H - 3FFH AT I/O
address space.
•Drives Datum’s optional LED display modules with the decoded time.
1.2 PHYSICAL AND FUNCTIONAL OVERVIEW
The bc630AT is a half height IBM XT/AT bus board designed to provide a precision real time clock,
decode serial time code signals, digitally synchronize multiple PC's and provide a number of other
valuable timing features. The bc630AT also incorporates a battery backed real time clock IC which
maintains settable time during power loss and can be synchronized to an external time code signal. The
real time clock can also be decoded with microsecond precision.
The operation of the bc630AT is controlled by sixteen 8-bit registers written and read by the host
XT/AT computer. These registers are used for defining the time source the bc630AT decodes, mode
of operation, setting and reading the real time clock, activating time capture operations, holding the
captured time and status; defining the heartbeat frequency, and defining the propagation delay
compensation value.
1.3 PERFORMANCE SPECIFICATIONS
The principal performance characteristics are listed in Table 1-1, on the following page.
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INTRODUCTION
Datum Inc bc630AT Real Time Clock Module 1-3
Table 1-1
Performance Specifications
Item Description
Time Code Reader Time Code Formats IRIG A, B, NASA 36, 2137.
Carrier Range IRIG A - 10 kHz ±2%.
IRIG B, NASA 36, 2137 - 1 kHz ±2%.
Flywheel Accuracy <3.6 milliseconds per hour (with Filter enabled).
Modulation Ratio 3:1 to 6:1.
Input Amplitude 100 mVrms to 1 Vrms.
Input Impedance 10K Ω(AC Coupled).
Real Time Clock Format 24 hour.
Accuracy ±10 PPM.
XT/AT Bus
Interface Address Space 1 block of 16 bytes in the PC I/O map. Range: 100H - 3FFH in an AT computer.
200H - 3FFH in an XT computer.
Interrupts Jumper selectable for IRQ3-7, 9, 10, 11, 12, 14 or
15 interrupt lines.
Power +5VDC @ 500mA.
TTL/CMOS Input
Signals Event Capture TTL/CMOS, positive or negative edge triggered, 50ns min width, 500 µs min period.
TTL Output
Signals 1 Pulse Per Second TTL/CMOS, positive edge on time.
Heartbeat Pulse TTL/CMOS, positive edge on time.
RS-422
Input/Output
Signals
1PPS 1PPS (+), 1PPS (-), positive edge on time.
Serial Time/Mssg TX/RX (+), TX/RX (-) 9600 Baud, 8 bits, 1 stop bit,
no parity.
TX (-) compatible with most RS-232 devices.
Operating and
Storage
Environments
Temperature
Operating
Non-Operating 0oto 70oC. -50oto 125oC.
Relative Humidity
Operating
Non-Operating 10% to 80% (non-condensing). 5% to 95% (non-condensing).
Altitude
Operating
Non-Operating
1,000 feet below sea level to 10,000 feet above sea
level.
1,000 feet below sea level to 20,000 feet above sea
level.
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CHAPTER ONE
1-4bc630AT Real Time Clock Module Datum Inc
1.4 TIME CODE FORMATS
The widespread use of coded timing signals to assist in the correlation of intercept and test data began in
the early 1950's. These signals can be decoded in real time to indicate the current Time of Day (TOD)
or recorded along with intercept/test data on magnetic tape recorders for post processing and time
correlation.
Hundreds of time code formats were developed - one for each agency involved. During the early
1960's the InterRange Instrumentation Group (IRIG) promoted a series of 'standard' time code formats
now loosely referred to as 'IRIG Time Codes'. The bc630AT decodes two of these formats: IRIG A
and IRIG B.
More complete details on these and other time code formats is available free of charge, on request from
Datum Inc in the form of the 'Datum Inc, Handbook of Time Code Formats'. Figure 1-1 illustrates a
frame of IRIG A, B or G time code.
Figure 1-1
IRIG Time Code Frame
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INTRODUCTION
Datum Inc bc630AT Real Time Clock Module 1-5
1.5 IBM XT/AT COMPATIBILITY
AT type computers have an extended memory addressing capability over XT type computers. The
bc630AT Real Time Clock is a port mapped device and does not make use of this extended memory
capability but does give the user the option of using the additional interrupts found on the AT bus.
Therefore, the bc630AT can be utilized in an XT computer with complete functionality and performance
with the exception of a lower number of interrupt selections.
Physically, the bc630AT mounts in either an XT or AT type computer. In the case of the XT, the AT's
second connector is not accessed resulting in a lower number of interrupt selections available to the PC.
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Datum Inc bc630AT Real Time Clock Module 2-1
CHAPTER TWO
INSTALLATION AND SETUP
2.0 GENERAL
The bc630AT is a half height IBM XT/AT bus board. The bc630AT registers are 8-bits wide. This
section details the steps required to setup the module for operation.
2.1 BASE ADDRESS SELECTION
Before installing the module in the computer, the address select DIP switch (SW1) must be set. The
bc630AT occupies 16 bytes in the PC I/O address space and can be freely located on any 16 byte
boundary. The 6 DIP switch positions of SW1 correspond to address bits A9 - A4 as shown in Figure
2-1, and determine the base address for the module (switch positions 7 and 8 are not used). The base
address is defined as the address selected by the SW1 DIP switch when A3 - A0 are 0.
Figure 2-1
DIP Switch SW1
Address Bit A9 A8 A7 A6 A5 A4
SW1 Switch
To select a base address, set each of the 6 DIP switches to the ON (same as CLOSED) or OFF (same
as OPEN) position. Setting a DIP switch to the ON position selects a logical 0 for that address bit, and
the OFF position selects a logical 1.
In an AT computer the base address can be set in the range of 100H - 3F0H. In an XT computer the
base address can be set in the range of 200H - 3F0H.
Note:Setting a base address that is out of these ranges will probably prevent your computer
from booting.
For example, to set the bc630AT base address to 300H, set switches 1 and 2 to the OFF position and
set switches 3, 4, 5, and 6 to the ON position. Refer to Table 2-1 for a list of all the available base
addresses in the PC bus and the corresponding switch settings.
1 2 3 4 5 6
OPEN
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CHAPTER TWO
2-2bc630AT Real Time Clock Module Datum Inc
Table 2-1
PC Bus Base Address Selection (SW1)
Base
Addr S1 A9 S2 A8 S3 A7 S4 A6 S5 A5 S6 A4 A3 A2 A1 A0
100H ON OFF ON ON ON ON 0 0 0 0
110H ON OFF ON ON ON OFF 0 0 0 0
120H ON OFF ON ON OFF ON 0 0 0 0
130H ON OFF ON ON OFF OFF 0 0 0 0
140H ON OFF ON OFF ON ON 0 0 0 0
150H ON OFF ON OFF ON OFF 0 0 0 0
160H ON OFF ON OFF OFF ON 0 0 0 0
170H ON OFF ON OFF OFF OFF 0 0 0 0
180H ON OFF OFF ON ON ON 0 0 0 0
190H ON OFF OFF ON ON OFF 0 0 0 0
1A0H ON OFF OFF ON OFF ON 0 0 0 0
1B0H ON OFF OFF ON OFF OFF 0 0 0 0
1C0H ON OFF OFF OFF ON ON 0 0 0 0
1D0H ON OFF OFF OFF ON OFF 0 0 0 0
1E0H ON OFF OFF OFF OFF ON 0 0 0 0
1F0H ON OFF OFF OFF OFF OFF 0 0 0 0
Table 2-2
PC Bus Base Address Selection (SW1)
Base
Addr S1 A9 S2 A8 S3 A7 S4 A6 S5 A5 S6 A4 A3 A2 A1 A0
200H OFF ON ON ON ON ON 0 0 0 0
210H OFF ON ON ON ON OFF 0 0 0 0
220H OFF ON ON ON OFF ON 0 0 0 0
230H OFF ON ON ON OFF OFF 0 0 0 0
240H OFF ON ON OFF ON ON 0 0 0 0
250H OFF ON ON OFF ON OFF 0 0 0 0
260H OFF ON ON OFF OFF ON 0 0 0 0
270H OFF ON ON OFF OFF OFF 0 0 0 0
280H OFF ON OFF ON ON ON 0 0 0 0
290H OFF ON OFF ON ON OFF 0 0 0 0
2A0H OFF ON OFF ON OFF ON 0 0 0 0
2B0H OFF ON OFF ON OFF OFF 0 0 0 0
2C0H OFF ON OFF OFF ON ON 0 0 0 0
2D0H OFF ON OFF OFF ON OFF 0 0 0 0
2E0H OFF ON OFF OFF OFF ON 0 0 0 0
2F0H OFF ON OFF OFF OFF OFF 0 0 0 0
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INSTALLATION AND SETUP
Datum Inc bc630AT Real Time Clock Module 2-3
Table 2-3
PC Bus Base Address Selection (SW1)
Base
Addr S1 A9 S2 A8 S3 A7 S4 A6 S5 A5 S6 A4 A3 A2 A1 A0
300H OFF OFF ON ON ON ON 0 0 0 0
310H OFF OFF ON ON ON OFF 0 0 0 0
320H OFF OFF ON ON OFF ON 0 0 0 0
330H OFF OFF ON ON OFF OFF 0 0 0 0
340H OFF OFF ON OFF ON ON 0 0 0 0
350H OFF OFF ON OFF ON OFF 0 0 0 0
360H OFF OFF ON OFF OFF ON 0 0 0 0
370H OFF OFF ON OFF OFF OFF 0 0 0 0
380H OFF OFF OFF ON ON ON 0 0 0 0
390H OFF OFF OFF ON ON OFF 0 0 0 0
3A0H OFF OFF OFF ON OFF ON 0 0 0 0
3B0H OFF OFF OFF ON OFF OFF 0 0 0 0
3C0H OFF OFF OFF OFF ON ON 0 0 0 0
3D0H OFF OFF OFF OFF ON OFF 0 0 0 0
3E0H OFF OFF OFF OFF OFF ON 0 0 0 0
3F0H OFF OFF OFF OFF OFF OFF 0 0 0 0
2.2 INSTALLATION PROCEDURE
To install the bc630AT module in your computer chassis:
1. Remove the computer chassis cover.
2. Select a vacant expansion slot and remove the blank rear panel bracket. Save the screw.
3. Slide the bc630AT Real Time Clock Module straight down to engage the motherboard
connectors.
4. Fasten the top of the bracket to the chassis using the screw that was saved from Step 2.
5. Replace the chassis cover.
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CHAPTER TWO
2-4bc630AT Real Time Clock Module Datum Inc
2.3 DEMONSTRATION DISKETTE
This disk contains two executable programs that demonstrate the use of the bc630AT Real Time Clock
Module.
630DEMO1.EXE
Reads IRIG B, IRIG A, NASA 36, 2137 modulated and DC level shift time codes.
630DEMO2.EXE
General Purpose Demo Program for all time sources, time code types and features of the bc630AT.
630CODE.SYS
Device drivers that, when installed, replace the usual clock driver of 630RTC.SYS the PC with the
bc630AT.
Instructions on the use of these programs is contained in the diskette file - README.DOC. At the
DOS prompt simply type 'README'.
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Datum Inc bc630AT Real Time Clock Module 3-1
CHAPTER THREE
OPERATION AND SOFTWARE INTERFACE
3.0 GENERAL
The bc630AT occupies one block of 16 bytes in the XT/AT I/O address space. Refer to Section 2.1
for details on base address selection. Data transfers between the XT/AT bus can be accomplished with
8 bit I/O instructions. This chapter describes the bc630AT registers and their use.
3.1 REGISTERS
This section describes the registers used on the bc630AT for controlling its operation and transferring
time data. Section 3.2 details the use of these registers. The Control Register memory map for the
bc630AT is listed in Table 3-1. The memory map for the rest of the bc630AT registers is listed in
Table 3-2. The first column of these tables shows the offset from the base address of each register.
The value of each register following a power on or software reset is shown. A value of '--' indicates
that the register contents are undefined. A label for each register is listed as is a brief description of the
register's function.
3.1.1 CONTROL REGISTERS
The Control Registers govern the operation of the bc630AT. To control the operation of the bc630AT,
first write the appropriate values to the control registers, then execute an 'Initialize' command. The
control registers are described below. All values are in base hexadecimal.
Table 3-1
bc630AT Control Register Memory Map
Offset (HEX) Default Value Label Description
07H 00 STATUS Status Register.
08H * 00 TMSEL Time Code Select.
09H * 00 MASKS Masks Register.
0AH * D0H HBRATE0 Heartbeat Rate LSB.
0BH * 07H HBRATE1 Heartbeat Rate MSB.
0CH * 00 PROPDEL0 Propagation Delay LSB.
0DH * 00 PROPDEL1 Propagation Delay MSB.
* Denotes battery backed value loaded at power on.
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CHAPTER THREE
3-2bc630AT Real Time Clock Module Datum Inc
3.1.2 STATUS REGISTER (STATUS - offset 07H)
The bc630AT provides a read/write status byte containing the status of the Real Time Clock Module.
The status byte is the only control register that is written to by the bc630AT.
1PPS EVENT TSTAT1 TSTAT0 TC3 TC2 TC1 TC0
STATUS - Offset 07H
TC3, TC2, TC1, and TC0 each designate the Last Known Time Code Detected.
Table 3-1
Status - Offset 07H
TC3 TC2 TC1 TC0 Description
0 0 0 0 Initialization or reset is complete, time code not yet found.
0 0 0 1 IRIG B - Modulated Time Code.
0 0 1 0 IRIG A - Modulated Time Code.
0 0 1 1 2137 - Modulated Time Code.
0 1 0 0 Battery Backed Real Time Clock IC.
0 1 0 1 bc630AT Master.
0 1 1 0 NASA 36 - Modulated Time Code.
0 1 1 1 IRIG B - DC Level Shift Time Code.
1 0 0 0 IRIG A - DC Level Shift Time Code.
1 0 0 1 NASA 36 - DC Level Shift Time Code.
1 0 1 0 External 1PPS.
1 0 1 1 External 1, 5, 10 MHz Frequency.
TSTAT1, TSTAT0
Time Code Tracking Status.
00 = time code present.
01 = flywheeling to the internal crystal.
10 = flywheeling to an external 1PPS.
11 = flywheeling to an external 1, 5, 10 MHz frequency reference.
Note:The term 'flywheeling' means that the input time source has been lost or is unusable, but
the bc630AT is still providing time, heartbeats, etc. as if the time source is still present.
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OPERATION AND SOFTWARE INTERFACE
Datum Inc bc630AT Real Time Clock Module 3-3
EVENT
Event Capture Flag.
0 = No event.
1 = Event captured.
1PPS
1PPS Flag.
0 = On-time mark has not occurred.
1 = On-time mark has occurred.
Note:This flag is set each second approximately 150 :secs after the on-time mark occurs. The
bc630AT clears this flag only at Power On and with a software 'Reset' or 'Initialize'
command. If utilized the user is responsible for clearing the flag.
3.1.3 TIME CODE SELECT REGISTER (TCSEL - offset 08H)
-- MOD/DC IM1 IM0 TC3 TC2 TC1 TC0
Time Code Select Byte - offset 07H
TC3, TC2, TC1, and TC0 designate the time code to be decoded.
0000 = Auto detect IRIG B, IRIG A, NASA 36 and 2137 modulated & DC level shift
time codes.
0001 = IRIG A.
0010 = IRIG B.
0011 = 2137.
0100 = Battery Backed Real Time Clock IC.
0101 = bc630AT Master.
0110 = NASA 36.
1010 = External 1PPS Synchronization.
1011 = External 1, 5, 10 MHz Synchronization.
Note:When auto detect is selected, the MOD/DC bit must be 0.
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CHAPTER THREE
3-4bc630AT Real Time Clock Module Datum Inc
IM1, IM0
Designates the Initialization Mode upon power on or after an 'Initialize' command is issued.
00 = Normal initialization.
01 = Battery Backed RTC IC time and RTC time code period.
10 = Battery Backed RTC IC time and battery backed time source period.
11 = Battery Backed RTC IC time and user defined time source period specified in
DAT00 (LSB) and DAT01 (MSB).
Initialization modes 1, 2, and 3 synchronize the bc630AT with the battery backed RTC IC time and the
respective time code period of the mode during initialization. When initialization completes, the
bc630AT searches for the designated time code and if a valid time code is not found, enters a 'flywheel'
state maintaining time with the mode specified time code period.
The bc630AT continues flywheeling until a valid time code specified by TC3-TC0 is found at which
time the bc630AT's clock is re-synchronized to the time code.
Note:Initialization takes approximately 3 seconds when Initialization Modes 1, 2 and 3 are
selected.
MOD/DC
Designates the time code type specified by TC3 - TC0 as either Modulated or DC Level Shift.
0 = DC Level Shift Time Code.
1 = Modulated Time Code.
Note:In auto detect mode the MOD/DC bit must be 0. When non-time codes are selected (i.e.
battery backed RTC IC, Master bc630AT, etc.) this bit is not used.
3.1.4 MASKS REGISTER (MASKS - offset 09H)
The Masks Register controls the disabling (masking) and enabling (unmasking) of the event capture,
digital filtering of incoming time signals, heartbeat pulses, external flywheel synchronization and selects
the interrupt source. If a change to the default conditions is desired a new value is written to the Masks
Register and followed by an 'Initialize' or 'Process Masks Register' command.
ISRC2 ISRC1 ISRC0 HBEN FILTER XFW EVN1 EVN0
MASKS - offset 09H
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OPERATION AND SOFTWARE INTERFACE
Datum Inc bc630AT Real Time Clock Module 3-5
EVN1, EVN0
External Event Capture Control
00 = Disable External Event Capture.
01 = Enable External Event Capture on the falling edge of the external Event Capture
Input.
10 = Enable External Event Capture on the rising edge of the External Event Capture
Input.
11 = Enable External Event Capture on both the rising and falling edges of the External
Event Capture Input.
XFW
Enable/Disable External Flywheel Synchronization
0 = Disable External Flywheel Synchronization.
1 = Enable External Flywheel Synchronization.
Enables disciplining of the bc630AT's time base during 'flywheel' periods with an external 1PPS or 1, 5,
10 MHz frequency reference if present.
FILTER
Enables Digital Filtering of the time source signals.
0 = Disable filter
1 = Enable filter
Enabling the Digital Filter invokes an algorithm which allows the bc630AT to decode all available time
sources with maximum accuracy and increases the accuracy of the 'flywheel' during drop outs of the
time source. The filter should be disabled if decoding time from an unstable time code or tape source
(i.e. time frames fluctuate more than "15 :secs).
HBEN
Heartbeat Pulses/Interrupts Control.
0 = Disable heartbeat pulses/interrupts (pulse output remains high)
1 = Enable heartbeat pulses/interrupts at the rate defined by HBRATE1 (MSB) and
HBRATE0 (LSB).
Note:The heartbeat feature is not available for IRIG A.
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CHAPTER THREE
3-6bc630AT Real Time Clock Module Datum Inc
ISRC2, ISRC1 and ISRC0
Interrupt Source Selection.
Interrupt Register Value Interrupt Source
000 - - No Interrupts Selected.
001 Ready Byte Value Ready Byte.
010 40H Event.
011 60H Heartbeat.
100 80H 1PPS.
The bc630AT generates an interrupt to the host PC by writing the Int Reg Val to the Interrupt Register
(offset 0FH) upon the occurrence of the selected interrupt source. The interrupt is asserted until the
host PC reads the Interrupt Register. The PC interrupt IRQ channel that the bc630AT asserts is
controlled by jumper JP-5 (See Table 4-9). The host can optionally use the Interrupt Register in a
polled mode by clearing the register and polling for the proper Interrupt Register Value.
Note:Only one Interrupt source can be selected. Maximum polling rate of Interrupt Register not to
exceed 500 kHz.
3.1.5 HEARTBEAT RATE (HBRATE1, HBRATE0 - offset 0AH and 0BH)
The rate at which the heartbeat pulses/interrupts are generated is controlled by these registers which
combine to produce a 16-bit unsigned value. The heartbeat pulse rate represents the number of
pulses/interrupts generated each second. The frequency range of the heartbeat rate is 1 to 2000 Hz.
The rising edge of the heartbeats pulses are synchronized to on-time. For example, a heartbeat rate of
1000 would result in a generated pulse/interrupt each millisecond whose rising
edge would correspond to exactly 1 millisecond. (i.e. 0.000 000 , 0.001 000, 0.002 000 ... 0.999
000, 1.000 000 seconds.)
The bc630AT processes the heartbeat rate data when it receives an 'Initialize' or 'Synchronize
Heartbeats' command. (See Section 3.3.)
Note:The bc630AT must be decoding time or flywheeling before the Heartbeat Rate is
programmed.
3.1.6 PROPAGATION DELAY (PROPDEL1, PROPDEL0 - offset 0CH and 0DH)
The propagation delay compensation function can offset the effects of long cables between the time
code source and the bc630AT. These two registers combine to produce a signed 16-bit quantity. The
range of values supported is -2048 to +2047. Each unit represents a delay of 0.5 :sec. For example, a
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OPERATION AND SOFTWARE INTERFACE
Datum Inc bc630AT Real Time Clock Module 3-7
value of 1000 would effect a delay of 500 :sec. Positive values advance the 1PPS (Pulse Per Second)
and heartbeat pulses relative to the time code. Negative values retard the 1PPS and heartbeat pulses.
3.2 DATA TRANSFER ADDRESS SPACE
The data transfer address space consists of a sequence of 7 data bytes starting at the base address and
one command byte at offset 0EH. The command byte also serves as a 'data ready flag byte' to
feedback ready flag values which indicate the bc630AT has successfully completed a command task.
The PC XT/AT computer requests specific data from the bc630AT by writing a coded request to the
Command Register at offset 0EH. The baseboard must then wait for the command byte to be modified
by the bc630AT firmware to indicate that the requested data is available at offset locations 00H through
06H. The data format is predefined in this section.
Note:Polling rates of the Command Register must not exceed 500 kHz.
Table 3-2
bc630AT Data Transfer, Command and Interrupt Register Memory Map
Offset (HEX) Reset Value Label Description
00H - - DAT00 Data Byte 0.
01H - - DAT01 Data Byte 1.
02H - - DAT02 Data Byte 2.
03H - - DAT03 Data Byte 3.
04H - - DAT04 Data Byte 4.
05H - - DAT05 Data Byte 5.
06H - - DAT06 Data Byte 6.
0EH 10H/1EH COMMAND Command Register.
0FH - - INTERRUPT Interrupt Register.
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CHAPTER THREE
3-8bc630AT Real Time Clock Module Datum Inc
3.3 SOFTWARE COMMANDS
The following command bytes have been defined for version OS 3.0. Additional command bytes may
be added in future versions of the bc630AT firmware.
com ready data
byte flag offset / bits 7-4 / bits 3-0
<Request Time> Current time is logged as the time when 80H was written to offset 0EH.
80H 00H 0 / seconds tens / seconds units
1 / minutes tens / minutes units
2 / hours tens / hours units
3 / days tens / days units
4 / DH1 DH0 -- C20 / C19 C18 C17 C16
5 / C07 C06 C05 C04 / C03 C02 C01 C00
6 / C15 C14 C13 C12 / C11 C10 C09 C08
C20-C00 = binary 0.5 microsecond count
DH1-DH0 = days hundreds value (0, 1, 2, 3)
-- = bit undefined
<Request Event Time> Last event time logged on programmed edge, positive or negative or
both.
81H 01H 0 / seconds tens / seconds units
1 / minutes tens / minutes units
2 / hours tens / hours units
3 / days tens / days units
4 / DH1 DH0 -- C20 / C19 C18 C17 C16
5 / C07 C06 C05 C04 / C03 C02 C01 C00
6 / C15 C14 C13 C12 / C11 C10 C09 C08
C20-C00 = binary 0.5 microsecond count
DH1-DH0 = days hundreds value (0, 1, 2, 3)
-- = bit undefined
<Clear Event Capture> Event capture is disabled after each event until the command is
executed.
82H 02H 0 / Time code Period mod 65536 LSB
1 / Time code Period mod 65536 MSB
2 / AUXA1 data byte
3 / AUXA2 data byte
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OPERATION AND SOFTWARE INTERFACE
Datum Inc bc630AT Real Time Clock Module 3-9
The time code period and AUX analog data are returned to facilitate data logging applications which
use the event strobe.
com ready data
byte flag offset / bits 7-4 / bits 3-0
<Output auxiliary data>
83H 03H 0 / Time code Period mod 65536 LSB
1 / Time code Period mod 65536 MSB
2 / AUXA1 data byte
3 / AUXA2 data byte
4 / AGC level
5 / reserved
6 / reserved
<Set RTC Chip IC Time> Set the time of the battery backed Real Time Clock IC.
84H 04H 0 / seconds tens / seconds units
1 / minutes tens / minutes units
2 / hours tens / hours units
3 / days tens / days units
4 / months tens / months units
5 / year tens / year units
6 / 0000 / day of week
(Sunday = 0 ... Saturday = 6)
<Request RTC IC Time> Current time of day obtained from the battery backed Real Time
Clock IC as the time when 85H was written to offset 0EH.
85H 05H 0 / seconds tens / seconds units
1 / minutes tens / minutes units
2 / hours tens / hours units
3 / days tens / days units
4 / months tens / months units
5 / year tens / year units
6 / 0000 / day of week
(Sunday = 0 ... Saturday = 6)
<Request Power Off Time> Time when computer was last turned off.
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