DDC RDC-19220 Series User manual

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Data Device Corporation
105 Wilbur Place
Bohemia, New York 11716
631-567-5600 Fax: [phone]
www.ddc-web.com
FOR MORE INFORMATION CONTACT:
Technical Support:
1-800-DDC-5757 ext. 7771
DESCRIPTION
The RDC-19220 Series of converters are low-cost, versatile, 16-bit
monolithic, state-of-the-art Resolver(/LVDT)-to-Digital Converters.
These single-chip converters are available in small 40-pin DDIP, or
44-pin J-Lead packages and offer programmable features such as
resolution, bandwidth and velocity output scaling.
Resolution programming allows selection of 10-, 12-, 14-, or 16-bit,
with accuracies to 2.3 min. This feature combines the high tracking
rate of a 10-bit converter with the precision and low-speed velocity
resolution of a 16-bit converter in one package.
The velocity output (VEL) from the RDC-19220 Series, which can be
used to replace a tachometer, is a 4 V signal (3.5 V with the +5 V only
option) referenced to ground with a linearity of 0.75% of output voltage.
The full scale value of VEL is set by the user with a single resistor.
RDC-19220 Series converters are available with operating tempera-
ture ranges of 0° to +70°C, -40° to +85°C and -55° to +125°C. Military
processing is available (consult factory).
APPLICATIONS
With its low cost, small size, high accuracy and versatile performance,
the RDC-19220 Series converter is ideal for use in modern high-per-
formance industrial and military control systems. Typical applications
include motor control, radar antenna positioning, machine tool con-
trol, robotics, and process control. MIL-PRF-38534 processing is
available for military applications.
© 1999 Data Device Corporation
RDC-19220 SERIES
16-BIT MONOLITHIC TRACKING RESOLVER
(LVDT)-TO-DIGITAL CONVERTERS FEATURES
•+5 Volt Only Option
•Only Five External Passive
Components
•Programmable:
- Resolution: 10-, 12-, 14-, or 16-Bit
- Bandwidth: to 1200 Hz
- Tracking: to 2300 RPS
•Differential Resolver and LVDT
Input Modes
•Velocity Output Eliminates
Tachometer
•Built-In-Test (BIT) Output
•Small Size: 40-Pin DDIP or
44-Pin J-Lead Package
•-55° to +125°C Operating
Temperature Available
•Programmable for LVDT input

2
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RDC-19220 SERIES
Q-05/05-0
FIGURE 1. RDC-19220 SERIES BLOCK DIAGRAM
SIN
-S
+S
COS
-C
+C
+5C
+CAP
-CAP
-5C
A GND
+5 V
GND
-5 V
CONTROL
TRANSFORMER
-5 V
INVERTER
DATA
LATCH
GAIN DEMODULATOR
16 BIT
UP/DOWN
COUNTER
HYSTERESIS
+REF -REF BIT
R
1
VCO
&
TIMING
-
+
-
+
AB
INH EM BIT 1
THRU
BIT 16
EL AB CB
E
R
S
R
C
R
V
R
B
C
BW
C
BW
10
-VSUM VEL -VCO
INTEGRATOR

(Note 6)
TTL/CMOS compatible
Logic 0 = 0.8 V max.
Logic 1 = 2.0 V min.
Loading =10 µA max pull-up cur-
rent source to +5 V //5 pF max.
CMOS transient protected
Logic 0 inhibits; Data stable
within 0.3 µs
Logic 0 enables;Data stable with
-in 150 ns (logic 0=Transparent)
Logic 1 = High Impedance
Data High Z within 100 nS
Mode B A Resolution
resolver 0 0 10 bits
" 0 1 12 bits
" 1 0 14 bits
" 1 1 16 bits
LVDT -5 V 0 8 bits
" 0 -5 V 10 bits
" 1 -5 V 12 bits
" -5 V -5 V 14 bits
10, 12, 14, or 16 parallel lines;
natural binary angle positive
logic (see TABLE 2)
0.25 to 0.75 µs positive pulse
leading edge initiates counter
update.
Logic 1 at all 0s (ENL to -5 V);
LSBs are enabled
Logic 0 for BIT condition.
±100 LSBs of error typ. with a
filter of 500 µS, or total Loss-of-
Signal (LOS)
50 pF +
Logic 0; 1 TTL load, 1.6 mA at
0.4 V max
Logic 1; 10 TTL loads, = 0.4 mA
at 2.8 V min
Logic 0; 100 mV max driving CMOS
Logic 1; +5 V supply minus 100mV
min driving CMOS, High Z;
10 uA//5 pF max
3
Data Device Corporation
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RDC-19220 SERIES
P-05/05-0
TABLE 1. RDC-19220 SPECIFICATIONS
These specifications apply over the rated power supply, temperature
and reference frequency ranges, and 10% signal amplitude variation
and harmonic distortion.
PARAMETER UNIT VALUE
RESOLUTION Bits 10, 12, 14, or 16
ACCURACY Min 4 or 2 + 1 LSB (note 3)
REPEATABILITY LSB 1 max
DIFFERENTIAL LINEARITY LSB 1 max in the 16th bit
REFERENCE
Type
Voltage:
differential
single ended
overload
Frequency
Input Impedance
VP-P
VP
V
Hz
Ohm
(+REF, -REF)
Differential
10 max
±5 max
±25 continuous, 100 transient
DC to 40,000 (note 4 & note 9)
10M min // 20 pf
SIGNAL INPUT
Type
Voltage: operating
overload
Input impedance
Vrms
V
Ohm
(+S, -S, SIN, +C, -C, COS)
Resolver, differential, groundbased
2 ±15%
±25 continuous
10M min//10 pf.
DIGITAL INPUT/OUTPUT
Logic Type
Inputs
Inhibit (INH)
Enable Bits 1 to 8 (EM)
Enable Bits 9 to 16 (EL)
Resolution and Mode
Control (A & B)
(see notes 1 and 2.
pre-set to logic 1 note 6)
Outputs
Parallel Data (1-16)
Converter Busy (CB)
Zero Index
Built-in-Test (BIT)
Drive Capability
(Zl)
UNITPARAMETER VALUE
DYNAMIC
CHARACTERISTICS
Resolution
Tracking Rate (max)(note 4)
Bandwidth(Closed Loop)
(max) (note 4)
Ka (Note 7)
A1
A2
A
B
Acceleration (1 LSB lag)
Settling Time(179° step)
bits
rps
Hz
1/sec2
1/sec
1/sec
1/sec
1/sec
deg/s2
msec
(at maximum bandwidth)
10 12 14 16
1152 288 72 18
1200 1200 600 300
5.7M 5.7M 1.4M 360k
19.5 19.5 4.9 1.2
295k 295k 295k 295k
2400 2400 1200 600
1200 1200 600 300
2M 500k 30k 2k
2 8 20 50
VELOCITY
CHARACTERISTICS
Polarity
Voltage Range(Full Scale)
Scale Factor Error
Scale Factor TC
Reversal Error
Linearity
Zero Offset
Zero Offset TC
Load
Noise
V
%
PPM/C
%
%
mv
µV/C
kΩ
(Vp /V)%
Positive for increasing angle
±4 (at nominal ps)
10 typ 20 max
100 typ 200 max
0.75 typ 1.3 max
0.25 typ 0.50 max
5 typ 10 max
15 typ 30max
8 min
1 typ .125 min 2 max
POWER SUPPLIES
Nominal Voltage
Voltage Range
Max Volt. w/o Damage
Current
V
%
V
mA
(note 5)
+5 -5
± 5 ±5
+7 -7
14 typ, 22 max (each)
TEMPERATURE RANGE
Operating (Case)
-30X
-20X
-10X
-A0X
Storage
plastic package
ceramic package
°C
°C
°C
°C
°C
°C
0 to +70
-40 to +85
-55 to +125
-40 to +125
-65 to +150
-65 to +150
THERMAL RESISTANCE
Junction-to-Case (θjc)
40-pin DDIP (ceramic)
44-pin J-Lead (plastic)
44-pin J-Lead (ceramic)
°C/W
°C/W
°C/W
4.6
72.6
2.4
PHYSICAL
CHARACTERISTICS
Size: 40-pin DDIP
44-pin J-Lead
in(mm)
in(mm)
2.0 x 0.6 x 0.2 (50.8 x 15.24 x 5.08)
0.690 square (17.526)
Weight:
40-pin DDIP
44-pin J-Lead
oz(g)
oz(g)
Plastic Ceramic
n/a 0.24 (6.80)
0.08 (2.27) 0.065 (1.84)
TABLE 1. RDC-19220 SPECIFICATIONS (CONT’D)
These specifications apply over the rated power supply, temperature
and reference frequency ranges, and 10% signal amplitude variation
and harmonic distortion.
MOISTURE SENSITIVITY
LEVEL JEDEC Level 3

4
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RDC-19220 SERIES
Q-05/05-0
THEORY OF OPERATION
The RDC-19220 Series of converters are single CMOS custom
monolithic chips. They are implemented using the latest IC tech-
nology which merges precision analog circuitry with digital logic
to form a complete, high-performance tracking Resolver-to-
Digital converter. For user flexibility and convenience, the con-
verter bandwidth, dynamics and velocity scaling are externally
set with passive components.
FIGURE 1 is the functional block diagram of the RDC-19220
Series. The converter operates with ±5 Vdc power supplies.
Analog signals are referenced to analog ground, which is at
ground potential. The converter is made up of two main sections;
a converter and a digital interface. The converter front-end con-
sists of sine and cosine differential input amplifiers. These inputs
are protected to ±25 V with 2 kΩresistors and diode clamps to
the ±5 Vdc supplies. These amplifiers feed the high accuracy
Control Transformer (CT). Its other input is the 16-bit digital angle
φ. Its output is an analog error angle, or difference angle,
between the two inputs. The CT performs the ratiometric trigono-
metric computation of SINθCOSφ- COSθSINφ= SIN(θ-φ) using
amplifiers, switches, logic and capacitors in precision ratios.
Note: The transfer function of the CT is normally trigonometric,
but in LDVT mode the transfer function is triangular (linear)
and could thereby convert any linear transducer output.
GAIN
11 mV/LSB
16 BIT
UP/DOWN
COUNTER
R
1
VCO
R
V
R
B C
BW
C /10
BW
VEL
-VCO
H = 1
-VSUM VEL
C F
S S
CT
+
-
RESOLVER
INPUT
(θ)
R
S
50 pf
C
VCO
DIGITAL
OUTPUT
(φ)
DEMOD
±1.25 V
THRESHOLD
1
FIGURE 2. TRANSFER FUNCTION BLOCK DIAGRAM #1
TABLE 2. DIGITAL ANGLE OUTPUTS
BIT DEG/BIT MIN/BIT
1(MSB)
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
180
90
45
22.5
11.25
5.625
2.813
1.405
0.7031
0.3516
0.1758
0.0879
0.0439
0.0220
0.0110
0.0055
10800
5400
2700
1350
675
337.5
168.75
84.38
42.19
21.09
10.55
5.27
2.64
1.32
0.66
0.33
Note: EM enables the MSBs and EL enables the LSBs.
The converter accuracy is limited by the precision of the com-
puting elements in the CT. For enhanced accuracy, the CT in
these converters uses capacitors in precision ratios, instead of
the more conventional precision resistor ratios. Capacitors, used
as computing elements with op-amps, need to be sampled to
eliminate voltage drifting. Therefore, the circuits are sampled at a
high rate (67 kHz) to eliminate this drifting and at the same time
to cancel out the op-amp offsets.
The error processing is performed using the industry standard
technique for type II tracking R/D converters. The dc error is inte-
grated yielding a velocity voltage which in turn drives a voltage
controlled oscillator (VCO). This VCO is an incremental integra-
tor (constant voltage input to position rate output) which togeth-
Notes for TABLE 1:(from previous page)
1. Unused data bits are set to logic “0.”
2. In LVDT mode, bit 16 is LSB for 14-bit resolution or bit 12 is LSB for
10-bit resolution.
3. Accuracy spec below for LVDT mode, null to + full scale travel (45
degrees).(2 wire-LVDT configuration).
4 Min part = 0.15% + 1 LSB of full scale “resolution set”.
2 Min part = 0.07% + 1 LSB of full scale “resolution set”
1 Min part = 0.035% + 1 LSB of full scale “resolution set”
Accuracy spec below for LVDT mode, null to + full scale travel (90
degrees).(3 wire-LVDT configuration).
4 Min part = 0.07% + 1 LSB of full scale “resolution set”.
2 Min part = 0.035% + 1 LSB of full scale “resolution set”
1 Min part = 0.017% + 1 LSB of full scale “resolution set”
Note that this is the converter spec only and does not consider the
front end external resistor tolerances.
4. See text, General Setup Considerations and HigherTracking Rates.
5. See text: General Setup Considerations for RDC19222.
6. Any unused input pins may be left floating (unconnected). All input
pins are internally pulled-up to +5 Volts.
7. KA = Acceleration constant, for a full definition see the RDC-
19220/RD-19230 application manual acceleration lag section.
8. When using internally generated -5V, the internal -5V charge pump
when measured at the converter pin, can read as low as -20% (or -
4V).
9. No 180° hangup with A/C reference above 360°.

5
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RDC-19220 SERIES
P-05/05-0
er with the velocity integrator forms a type II servo feedback loop.
A lead in the frequency response is introduced to stabilize the
loop and another lag at higher frequency is introduced to reduce
the gain and ripple at the carrier frequency and above. The set-
tings of the various error processor gains and break frequencies
are done with external resistors and capacitors so that the con-
verter loop dynamics can be easily controlled by the user.
TRANSFER FUNCTION AND BODE PLOT
The dynamic performance of the converter can be determined from
its Transfer Function Block Diagrams and its Bode Plots (open and
closed loop). These are shown in FIGURES 2, 3, and 4.
The open loop transfer function is as follows:
where A is the gain coefficient and A2= A1A2
and B is the frequency of lead compensation.
The components of gain coefficient are error gradient, integrator
gain and VCO gain. These can be broken down as follows:
RV, RB, and CBW are selected by the user to set velocity scaling
and bandwidth.
- Error Gradient = 0.011 volts per LSB (CT + Error Amp + Demod
with 2 Vrms input)
- Integrator Gain = volts per second per volt
- VCO Gain = LSBs per second per volt
where: Cs = 10 pF
Fs = 67 kHz when Rs = 30 kΩ
Fs = 100 kHz when Rs = 20 kΩ
Fs = 134 kHz when Rs = 15 kΩ
CVCO = 50 pF
Cs Fs
1.1 CBW
1
1.25 RVCVCO
2 S
A +1
( )
B
2 S
S +1
( )
10B
Open Loop Transfer Function =
ERROR PROCESSOR
RESOLVER
INPUT
(θ)
VELOCITY
OUT
DIGITAL
POSITION
OUT (φ)
VCO
CT S
A + 1
1
B
S
S + 1
10B
H = 1
+
-
eA
2
S
-12 db/oct
BA
2A
-6 db/oct
10B
ω(rad/sec)
2A 2 2 A ω(rad/sec)
f = BW (Hz) =
BW 2 A
π
CLOSED LOOP
(B = A/2)
GAIN = 0.4
GAIN = 4
(CRITICALLY DAMPED)
OPEN LOOP
FIGURE 3. TRANSFER FUNCTION
BLOCK DIAGRAM #2 FIGURE 4. BODE PLOTS
GENERAL SETUP CONSIDERATIONS
Note: For detailed application and technical information see the RDC-19220 & RD-
19230 series converter applications manual (Document number MN-19220XX-001)
which is available for download from the DDC web site @ www.ddc-web.com.
DDC has external component selection software which consid-
ers all the criteria below, and in a simple fashion, asks the key
parameters (carrier frequency, resolution, bandwidth, and track-
ing rate) to derive the external component value.
The following recommendations should be considered when
installing the RDC-19220 Series R/D converters:
1) In setting the bandwidth (BW) and Tracking Rate (TR) (select-
ing five external components), the system requirements need
to be considered. For greatest noise immunity, select the min-
imum BW and TR the system will allow.
2) Power supplies are ±5 V dc. For lowest noise performance it
is recommended that a 0.1 µF or larger cap be connected
from each supply to ground near the converter package.
When using a +5v and -5v supply to power the converter, pins
22, 23, 25, 26 must be no connection.
3) This converter has 2 internal ground planes, which reduce
noise to the analog input due to digital ground currents. The
resolver inputs and velocity output are referenced to AGND.
The digital outputs and inputs are referenced to GND. The
AGND and GND pins must be tied together as close to the
converter package as possible. Not shorting these pins
together as close to the converter package as possible will
cause unstable converter results.
4) The BIT output which is active low is activated by an error of
approximately 100 LSBs. During normal operation for step
inputs or on power up, a large error can exist.
5) This device has several high impedance amplifier inputs (+C,
-C, +S, -S, -VCO and -VSUM). These nodes are sensitive to

noise and coupling components should be connected as
close as possible.
6) Setup of bandwidth and velocity scaling for the optimized crit-
ically damped case should proceed as follows:
Note: DDC has software available to perform the previous calcu-
lations. Contact DDC to request software or visit our web-
site at www.ddc-web.com to download software.
7) Selecting a fBW that is too low relative to the maximum appli-
cation tracking rate can create a spin-around condition in
which the converter never settles. The relationship to insure
against spin-around is as follows (TABLE 3):
8) For RDC-19222: package only.
This version is capable of +5V only operation. It accomplishes
this with a charge pump technique that inverts the +5V supply
for use as -5V, hence the +5V supply current doubles. The
built-in -5 V inverter can be used by connecting pin 2 to 26, pin
17 to 22, a 10 µF/10 Vdc capacitor from pin 23 (negative ter-
minal) to pin 25 (positive terminal), and a 47 µF/10 Vdc capac-
- Select the desired f BW (closed loop) based on overall
system dynamics.
- Select f carrier ≥3.5f BW
- Select the applications tracking rate (in accordance with TABLE 3),
and use appropriate values for R SET and R CLK
- Compute Rv =
- Compute CBW (pF) =
- Where Fs = 67 kHz for R CLK = 30 KΩ
100 kHz for R CLK = 20 KΩ
125 kHz for R CLK = 15 KΩ
- Compute RB=
- Compute
3.2 x Fs (Hz) x 108
Rv x (f BW)2
Full Scale Velocity Voltage
Tracking Rate (rps) x 2 resolution x 50 pF x 1.25 V
0.9
CBW x f BW
CBW
10
As an example:
Calculate component values for a 16-bit converter with 100Hz
bandwidth, a tracking rate of 10RPS and a full scale velocity
of 4 volts.
- Rv = = 97655 Ω
- Compute CBW (pF) = = 21955 pF
- Compute RB= = 410 kΩ
4 V
10 rps x 216 x 50 pF x 1.25 V
0.9
21955 x 10 -12 x 100 Hz
3.2 x 67 kHz x 108
97655 x 100 Hz2
6
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RDC-19220 SERIES
Q-05/05-0
itor from -5 V to GND. The current drain from the +5 V supply
doubles. No external -5 V supply is needed (SEE FIGURE 5).
When using the -5 V inverter, the max. tracking rate should be
scaled for a velocity output of 3.5 V max. Use the following equa-
tion to determine tracking rate used in the formula on page 5:
TR (required) x (4.0) = Tracking rate used in calculation
(3.5)
Note: When using the highest BW and Tracking Rates, using
the -5 V inverter is not recommended.
HIGHER TRACKING RATES AND CARRIER FREQUENCIES
Tracking rate (nominally 4 V) is limited by two factors: velocity
voltage saturation and maximum internal clock rate (nominally
1,333,333 Hz). An understanding of their interaction is essential
to extending performance.
The General Setup Considerations section makes note of the
selection of Rvfor the desired velocity scaling. Rvis the input resis-
tor to an inverting integrator with a 50 pF nominal feedback capac-
itor. When it integrates to -1.25 V, the converter counts up 1 LSB
and when it integrates to +1.25 V, the converter counts down 1
LSB. When a count is taken, a charge is dumped on the capaci-
tor; such that, the voltage on it changes 1.25 V in a direction to
bring it to 0 V. The output counts per second per volt input is there-
fore:
1
(Rvx 50 pF x 1.25)
As an example:
TABLE 3. TRACKING/BW RELATIONSHIP
RPS (MAX)/BW RESOLUTION
110
0.45 12
0.25 14
0.125 16
RDC-19222 10µf
23
25
+CAP
-CAP
.01uf
(-5c) -5V
22 17
.01uf
(+5c) +5V
26 2
47uf 47uf
+
+
FIGURE 5. -5V BUILT-IN INVERTER

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RDC-19220 SERIES
P-05/05-0
TABLE 4. MAX TRACKING RATE
(MIN) IN RPS
RC/RSET
(ΩΩ)
RS/RCLK
(ΩΩ)
RESOLUTION
10 12 14 16
30k**or open 30k 1200 288 72 18
23k 20k 1728 432 108 27
23k 15k *576 * *
*
10
*
14
32
24
40
34
15k
20k
23k
23k
711122430k23k
57112030k30k** or open
16141210
RESOLUTION
RS/RCLK
(ΩΩ)
RC/RSET
(ΩΩ)
TABLE 5. CARRIER FREQUENCY
(MAX) IN KHZ
Depending on the res-
olution, select one of
the values from this
row, for use in convert-
er max tracking rate
formula. (See previous
page for formula.)
* Not recommended.
** The use of a high quality thin-film resistor will provide better temperature
stability than leaving open. * Not recommended.
** The use of a high quality thin-film resistor will provide better temperature
stability than leaving open.
Note: RC“Rcurrent” = RSET
RS“Rsample” = RCLK
* ±10% Frequency (Hz) and Line-to-Line input voltage (Vrms) tolerances
** 2 Vrms Output Magnitudes are -2 Vrms ±0.5% full scale
*** Angle Accuracy (Max Minutes)
**** 3 Vrms to ground or 6 Vrms differential (±3% full scale)
Dimensions are for each individual main and teaser
60 Hz Synchro transformers are active (requires ±15 Vdc power supplies)
400 Hz transformer temperature range: -55°C to +125°C
60 Hz transformer (52039-X, 24133-X) temperature ranges: add to part number -1 or -3,
-1 = -55°C to +85°C
-3 = 0 to +70°C
3/6 ****11560Reference24133-X
29060Synchro52039-X
3.4115400ReferenceB-426
290400R - R52038
226400R - R52037
211.8400R - R52036
290400S - R52035
211.8400S - R52034
OUT (VRMS)**IN (VRMS)*
FREQUENCY
(HZ)*
TYPEP/N
TABLE 6. TRANSFORMERS
1.125N/A
1.11
0.81N/A
0.811
0.811
0.811
0.811
0.811
LENGTH
(IN)
ANGLE
ACCURACY***
1.125
1.14
0.61
0.61
0.61
0.61
0.61
0.61
WIDTH
(IN)
.42
.42
0.32
0.3
0.3
0.3
0.3
0.3
HEIGHT
(IN)
5D
5D
5C
5B
5B
5B
5A
5A
FIGURE
NUMBER
BOTTOM VIEW
0.81 MAX
(20.57)
0.30 MAX
(7.62)
0.61 MAX
(15.49)
0.15 MAX
(3.81)
0.09 MAX
(2.29)
0.100 (2.54) TYP
TOL NON CUM
0.61 MAX
(15.49)
0.15 MAX
(3.81) 0.09 MAX (2.29)
0.600
(15.24)
0.115 MAX
(2.92)
1345
109876
11 12 14 15
20 19 18 17 16
PIN NUMBERS FOR REF. ONLY
TERMINALS
0.025 ±0.001 (6.35 ±0.03) DIAM
0.125 (3.18) MIN LENGTH
SOLDER PLATED BRASS
T1A T1B
BOTTOM VIEW
SIDE VIEW
Dimensions are shown in inches (mm).
1
5
3
6
10
11
15
16
20
T1A
T1B
SYNCHRO
INPUT RESOLVER
OUTPUT
-SIN
+SIN
-COS
+COS
S1
S3
S2
FIGURE 5A. TRANSFORMER LAYOUT AND
SCHEMATIC (SYNCHRO INPUT - 52034/52035)
1
3
6
10
11
15
16
20
T1A
T1B
RESOLVER
INPUT RESOLVER
OUTPUT
-SIN
+SIN
-COS
+COS
S1
S3
S2
S4
BOTTOM VIEW
0.81 MAX
(20.57)
0.30 MAX
(7.62)
0.61 MAX
(15.49)
0.15 MAX
(3.81)
0.09 MAX
(2.29)
0.100 (2.54) TYP
TOL NON CUM
0.61 MAX
(15.49)
0.15 MAX
(3.81) 0.09 MAX (2.29)
0.600
(15.24)
0.115 MAX
(2.92)
1345
109876
11 12 14 15
20 19 18 17 16
PIN NUMBERS FOR REF. ONLY
TERMINALS
0.025 ±0.001 (6.35 ±0.03) DIAM
0.125 (3.18) MIN LENGTH
SOLDER PLATED BRASS
T1A T1B
BOTTOM VIEW
SIDE VIEW
Dimensions are shown in inches (mm).
FIGURE 5B. TRANSFORMER LAYOUT AND
SCHEMATIC (RESOLVER INPUT - 52036/52037/52038)
DDC
DDC
BETA
BETA
BETA
BETA
BETA
BETA
AVAILABLE
FROM
NOTE 1
Note 1: Available from refer’s to the company that the trans-
former is available from.
Beta Transformer Technology Corporation
www.bttc-beta.com

8
Data Device Corporation
www.ddc-web.com
RDC-19220 SERIES
Q-05/05-0
1
5
6
10
INPUT OUTPUT
BOTTOM VIEW
0.32 MAX
(8.13)
0.61 MAX
(15.49)
0.15 MAX
(3.81)
0.09 MAX
(2.29)
0.100 (2.54) TYP
TOL NON CUM
1325
109876
TERMINALS
0.025 ±0.001 (6.35 ±0.03) DIAM
0.125 (3.18) MIN LENGTH
SOLDER-PLATED BRASS
T1A
SIDE VIEW
Dimensions are shown in inches (mm).
0.105 (2.66)
0.600
(15.24) 0.81 MAX
(20.57)
0.125 MIN
(3.17)
FIGURE 5C. TRANSFORMER LAYOUT AND
SCHEMATIC (REFERENCE INPUT - B-426)
B-426
1
5
6
10
RL RH
RL RH
S1
S3
S4
S2
1
36
10
11
15
20
16
EXTERNAL
REFERENCE
LO HI
-S SIN -R +R -VSUM VEL
-VCO
DIGITAL
OUTPUT
16
CB
BIT
INH
EM
EL
AB +5V -5V
+S
+C
-C
COS
AGND
GND
RDC-19220
TIB
TIA
TIA
TIB
S1
S3
S2
RESOLUTION
CONTROL
}
52036(11.8V)
52037(26V)
OR
52038(90V)
OR
52034(11.8V)
52035(90V)
OR
1
3
10
6
16
11
15
20
5
OR
SYNCHRO INPUT
+S
+C
AGND
GND
Rs Rc
RB CBW
CBW/10 RV
30K
Ω
30K
Ω
FIGURE 6. TYPICAL TRANSFORMER CONNECTIONS
1.14 MAX
(28.96)
CASE IS BLACK AND
NON-CONDUCTIVE
1.14 MAX
(28.96)
•
*
S1
•
*
S3 •
(+15 V)
+15 V •
(-R)
+S
+
*
*
(RH)
•
S2
(RL)
+
*
(V)
•
V
(+R)
•
+C
(-Vs)
•
-Vs
52039
or
24133
0.21 ±0.3
(5.33 ±0.76)
0.85 ±0.010
(21.59 ±0.25)
0.175 ±0.010 (4.45 ±0.25)
NONCUMULATIVE
TOLERANCE 0.040 ±0.002 DIA. PIN.
SOLDER PLATED BRASS
0.42
(10.67)
MAX.
0.25
(6.35)
MIN.
(BOTTOM VIEW)
0.13 ±0.03
(3.30 ±0.76)
RH
RL
+15 V
V
(Analog
Gnd)
-Vs
(-15 V)
Output
+R (RH)
-R (RL)
24133
Input
S1
+15 V
V
(Analog
Gnd)
-Vs
(-15 V)
Output
+S
+C
52039
Input
S2
S3
The mechanical outline is the same for the synchro input transformer (52039) and
the reference input transformer (24133), except for the pins. Pins for the reference
transformer are shown in parenthesis ( ) below. An asterisk * indicates that the
pin is omitted.
FIGURE 5D. 60 HZ SYNCHRO AND REFERENCE
TRANSFORMER DIAGRAMS
(SYNCHRO INPUT - 52039 / REFERENCE INPUT - 24133)

9
Data Device Corporation
www.ddc-web.com
RDC-19220 SERIES
P-05/05-0
R
1
R
3
R
2
R
4
EXTERNAL
REF
LO HI
RESOLVER
S4
S3
S1
S2
GND
+S
-S
SIN
COS
-C
+C
A GND
-R +R
Notes:
1) Resistors selected to limit Vref peak to between 1 V and 5 V.
2) External reference LO is grounded, then R3 and R4 are not
needed, and -R is connected to GND.
10k Ω (1%)
10k Ω (1%)
3) See thin film network DDC-55688-1.
R
1
R
2
S3
S1
S2
+S -S SIN
COS-C
+C
A GND
S4
R
1
R
2
FIGURE 7A. TYPICAL CONNECTIONS, 2 V RESOLVER, DIRECT INPUT
FIGURE 7B. TYPICAL CONNECTIONS, X- VOLT RESOLVER, DIRECT INPUT
TYPICAL INPUT CONNECTIONS
FIGURES 7 through 9 illustrate typical input configurations
R2 =2
R1 + R2 X Volt
R1 + R2 should not load the Resolver too much; it is recommended to use a R2 = 10k.
R1 + R2 Ratio Errors will result in Angular Errors,
2 cycle, 0.1% Ratio Error = 0.029° Peak Error.
Note: The five external BW components as
shown in FIGURE 1 and 2 are necessary
for the R/D to function.
Note: The five external BW components as
shown in FIGURE 1 and 2 are necessary for
the R/D to function.

10
Data Device Corporation
www.ddc-web.com
RDC-19220 SERIES
Q-05/05-0
R
i
S1
S3 +S
-S
SIN
R
f
R
i
R
f
R
i
S4
S2 +C
-C
R
f
R
i
R
f
COS
A GND
CONVERTER
810
-
+
-
+
RESOLVER
INPUT
R
i
S1
S3 +S
-S
SIN
R
f
R
i
R
f
R
i
S4
S2 +C
-C
R
f
R
i
R
f
COS
A GND
CONVERTER
810
12
15
13
2
3
1
6
16
7
4
5
-
+
-
+
RESOLVER
INPUT
Ri x 2 Vrms = Resolver L-L rms voltage
Rf
Rf ≥ 6 kΩ
S1 and S3, S2 and S4, and RH and RL should be ideally twisted shielded, with the shield tied to GND at the converter.
Note : For 2v direct input use 10K Ωmatched resistors for Ri & Rf.
FIGURE 8A. DIFFERENTIAL RESOLVER INPUT
FIGURE 8B. DIFFERENTIAL RESOLVER INPUT, USING DDC-49530, DDC-57470 (11.8 V),
DDC-73089 (2V), OR DDC-49590 (90 V)
S1 and S3, S2 and S4, and RH and RL should be ideally twisted shielded, with the shield tied to GND at the converter.For DDC-49530
or DDC-57470: Ri = 70.8 kW, 11.8 V input, synchro or resolver. For DDC-49590: Ri = 270 kW, 90 V input, synchro or resolver. Maximum
addition error is 1 minute using recommended thin film package.
Note on DC Offset Gains: Input options affect DC offset gains and therefore affect carrier frequency ripple and jitter. Offsets gains
associated with differential mode, (offset gain for differential configuration = 1 + RF/RI) and direct mode (offset gain for direct config-
uration = 1), show differential will always be higher. Higher DC offsets cause higher carrier frequency ripple due to demodulation
process. This carrier frequency ripple because it is riding on the top of the DC error signal causes jitter. A higher carrier frequency vs
bandwidth ratio will help decrease ripple and jitter associated with offsets. Summary: R/D’s with differential inputs are more suscepti-
ble to offset problems than R/D’s in single ended mode. RD’s in higher resolutions, such as 16 bit, will further compound offset issues
due to higher internal voltage gains. Although the differential configuration has a higher DC offset gain, the differential configuration’s
common mode noise rejection makes it the preferred input option. The tradeoffs should be considered on a design to design basis.
Note: The five external BW components as
shown in FIGURE 1 and 2 are necessary
for the R/D to function.
Note: The five external BW components as
shown in FIGURE 1 and 2 are necessary
for the R/D to function.

11
Data Device Corporation
www.ddc-web.com
RDC-19220 SERIES
P-05/05-0
R
i
S1
S3 +S
-S
SIN
R
f
R
i
R
f
R
i
S2 +C
-C
R /2
i
COS
A GND
CONVERTER
R
i
R / 3
f
R / 3
f
-
+
-
+
R
i
S1
S3 +S
-S
SIN
R
f
R
i
R
f
R
i
S2 +C
-C
R /2
i
COS
A GND
CONVERTER
8
15
11
15
14
2
3
1
6
16
7
4
5
R
i
9
R / 3
f
R / 3
f
10
-
+
-
+
Ri x 2 Vrms = Synchro L-L rms voltage
Rf
Rf ≥ 6 kΩ
S1, S2, and S3 should be triple twisted shielded; RH and RL should be twisted shielded, In both cases the shield should be tied to GND at the
converter.
FIGURE 9A. SYNCHRO INPUT
FIGURE 9B. SYNCHRO INPUT, USING DDC-49530/DDC-57470 (11.8 V), DDC-73089 (2V) OR DDC-49590 (90 V)
S1, S2, and S3 should be triple twisted shielded; RH and RL should be twisted shielded, In both cases the shield should be tied to GND at the converter.
90 V input = DDC-49590: Ri = 270 kΩ, 90 V input, synchro or resolver.
11.8 V input = DDC-49530 or DDC-57470: Ri = 70.8 kΩ, 11.8 V input, synchro or resolver.
Maximum addition error is 1 minute.
Note: The five external BW components as
shown in FIGURE 1 and 2 are necessary
for the R/D to function.
Note: The five external BW components as
shown in FIGURE 1 and 2 are necessary
for the R/D to function.

12
Data Device Corporation
www.ddc-web.com
RDC-19220 SERIES
Q-05/05-0
8
10
-VCO
VEL
+5 V
-5 V
100 kΩ
(OFFSET)
100 R
V
0.8 R
V
0.4 R (SCALING)
V
RDC-19220
R
+ REF
C
LAG
- REF
+ REF
- REF
R
+ REF
C
LEAD
- REF
+ REF
- REF
FIGURE 10. VELOCITY TRIMMING FIGURE 11. PHASE-SHIFT COMPENSATION
X
c
tan ϕ=
R
Where ϕ= desired phase-shift
1
X
c=
2π fc
Where f = carrier frequency
Where
c = capacitance
Calculate Rv for the maximum counting rate, at a VEL voltage
of 4 V.
For a 12-bit converter there are 212 or 4096 counts per rotation.
1,333,333/4096 = 325 rotations per second or 333,333 counts
per second per volt.
The maximum rate capability of the RDC-19220 is set by Rs.
When Rs= 30 kΩit is nominally 1,333,333 counts/sec, which
equates to 325 rps (rotations per second). This is the absolute
maximum rate; it is recommended to only run at <90% of this rate
(as seen in TABLE 3), therefore the minimum Rvwill be limited
to 55 kΩ. The converter maximum tracking rate can be increased
50% in the 16- and 14-bit modes and 100% in the 12- and 10-bit
modes by increasing the supply current from 12 to 15 mA (by
using an Rc= 23 kΩ), and by increasing the sampling rate by
changing Rsto 20 kΩfor 16- and 14-bit resolution or to 15 kΩfor
12- and 10-bit resolution (see TABLE 4).
The maximum carrier frequency can, in the same way, increase
from: 5 to 10 kHz in the 16-bit mode, 7 to 14 kHz in the 14-bit
mode, 11 to 32 kHz in the 12-bit mode, and 20 to 40 kHz in the
10-bit mode (see TABLE 5).
The maximum tracking rate and carrier frequency for full perfor-
mance are set by the power supply current control resistor (Rc)
per the following tables:
1
(333,333 x 50 pF x 1.25)
Rv = = 48 kΩ
The carrier frequency should be 1/10, or less, of the sampling fre-
quency in order to have many samples per carrier cycle. The con-
verter will work with reduced quadrature rejection at a carrier fre-
quency up to 1/4 the sampling frequency. Carrier frequency should
be at least 3.5 times the BW in order to eliminate the chance of jitter.
REDUCED POWER SUPPLY CURRENTS
When Rs= 30 kΩ(tracking rate is not being pushed), nominal power
supply current can be cut from 14 to 9 mA by setting Rc= 53 kΩ.
TRANSFORMER ISOLATION
System requirements often include electrical isolation. There are
transformers available for reference and synchro/resolver signal
isolation. TABLE 6 includes a listing of the most common trans-
formers.The synchro/resolver transformers reduce the voltage to
2 Vrms for a direct connection to the converter. See FIGURES
5A, 5B, 5C and 5D for transformer layouts and schematics, and
FIGURE 6 for typical connections.
DC INPUTS
As noted in TABLE 1, the RD-19220/2 will accept DC inputs.

13
Data Device Corporation
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RDC-19220 SERIES
P-05/05-0
+S
-S
SIN
aR
R
+C
-C
COS
R
-
+
-
+
R
R
R
aR
C
1
bR
2R
2R
R
bR
+REF
-REF
R
C
2
2 WIRE LVDT
REF IN
R
2 V
FS = 2 V
FIGURE 12A. 2-WIRE LVDT DIRECT INPUT
TABLE 7. LVDT OUTPUT CODE (14-BIT R/D OR
12-BIT LVDT)
DATA
+ over full travel
+ full travel -1 LSB
+0.5 travel
+1 LSB
null
- 1 LSB
-0.5 travel
- full travel
- over full travel
01 xxxx xxxx xxxx
00 1111 1111 1111
00 1100 0000 0000
00 1000 0000 0001
00 1000 0000 0000
00 0111 1111 1111
00 0100 0000 0000
00 0000 0000 0000
11 xxxx xxxx xxxx
C1= C2, set for phase lag = phase lead through the LVDT.
Note: TABLE 7 refers to FIGURE 12C.
• Operation from 0° to 180° or 180° to 359° only. This is due to
the possibility of a unstable false null. IE: 180° hang-up.This 180°
hang-up is unstable and once the converter moves it will go to
the correct answer. In real world applications where an instanta-
neous 180° change are not possible the converter will always be
correct within 360°. The problem arises at power-up in real sys-
tems. If the converter angle powers up at exactly 180° from the
applied input the converter will not move. This is very unlikely
although it is theoretically possible. This condition is most often
encountered during wrap around verification tests, simulations or
troubleshooting.
• Set the REF input to DC by tying RH to +5V and RL to GND or
-5V.
• Set the COS and SIN inputs such that max signal will be equal
to 1.8VDC. IE: For 90°, the SIN input will equal 1.8VDC. This will
keep the BW hysteresis consistant with AC operation.
• Input offsets will affect accuracy. Verify the COS and SIN inputs
do not have DC offsets. If offsets are present , a differential op
amp configuration can be used to minimize differential offset
problems.
• With DC inputs the converter BIT will remain at logic 0.
• The Bandwidth value of the converter should be chosen based
on the rate of change of the system’s input amplitude variation,
and should be large enough so to minimize it’s effect on the sys-
tem dynamics. Note that if the bandwidth is too high the system
will be more susceptible to noise.
• The accuracy of the converter using a DC input will be degrad-
ed from the rated accuracy. Consider the best case where the
input is single ended and no additional DC offsets are present on
the input converter - the accuracy will degrade by about 2 arc
minutes. IE:, If a part is rated at 2 arc minutes, a DC input will
degrade the accuracy to approximately 4 arc minutes.
LVDT OUTPUT MSB LSB
OVER
RANGE

14
Data Device Corporation
www.ddc-web.com
RDC-19220 SERIES
Q-05/05-0
+S -S SIN
-C COS
-REF
+REF
A GND
+C
RDC-19220
+S
-S
SIN
aR
R
+C
-C
COS
R'
-
+
-
+
R/2
R
R
aR
bR
2R'
2R'
R'
bR +REF
-REF
R'
R'
R
V
B
V
A
REF
-2V
FS=2V
Notes:
1. R' > 10kΩ
2. Consideration for the value of R is LVDT loading.
3. RMS values given.
4. Use the absolute values of Va and Vb when subtracting per the formula for
calculating resistance values, and then use the calculated sign of "Va and Vb"
for calculating SIN and COS. The calculations shown are based upon full scale
travel being to the Va side of the LVDT.
5. See the RDC application manual for calculation examples.
6. Negative voltages are 180˚ phase from the reference
V
B
V
A
LVDT
OUTPUT
+FS -FSNULL COS
SIN
RDC-19220
INPUT
-FS +FSNULL
1V
2V
FIGURE 12B. 3-WIRE LVDT DIRECT INPUT
FIGURE 12C. 3-WIRE LVDT SCALING CIRCUIT
1
V
b = =
Anull
1
VBnull
2
(V - V )
a =
AB
SIN=-1V+ (V - V )
AB
a
2
COS=-1V - (V - V )
AB
a
2
max.

15
Data Device Corporation
www.ddc-web.com
RDC-19220 SERIES
P-05/05-0
DATA DATA
VALID
300 ns max
INHIBIT
100 ns MAX
ENABLE
150 ns MAX
DATA DATA
VALID
HIGH Z HIGH Z
Note: For 16 BIT BUS operation, EM/EL may be tied to ground
for transparent mode, as long as only 1 R/D channel is on
the data bus.
1/40 F
S
(375 nsec nominal)
CB
50 ns
DATA DATA
VALID
DATA
VALID
FIGURE 13. INHIBIT TIMING
FIGURE 14. ENABLE TIMING FIGURE 15. CONVERTER BUSY TIMING
VELOCITY TRIMMING
RDC-19220 Series specifications for velocity scaling, reversal
error and offset are contained in TABLE 1. Velocity scaling and
offset are externally trimmable for applications requiring tighter
specifications than those available from the standard unit. FIG-
URE 10 shows the setup for trimming these parameters with
external pots. It should also be noted that when the resolution is
changed, VEL scaling is also changed. Since the VEL output is
from an integrator with capacitor feedback, the VEL voltage can-
not change instantaneously. Therefore, when changing resolu-
tion while moving there will be a transient with a magnitude pro-
portional to the velocity and a duration determined by the con-
verter bandwidth.
INCREASED TRACKING/DECREASED SETTLING
(GEAR SHIFTING)
Connecting the BIT output to the resolution control lines (A and
B) will change the resolution of the converter down (“gear shift”)
and make the converter settle faster and track at higher rates.
The converter bandwidth is independent of the resolution.
ADDITIONAL ERROR SOURCES
Quadrature voltages in a resolver or synchro are by definition the
resulting 90° fundamental signal in the nulled out error voltage (e)
in the converter. This voltage is due to capacitive or inductive cou-
pling in the synchro or resolver signals. A digital position error will
result due to the interaction of this quadrature voltage and a refer-
ence phase shift between the converter signal and reference
inputs. The magnitude of this error is given in the following formula:
Magnitude of Error = (Quadrature Voltage/F.S.signal) • tan α
Where:
Magnitude of Error is in radians
Quadrature Voltage is in volts
Full Scale signal is in volts
α= signal to REF phase shift
An example of the magnitude of error is as follows:
Let: Quadrature Voltage = 11.8 mV
Let: F.S. signal = 11.8 V
Let: α = 6°
Then: Magnitude of Error = 0.36 min @ 1 LSB in the 16th bit.
Note: Quadrature is composed of static quadrature which is
specified by the synchro or resolver supplier plus the speed
voltage which is determined by the following formula:
Speed Voltage = (rotational speed/carrier frequency) • F.S. signal
Where:
Speed Voltage is the quadrature due to rotation.
Rotation speed is the rps (rotations per second) of the synchro
or resolver.
Carrier frequency is the REF in Hz.
PHASE SHIFT COMPENSATION
FIGURE 11 illustrates a circuit to LEAD or LAG the reference
into the converter that will compensate for phase-shift between
the signal and the reference to reduce the effects of the quadra-
ture. This should be used for greater than 6° phase shift between
Ref and COS/SIN inputs.

16
Data Device Corporation
www.ddc-web.com
RDC-19220 SERIES
Q-05/05-0
Therefore, there is no need to monitor the CB line when
applying an inhibit signal to the converter.
BUILT-IN-TEST (BIT)
The Built-ln-Test output (BIT) monitors the level of error from the
demodulator. This signal is the difference in the input and output
angles and ideally should be zero. However, if it exceeds approx-
imately 100 LSBs (of the selected resolution) the logic level at
BIT will change from a logic 1 to a logic 0.
This condition will occur during a large step and reset after the
converter settles out. BIT will also change to logic 0 for an over-
velocity condition, because the converter loop cannot maintain
input/output or if the converter malfunctions where it cannot
maintain the loop at a null. BIT will also be set low for a detect-
ed total Loss-of-Signal (LOS). The BIT signal may pulse during
certain error conditions (i.e., converter spin around or signal
amplitude on threshold of LOS).
LOS will be detected if both sin and cos input voltages are less
than 800 mV peak. The LOS has a filter on it to filter out the ref-
erence. Since the lowest specified frequency is 47hz (-27ms) the
filter must have a time constant long enough to filter this out.
Time constants of 50ms or more are possible.
ENCODER EMULATION
The RDC-19220 can be made to emulate incremental optical
encoder output signals, where such an interface is desired. This
is accomplished by tying EL to -5 V, whereby CB becomes Zero
Index (Zl) Logic 1 at all 0s, the LSB+1 becomes A, and the exclu-
sive-or of the LSB and LSB+1 becomes B emulating A QUAD B
signals as illustrated in FIGURE 16A. Also, the LSB byte is
always enabled.
FIGURE 16B illustrates a more detailed circuit with delays and
filtering to eliminate potential glitch due to data skew and rise/fall
differences caused by logic loading.
LVDT MODE
As shown in TABLE 1 the RDC-19220 Series units can be made
to operate as LVDT-to-digital converters by connecting
Resolution Control inputs A and B to “0,” “1,” or the -5 volt sup-
ply. In this mode the RDC-19220 Series functions as a ratiomet-
ric tracking linear converter. When linear ac inputs are applied
from a LVDT the converter operates over one quarter of its
range. This results in two less bits of resolution for LVDT mode
than are provided in resolver mode.
FIGURE 12B shows a direct LVDT 2 Vrms full scale input. Some
LDVT output signals will need to be scaled to be compatible with
the converter input. FIGURE 12C is a schematic of an input scal-
ing circuit applicable to 3-wire LVDTs. The value of the scaling
constant “a” is selected to provide an input of 2 Vrms at full
stroke of the LVDT. The value of scaling constant “b” is selected
to provide an input of 1 Vrms at null of the LVDT. Suggested
components for implementing the input scaling circuit are a quad
op-amp, such as a 4741 type, and precision film resistors of
0.1% tolerance. FIGURE 12A illustrates a 2-wire LVDT configu-
ration.
Data output of the RDC-19220 Series is Binary Coded in LVDT
mode. The most negative stroke of the LVDT is represented by
all zeros and the most positive stroke of the LVDT is represent-
ed by all ones. The most significant 2 bits (2 MSBs) may be
used as overrange indicators. Positive overrange is indicated by
code “01” and negative overrange is indicated by code “11” (see
TABLE 7).
INHIBIT, ENABLE, AND CB TIMING
The Inhibit (INH) signal is used to freeze the digital output angle
in the transparent output data latch while data is being trans-
ferred. Application of an Inhibit signal does not interfere with the
continuous tracking of the converter. As shown in FIGURE 13,
angular output data is valid 300 ns maximum after the applica-
tion of the negative inhibit pulse.
Output angle data is enabled onto the tri-state data bus in two
bytes. Enable MSBs (EM) is used for the most significant 8 bits
and Enable LSBs (EL) is used for the least significant 8 bits. As
shown in FIGURE 14, output data is valid 150 ns maximum after
the application of a negative enable pulse. The tri-state data bus
returns to the high impedance state 100 ns maximum after the
rising edge of the enable signal.
The Converter Busy (CB) signal indicates that the tracking con-
verter output angle is changing 1 LSB. As shown in FIGURE 15,
output data is valid 50 ns maximum after the middle of the CB
pulse. CB pulse width is 1/40 Fs, which is nominally 375 ns.
Note: The converter INH may be applied regardless of the CB
line state. If the CB is busy the converter INH will wait for
the timing to CB “Figure 15” before setting the INH latch.

17
Data Device Corporation
www.ddc-web.com
RDC-19220 SERIES
P-05/05-0
FIGURE 16B. FILTERED/BUFFERED ENCODER EMULATOR CIRCUIT
LSB +1
LSB
EL
-5 V
CB (ZI) (ZI)
A
B
FIGURE 16A. INCREMENTAL ENCODER EMULATION
LSB +1
LSB
EL
-5 V
RDC-19220
CB/NRP
R1
2k
D1
1N4148
C1
220 pF
4
5
C2
220 pF
13
12
C3
120 pF
9
10
R2
2k
U2A
74AC86
2
1
A
B
NRP
8
6
11
3
NOTE: CMOS LOGIC IS RECOMMENDED. TTL AND TTL
COMPATIBLE LOGIC WILL SKEW THE DELAYS.
U2D
74AC86
U2B
74AC86
U2C
74AC86
R3
2k

18
Data Device Corporation
www.ddc-web.com
RDC-19220 SERIES
Q-05/05-0
Built-In-TestBIT21GroundGND20
Converter BusyCB22Analog GroundA GND19
MSBBit 123Enable MSBsEM18
Bit 924Current Set
RC
17
Bit 225Sampling Set
RS
16
Bit 10
26Power Supply-5 V15
Bit 327Signal Input-S14
Bit 1128Signal Output+SIN13
Bit 429Signal Input+S12
Bit 1230Signal Input-C11
Bit 531Signal OutputCOS10
Bit 1332Signal Input+C9
Bit 633Velocity OutputVEL8
Bit 1434Vel Sum Point-VSUM7
Bit 735Neg VCO Input-VCO6
Bit 1536-Reference Input-REF5
Bit 837+Reference Input+REF4
LSBBit 1638InhibitINH3
Enable LSBs (see
note)
EL39Resolution ControlB2
Power Supply+5 V40Resolution ControlA1
DESCRIPTIONNAME#DESCRIPTIONNAME
TABLE 8. RDC-19220 PINOUTS (40-PIN)
#
-5
-15
3 TERMINAL
NEGATIVE REGULATOR
-5
6.8 V
ZENER
10.2 V
ZENER
-12
-5
-5
-15
-15
5.1 V
ZENER
79LO5
FIGURE 17. TYPICAL -5 VOLT CIRCUITS
TYPICAL -5 VOLT CIRCUITS
Since the 40-pin DDIP RDC-19220 does not have a pinout for
the -5 V inverter, it may be necessary to create a -5 V from other
supplies on the board. FIGURE 17 illustrates several possibili-
ties.
#NAME #NAME
1EL 44 Bit 16 (LSB)
2+5 V 43 Bit 8
3 A 42 Bit 15
4 B 41 Bit 7
5INH 40 Bit 14
6+REF 39 Bit 6
7-REF 38 Bit 13
8-VCO 37 Bit 5
9-VSUM 36 Bit 12
10 VEL 35 Bit 4
11 +C 34 Bit 11
12 COS 33 Bit 3
13 -C 32 Bit 10
14 +S 31 Bit 2
15 SIN 30 Bit 9
16 -S 29 Bit 1 (MSB)
17 -5 V 28 CB
18 RS 27 BIT
19 RC 26 +5C (+5 V)
20 EM 25 +CAP
21 A GND 24 GND
22 -5C (-5 V) 23 -CAP
NOTES:
1. When -5 V is applied to pin 1 (EL), Converter Busy (CB) becomes
Zero index (ZI).
2. When using the built-in -5 V inverter: connect pin 2 to 26, pin 17 to
22, and a 10 µF/10 Vdc capacitor from pin 23 (negative terminal) to
pin 25 (positive terminal). Connect a 47 µF/10 Vdc capacitor from -5
V to GND. The current drain from the +5 V supply doubles. No exter-
nal -5 V supply is needed.
TABLE 9. RDC-19222 PINOUTS (44-PIN, +5 V ONLY)
PINOUT FUNCTION TABLES BY MODEL NUMBER
The TABLES 8 and 9 detail pinout functions by the DDC model
number.
The RDC-19220 has differential inputs but requires both ±5 V
power supplies.
The RDC-19222 has differential inputs and can be used with the
+5 V only option.

19
Data Device Corporation
www.ddc-web.com
RDC-19220 SERIES
P-05/05-0
2.000 ±0.020
(50.8 ±0.51)
0.590 ±0.010
(14.99 ±0.25)
0.100 ±0.010 TYP
(2.54 ±0.25)
0.018 ±0.006 TYP
(0.46 ±0.15)
0.050 ±0.020 TYP
(1.27 ±0.51)
0.012 ±0.004 TYP
(0.31 ±0.10)
+0.050
0.600
- 0.020
+1.27
(15.25 )
- 0.51
DIMENSIONS SHOWN ARE IN INCHES (MM).
1
20
0.125 ±0.020
(3.18 ±0.508)
0.050 ±0.010
(1.27 ±0.25)
0.115 ±0.010
(2.921 ±0.25)
40
21
PIN NUMBERS
FOR REF ONLY
0.095 ±0.010
(2.41 ±0.25)
FIGURE 18. RDC-19220 (40-PIN DDIP) CERAMIC PACKAGE MECHANICAL OUTLINE

20
Data Device Corporation
www.ddc-web.com
RDC-19220 SERIES
Q-05/05-0
ALTERNATE PIN 1 IDENTIFIER
0.650 SQ. NOM
(16.51)
0.690 SQ. ±.005
(17.53)
DIMENSIONS SHOWN ARE IN INCHES (MM) TOLERANCE IN INCHES
PIN 1 IDENTIFIER
.050 ± .002
(1.27)
0.010 x 45˚ CHFR (3)
(0.25)
640
.020 MIN
.620 SQ
± .010
(15.75)
.016 ± .005 (.41)
.155 MAX
(3.94)
PIN #'S SHOWN
FOR REFERENCE ONLY
0.630 ±0.020 TYP
(16.00 ±0.51)
0.500 ±0.010
(12.70 ±0.25)
DIMENSIONS SHOWN ARE IN INCHES (MM)
0.020 x 45˚
(0.51)
CHAMFER
(ORIENTATION
MARK)
0.040 x 45˚
CHAMFER
(1.02)
(3 PLACES) 0.143 ± 10 (REF)
(3.63)
0.095 ±0.007
(2.413 ±0.18)
640
0.075 ±0.010
(1.91 ±0.25)
17
18 28
29
39
1
0.075 ±0.010
(1.91 ±0.25)
0.500 ±0.010
(12.70 ±0.25)
0.050 TYP
(1.27)
7
0.650 SQ ±0.010
(16.51 ±0.25)
0.690 ±0.010 TYP
(17.53 ±0.25)
PIN NUMBERS
FOR REF ONLY
0.017 TYP
(0.43)
FIGURE 19. RDC-19222 (44-PIN PLASTIC J-LEAD) MECHANICAL OUTLINE
FIGURE 20. RDC-19222 (44-PIN CERAMIC J-LEAD) MECHANICAL OUTLINE