Denon ADV-M71 User manual

SERVICE MANUAL
MODEL ADV-M71
DVD SURROUND RECEIVER
For U.S.A., Canada
& Japan model
16-11, YUSHIMA 3-CHOME, BUNKYOU-KU, TOKYO 113-0034 JAPAN
X0182V.01 DE/CDM 0307
注 意
サービスをおこなう前に、このサービスマニュアルを
必ずお読みください。本機は、火災、感電、けがなど
に対する安全性を確保するために、さまざまな配慮を
おこなっており、また法的には「電気用品安全法」に
もとづき、所定の許可を得て製造されております。
従ってサービスをおこなう際は、これらの安全性が維
持されるよう、このサービスマニュアルに記載されて
いる注意事項を必ずお守りください。
● 本機の仕様は性能改良のため、予告なく変更すること
があります。
● 補修用性能部品の保有期間は、製造打切後 8年です。
Some illustrations using in this service manual are
slightly different from the actual set.
●
●
Please use this service manual with referring to
the operating instructions without fail.
●
For purposes of improvement, specifications and
design are subject to change without notice.
●
修理の際は､必ず取扱説明書を参照の上、作業を行って,
ください。
● 本文中に使用しているイラストは、説明の都合上現物
と多少異なる場合があります。
Ver. 1
w w w . x i a o y u 1 6 3 . c o m
Q Q
3
7
6 3
1 5 1 5
0 9 9
2
8 9
4 2
9 8
T E L 1 3 9 4 2 2 9 6 5 1 3 9 9 2 8 9 4 2 9 8 0 5 1 5 1 3 6 7 3
Q Q
TEL [phone] QQ 376315150 892498299 TEL [phone] QQ 376315150 892498299
http://www.xiaoyu163.com
http://www.xiaoyu163.com

2
2
ADV-M71
SAFETY PRECAUTIONS
Thefollowingcheckshouldbeperformedforthecontinuedprotectionofthecustomerandservicetechnician.
LEAKAGE CURRENT CHECK
Beforereturningtheunittothecustomer,makesureyoumakeeither(1)aleakagecurrentcheckor(2)alinetochassis
resistancecheck.Iftheleakagecurrentexceeds0.5milliamps,oriftheresistancefromchassistoeithersideofthe
powercordislessthan460kohms,theunitisdefective.
LASER RADIATION
Donotstareintobeamorviewdirectlywithopticalinstruments,class3Alaserproduct.
(1)
(2)
500V
1M
(1)
(2)
w w w . x i a o y u 1 6 3 . c o m
Q Q
3
7
6 3
1 5 1 5
0 9 9
2
8 9
4 2
9 8
T E L 1 3 9 4 2 2 9 6 5 1 3 9 9 2 8 9 4 2 9 8 0 5 1 5 1 3 6 7 3
Q Q
TEL [phone] QQ 376315150 892498299 TEL [phone] QQ 376315150 892498299
http://www.xiaoyu163.com
http://www.xiaoyu163.com

3
3
ADV-M71
DISASSEMBLY
(Follow the procedure below in reverse order when reas-
sembling)
1. TOP COVER
Remove 2 screws on both sides and 4 screws on the rear,
then detach upward the Top Cover.
各部のはずしかた
（組み立てるときは、逆の順序でおこなってください。）
1. トップカバーのはずしかた
両サイドのからねじ 2本、リアパネルからのねじ 4本を
はずし、トップカバーを上にはずします。
2. FRONT PANEL
(1)Disconnect FFC and 3p WIRG on the P.W.B..
(2)Remove 4 lower screws.
(3)Detach the Front Panel with releasing the hook on both
sides.
FRONT PANEL
FFC
DVD MECHA
3P WIRG
HOOK
2. フロントパネルのはずしかた
(1)基板から、FFC と 3P ワイヤをはずします。
(2)FRONTPANELの下側からねじ 4 本をはずします。
(3)両サイドの HOOK をはずし、FRONTPANEL をはずし
ます。
w w w . x i a o y u 1 6 3 . c o m
Q Q
3
7
6 3
1 5 1 5
0 9 9
2
8 9
4 2
9 8
T E L 1 3 9 4 2 2 9 6 5 1 3 9 9 2 8 9 4 2 9 8 0 5 1 5 1 3 6 7 3
Q Q
TEL [phone] QQ 376315150 892498299 TEL [phone] QQ 376315150 892498299
http://www.xiaoyu163.com
http://www.xiaoyu163.com

4
4
ADV-M71
3. DVD MECHANISM UNIT
(1)Remove 5 screws to detach the MECHA COVER and
the DVD Mecha.
(2)Disconnect WIRG from the DVD Mecha.
DVD MECHA
EARTH CLIP
MECHA COVER
3. DVDメカのはずしかた
(1)ねじ 6 本をはずし、MECHACOVERとDVDMECHA-
EARTHCLIPをはずします。
(2)DVDMECHAからワイヤをはずします。
4. REAR PANEL
(1)Pull out the cord bush.
(2) Remove 26 screws.
CORD BUSH
4. リアパネルのはずしかた
(1)CORDBUSHをはずします。
(2)ねじ 26 本をはずします。
w w w . x i a o y u 1 6 3 . c o m
Q Q
3
7
6 3
1 5 1 5
0 9 9
2
8 9
4 2
9 8
T E L 1 3 9 4 2 2 9 6 5 1 3 9 9 2 8 9 4 2 9 8 0 5 1 5 1 3 6 7 3
Q Q
TEL [phone] QQ 376315150 892498299 TEL [phone] QQ 376315150 892498299
http://www.xiaoyu163.com
http://www.xiaoyu163.com

5
5
ADV-M71
5. POWER P.W.B. / AMP VIDEO P.W.B.
(1)Remove 3 screws to detach the P.W.B. BRACKET
together with the POWER P.W.B..
(2)Unplug 4 connectors on the POWER P.W.B..
(3)Remove 3 screws.
POWER P.W.B.
AMP VIDEO P.W.B.
(3)
(1)
(3)
PVC SHEET
P.W.B. BRACKET
(1)
(1)
5. パワー基板／アンプビデオ基板
(1)ねじ 3 本をはずし、POWERP.W.B.といっしょにP.W.B.
BRACKETをはずします。
(2)POWERP.W.B.のコネクタ４か所をはずします。
(3)ねじ３本をはずします。
6. MAIN P.W.B.
(1)Remove 2 screws fixing the P.W.B. stay.
(2)Remove 3 screws.
P.W.B. STAY
MAIN P.W.B.
6. メイン基板
(1)P.W.B.STAYを止めているねじ２本をはずします。
(2)ねじ 3 本をはずします。
w w w . x i a o y u 1 6 3 . c o m
Q Q
3
7
6 3
1 5 1 5
0 9 9
2
8 9
4 2
9 8
T E L 1 3 9 4 2 2 9 6 5 1 3 9 9 2 8 9 4 2 9 8 0 5 1 5 1 3 6 7 3
Q Q
TEL [phone] QQ 376315150 892498299 TEL [phone] QQ 376315150 892498299
http://www.xiaoyu163.com
http://www.xiaoyu163.com

6
6
ADV-M71
7. DISPLAY P.W.B.
(1)Pull out the VR knob and TUNING knob.
(2)Remove the spacer and the VR nut.
(3)Remove 7 screws.
TUNNING KNOB
VR KNOB
SPACER
VR NUT
7. ディスプレイ基板
(1)VRKNOBとTUNINGKNOBをはずします。
(2)SPACERとVRNUTをはずします。
(3)ねじ７本をはずします。
w w w . x i a o y u 1 6 3 . c o m
Q Q
3
7
6 3
1 5 1 5
0 9 9
2
8 9
4 2
9 8
T E L 1 3 9 4 2 2 9 6 5 1 3 9 9 2 8 9 4 2 9 8 0 5 1 5 1 3 6 7 3
Q Q
TEL [phone] QQ 376315150 892498299 TEL [phone] QQ 376315150 892498299
http://www.xiaoyu163.com
http://www.xiaoyu163.com

7
7
ADV-M71
DVD ENGINE UNIT RL-871 1U-3528 AMP/POWER UNIT
:IC :DVD Engine Block
SWITCHING POWER SUPPLY EEPROM PROG/INTE
16k DVD MECHA ROM RAM VCNT1/YC_H
PU/Traverse FRONT END VCNT2/WIDE
Loadin
g
RGB
_
H
LINE_2
DVD ON/OFF DI/DO/CS/CK
FL TUBE P ON/OFF for VDAC ex
p
and VIDEO DRIVER LINE_3
HNV-15SS04T SUB ON/OFF
(
UD-M30DVx : no use
)
with Filter
50/60
BACK END DSP
YUV[0
-
7]
BH7862 PY/Y
13digit Dot Matrix SYSTEM uCOM ES6028 PY/Y PY IN
VIDEO DAC 4ch
C
Pb/Cb
M30626 FHPGP with Pro
g
ressive scan Pb/Cb Pb IN
P
r
/C
rPr IN Pr/Cr
CLK YIN Y
SDATA I/O CIN C OUT C
FL DRIVER DA/CK/CE/RST
CS
AUDIO DECODER
MIXOUT V
M66005AFP
RESET
D
.
D/DTS/PCM/AAC
PLII/MP3/
(
WMA
)
/2chVirtual
User I/F ( MCLK)
(
PPCM
(
DVD-Audio
))
VR
-
JOG
A/B TBCK
KEY
KEY
-
0/1
Develo
p
ed TWS
D
own
Mi
x
V
.
MUTE 1/2
Y
Y/C
ROTARY ENCODER
LED-R
b
y
MONITOR OUT
LED LED-G DENON BASS Management C
Config-1(ON/OFF each CH)
ROM
REMOCON REMOTE
16MB
D
e
l
ay
C
ompos
it
e
GP1UE271XK AUDIO DSP MONITOR OUT
MELODY 100
RXD ADSST-MEL100 SPDIF RSD TSD3 TSD 2 TSD 1 TSD 0
TXD
DENON BUS
CLK
x2
SD-RAM FAN ON/OFF COOLING FAN
Communicate with DENON-BUS : MD/DECK/CD-R 64MB
SPDIF OUT
PCM/D.D/DTS bitstream H/P AMP
OPT OUT RESET/ACK/REQUEST/BUSY NJM4556AD
[GP1Z352TZ] WRIGHT/OSC/IOPOWER/POM_RST
I/O1
䌾
I/O7
DIR
OPT IN 1
RXOUT
LC89057
1U-3527 MAIN UNIT H/P
[GP1F352RZ] SPDIF SDATA
PCM/AAC/D.D/DTS bitstream SPDIF RWS
OPT IN 2 DIN 0 RBCK
[GP1F352RZ] PCM MCLK H/P MUTE
H/P SW
DI/DO/CE/CLK
STEREO
DI/DO/CE/CLK/RST
TUNED [I2S x 3] ERR/CS FLAG/96DET
SYR
AUDIO/EMPHA/INT
DATA
VR MUTE
FL/FR
PROTECT
CLK
C
THERMO
FM ANT
SL/SR
RELAY FR
FM/AM SDATA(AD) DO/CE/CLK/RST ERR MUTE SUB SUM VR OUTPUT GAIN SW
TUNER PACK LRCK/BCK for SP Config-2 SWITCHING 0䌾+18dB PRE AMP
AM ANT NJM2068 BA15218 BA15218 DSP/EXT/DIRECT BASS/TREBLE SDB 2dBstep BA15218
[
+
6dB]
[0dB]
FL
PASS
POWER AMP
[STK-402-050]
MUTING
TU
.
MUTE
FR
LINE-1 IN C
MUTE
LINE-2 IN SL
SR
LINE-1 OUT LFE
BA15218
8ch CODEC Max output
LINE-2 OUT AD1837 DMIXL [0dB] 4.2Vrms
INPUT GAIN AMP
for RECOUT 0/+6dB
DMIXR FUNCTION/VR/TONE/SDB IC
BD3811K1
1U-3528 AMP/POWER UNIT
㪤㪬㪫㪜
㪤㪬㪫㪜
㪤㪬㪫㪜
㪤㪬㪫㪜
㪤㪬㪫㪜
㪤㪬㪫㪜
MUTE
MUTE
MUTE
FL
A/D CONVERTER
㪏㪺㪿㩷㪛㪆㪘㩷㪚㪦㪥㪭㪜㪩㪫㪜㪩
DIGITAL IN/OUTAUDIO IN/OUT
SPEAKER OUT
J:D-TERMINAL VIDEO OUT
FR
SR
SL
SW
C
MUTE
MUTE
MUTE
MUTE
MUTE
PRE OUT
DISC information is
received from DVD
and it displays it in the
FL tube.
Mute PY/Pb/Pr or Y/C/V
constantly
Route of
DIRECT mode
E3:COMPONENT VIDEO OUT
㪤㪬㪫㪜
㪤㪬㪫㪜
BLOCK DIAGRAMS
w w w . x i a o y u 1 6 3 . c o m
Q Q
3
7
6 3
1 5 1 5
0 9 9
2
8 9
4 2
9 8
T E L 1 3 9 4 2 2 9 6 5 1 3 9 9 2 8 9 4 2 9 8 0 5 1 5 1 3 6 7 3
Q Q
TEL [phone] QQ 376315150 892498299 TEL [phone] QQ 376315150 892498299
http://www.xiaoyu163.com
http://www.xiaoyu163.com

8
8
ADV-M71
FL/FR
VR MAX: 12.6Vrms
VR MAX : 632mVrms
VR " 00 " : 80mVrms
VR MAX : 632mVrms
VR " 00 " : 80mVrms
(20W, 8Ω)
POWER AMPPRE AMP
SP OUTFL/FR
SL/SR/C
SW
FL/FR
SL/SR/C
SW
FL/FR
DIGITAL
OPT IN
SL/SR/C
SL/SR/C ch
SW
30dB
+6dB
+6dB
-15dB
+10dB
470
470
For
Config2
Prologic
Prologic
+3.31dB
+2.85dB
+7.5dB
Config-2
Config-1
-18dB
+6dB
26.4dB
at VR "00"
-18dB
atVR"00"
To Front ch
+6dB
+10dB
21.0dB
21.0dB
30dB
FL/FR
SL/SR/C
+19dB
MUTE
MUTE
TONE
SDB
MUTE
MUTE
MUTE
MUTE
8ch
D/A
2ch
A/D
AD1837
8ch CODEC
BD3811
ELEC. VR
ELEC. VR Head Room (4.2Vrms)
ELEC. VR Head Room (4.2Vrms)
PRE AMP Head Room (7.0Vrms)
DSP
DIR
0dBFs
-20dBFs
ANALOG
LINE IN
ANALOG L/R ch
FL/FR ch
DIGITAL
SW ch
ANALOG ANALOG DIRECT ANALOG DIRECT
To A/D
200mVrms
-10dBFs
-20dBFs
-23dB
=1Vrms
0dBFs
-10dBFs
-20dBFs
-30dBFs
-35dBFs
=1Vrms
Input Sens : 200mVrms
SP Output Power : 20W (THD 0.08%,8Ω)
Total GAIN : 36dB
PRE AMP Head Room (7.0Vrms)
-6dB
L,R
LEVEL DIAGRAMS
w w w . x i a o y u 1 6 3 . c o m
Q Q
3
7
6 3
1 5 1 5
0 9 9
2
8 9
4 2
9 8
T E L 1 3 9 4 2 2 9 6 5 1 3 9 9 2 8 9 4 2 9 8 0 5 1 5 1 3 6 7 3
Q Q
TEL [phone] QQ 376315150 892498299 TEL [phone] QQ 376315150 892498299
http://www.xiaoyu163.com
http://www.xiaoyu163.com

9
9
ADV-M71
SEMICONDUCTORS
Only major IC's are shown, general IC's etc. are omitted to list.
主な半導体を記載しています。汎用の半導体等は記載を省略しています。
●IC's
Note: Abbreviation ahead of IC No. indicates the name of P.W.B., etc.
注) : IC No. の前の記号は、基板の名称を表します。
DS : DSP P.W.B. AP: AMP/POWER P.W.B.
MA: Main P.W.B. ME : MECHA P.W.B.
ADSST-MEL100(DS:IC801)
Note : When this IC is defecitive, replace P.W.B. Unit Ass'y
NC A01
BMSTR A02
BMS_B A03
SPIDS A04
EBOOT A05
LBOOT A06
SCLK2 A07
SD3B A08
L0DAT[4] A09
L0ACK A10
L0DAT[2] A11
L1DAT[6] A12
L1CLK A13
L1DAT[2] A14
NC A15
FLAG10 E01
RESET_B E02
FLAG8 E03
SD0A E04
VDDEXT E05
VDDINT E06
VDDEXT E07
VDDINT E08
VDDEXT E09
VDDINT E10
VDDEXT E11
L0DAT[0] E12
DATA[39] E13
DATA[43] E14
TRST_B B01
TD1 B02
RPBA B03
MOSI B04
SFS0 B05
SCLK1 B06
SD2B B07
SD3A B08
L0DAT[7] B09
L0CLK B10
L0DAT[1] B11
L1DAT[4] B12
L1ACK B13
L1DAT[0] B14
NC B15
FLAG5 F01
FLAG7 F02
FLAG9 F03
FLAG6 F04
VDDINT F05
GND F06
GND F07
GND F08
GND F09
GND F10
VDDINT F11
DATA[37] F12
DATA[40] F13
DATA[38] F14
TMS C01
EMU_B C02
GND C03
SPICLK C04
SD08 C05
SD1A C06
SD2A C07
SFS2 C08
SFS3 C09
L0DAT[6] C10
L1DAT[7] C11
L1DAT[3] C12
L1DAT[1] C13
DATA[45] C14
DATA[47] C15
FLAG1 G01
FLAG2 G02
FLAG4 G03
FLAG3 G04
VDDEXT G05
GND G06
GND G07
GND G08
GND G09
GND G10
VDDEXT G11
DATA[34] G12
DATA[35] G13
DATA[33] G14
DATA[41] E15
IRQ2_B J01
ID1 J02
ID2 J03
ID0 J04
VDDEXT J05
GND J06
GND J07
GND J08
GND J09
GND J10
VDDEXT J11
DATA[26] J12
DATA[24] J13
DATA[25] J14
DATA[27] J15
ADDR[14] N01
ADDR[15] N02
ADDR[10] N03
ADDR[5] N04
ADDR[1] N05
MS0_B N06
BR5_B N07
BR2_B N08
BRST N09
SDCKE N10
CS_B N11
CLK_CFG1 N12
CLK_CFG0 N13
AVDD N14
DMARI1_B N15
DATA[36] F15
TIMEXP K01
ADDR[22] K02
ADDR[20] K03
ADDR[23] K04
VDDINT K05
GND K06
GND K07
GND K08
GND K09
GND K10
VDDINT K11
DATA[22] K12
DATA[19] K13
DATA[21] K14
DATA[23] K15
ADDR[13] P01
ADDR[9] P02
ADDR[8] P03
ADDR[4] P04
MS2_B P05
SBTS_B P06
BR4_B P07
BR1_B P08
SDCLK1 P09
SDCLK0 P10
REDY P11
CLKIN P12
DQM P13
AVSS P14
DMAR2_B P15
DATA[32] G15
ADDR[19] L01
ADDR[17] L02
ADDR[21] L03
ADDR[2] L04
VDDEXT L05
VDDINT L06
VDDEXT L07
VDDINT L08
VDDEXT L09
VDDINT L10
VDDEXT L11
CAS_B L12
DATA[20] L13
DATA[16] L14
DATA[18] L15
NC R01
ADDR[11] R02
ADDR[7] R03
ADDR[3] R04
MS3_B R05
PA_B R06
BR3_B R07
RDL_B R08
CLKOUT R09
HBR_B R10
HBG_B R11
CLKDBL R12
XTAL R13
SDWE_B R14
NC R15
DATA[31] H15
ADDR[16] M01
ADDR[12] M02
ADDR[18] M03
ADDR[6] M04
ADDR[0] M05
MS1_B M06
BR6_B M07
VDDEXT M08
WRL_B M09
SDA10 M10
RAS_B M11
ACK M12
DATA[17] M13
DMAG2_B M14
DMAG1_B M15
ADSST-MEL100 Terminal Function
Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No.
TOP VIEW
BOTTOM VIEW
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
B
C
D
E
F
G
H
J
K
L
M
N
P
R
w w w . x i a o y u 1 6 3 . c o m
Q Q
3
7
6 3
1 5 1 5
0 9 9
2
8 9
4 2
9 8
T E L 1 3 9 4 2 2 9 6 5 1 3 9 9 2 8 9 4 2 9 8 0 5 1 5 1 3 6 7 3
Q Q
TEL [phone] QQ 376315150 892498299 TEL [phone] QQ 376315150 892498299
http://www.xiaoyu163.com
http://www.xiaoyu163.com

10
10
ADV-M71
ES6028 (ME: U9)
FunctionI/OPin No. Pin Name
ES6038 Terminal Function
1, 18, 27, 59,
68, 75, 92, 99,
104, 130, 148, VEE I I/O power supply.
157, 159, 164,
183, 193, 201
8, 17, 26, 34,
43, 52, 60, 67,
76, 84, 91, 98,
103, 112, 120, VSS I Ground.
129, 138, 147,
156, 163, 171,
177, 184, 192,
200, 208
23:19, 16:10,
7:2, 207:204 LA[21:0] O Device address output.
9, 35, 44, 83,
121, 139, 172 VCC I Core power supply.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
VEE
LA4 LA5 LA6 LA7 LA8 LA9
VSS
VCC
LA10 LA11 LA12 LA13 LA14 LA15 LA16
VSS VEE
LA17 LA18 LA19 LA20 LA21
RESET#
TDMDX
VSS VEE
TDMDR
TDMCLK
TDMFS
TDMTSC#
TWS/SEL_PLL2
TSD0/SEL_PLL0
VSS
VCC
TSD1/SEL_PLL1
TSD2 TSD3
MCLK
TBCK
SPDIF/PLL3
NC
VSS
VCC RSD
RWS
RBCK
NC
XIN
XOUT
AVEE
VSS
DMA0
DMA1
DMA2
DMA3
DMA4
DMA5
VEE
VSS
DMA6
DMA7
DMA8
DMA9
DMA10
DMA11
VSS
VEE
DCAS#
DSCK_EN
DWE#
DRAS#
DMBS0
DMBS1
VEE
VSS
DB0
DB1
DB2
DB3
DB4
DB5
VCC
VSS
DB6
DB7
DB8
DB9
DB10
DB11
VSS
VEE
DB12
DB13
DB14
DB15
DCS1#
VSS
VEE
DCS0#
DQM
DSCK
VSS
VEE
VSS HA1 HA0 HCS3FX# HCS1FX# HIOCS16# HRD# HWR# VEE VSS HIORDY HRST# HIRQ HRDQ# HWRQ# HD15 HD14 VCC VSS HD13 HD12 HD11 HD10 HD9 HD8 HD7 VEE VSS HD6 HD5 HD4 HD3 HD2 HD1 HD0 VCC VSS HSYNC# VSYNC# PCLKQSCN PCLK2XSCN YUV7 YUV6 YUV5 VSS ADVEE YUV4 YUV3 YUV2 YUV1 YUV0 DCLK
VSS
LA3
LA2
LA1
LA0
CAMIN1
CAMIN0
VEE
VSS
LWRHL#
LWRLL#
LD15
LD14
LD13
LD12
VEE
VSS
LD11
LD10
LD9
LD8
LD7
LD6
LD5
VSS
VEE
LD4
LD3
LD2
LD1
LD0
VSS
LCS3#
LCS2#
LCS1#
LCS0#
VCC
VSS
LOE#
AUX[7]
AUX[6]
AUX[5]
AUX[4]
AUX[3]
VEE
VSS
AUX[2]
AUX[1]
AUX[0]
VEE
HA2
VEE
w w w . x i a o y u 1 6 3 . c o m
Q Q
3
7
6 3
1 5 1 5
0 9 9
2
8 9
4 2
9 8
T E L 1 3 9 4 2 2 9 6 5 1 3 9 9 2 8 9 4 2 9 8 0 5 1 5 1 3 6 7 3
Q Q
TEL [phone] QQ 376315150 892498299 TEL [phone] QQ 376315150 892498299
http://www.xiaoyu163.com
http://www.xiaoyu163.com

11
11
ADV-M71
24 RESET# I Reset input, active low.
25 TDMDX O TDM transmit data.
28 TDMDR I TDM receive data.
29 TDMCLK I TDM clock input.
30 TDMFS I TDM frame sync.
31 TDMTSC# O TDM output enable.
TWS O Audio transmit frame sync.
SEL_PLL2 I System and DSCK output clock frequency selection is made at the rising edge of RESET#.
The matrix below lists the available clock frequencies and their respective PLL bit settings.
SEL_PLL2 SEL_PLL1 SEL_PLL0 Clock Type
0 0 0 VCO off.
0 0 1 DCLK
32 0 1 0 Bypass mode
0 1 1 DCLK x 2
1 0 0 DCLK x 4.5
1 0 1 DCLK x 3
1 1 0 DCLK x 3.5z
1 1 1 DCLK x 4
33 TSD0 O Audio transmit serial data port 0.
SEL_PLL0 I Refer to the description and matrix for SEL_PLL2 pin 32.
36 TSD1 O Audio transmit serial data port 1.
SEL_PLL1 I Refer to the description and matrix for SEL_PLL2 pin 32.
37 TSD[2] O Audio transmit serial data output 2.
38 TSD[3] O Audio transmit serial data output 3.
39 MCLK I/O Audio master clock for audio DAC.
40 TBCK O Audio transmit bit clock.
SPDIF O S/PDIF output.
SEL_PLL3 I Clock source select.
41 SEL_PLL3 Clock Source
0 Crystal oscillator
1 DCLK input
42,48 NC No connect pins. Leave open.
45 RSD I Audio receive serial data.
46 RWS I Audio receive frame sync.
47 RBCK I Audio receive bit clock.
49 XIN I Crystal input.
50 XOUT O Crystal output.
51 AVEE I Analog power for PLL.
66:61, 58:53 DMA[11:0] O DRAM address bus [11:0]
69 DCAS# O DRAM column address strobe,
70 DSCK_EN O DRAM clock enable.
71 DWE# O DRAM write enable.
72 DRAS# O DRAM row address strobe.
73 DMBS0 O SDRAM bank select 0.
74 DMBS1 O SDRAM bank select 1.
96:93, 90:85,
82:77 DB[15:0] I/O DRAM data bus [15:0]
97, 100 DCS[1:0]# O SDRAM chip select [1:0]
101 DQM O Data input/output mask.
102 DSCK O Output clock to SDRAM.
105 DCLK I 27 MHz clock input to PLL.
106 UDAC OVideo UDAC output.
107 VREF I Internal voltage to video DAC.
108 CDAC OVideo CDAC output.
109 COMP I Compensation input.
110 RSET I DAC current adjustment resistor input.
111 ADVEE I Analog power for video DAC.
113 YDAC OVideo YDAC output.
FunctionI/O
Pin No. Pin Name
w w w . x i a o y u 1 6 3 . c o m
Q Q
3
7
6 3
1 5 1 5
0 9 9
2
8 9
4 2
9 8
T E L 1 3 9 4 2 2 9 6 5 1 3 9 9 2 8 9 4 2 9 8 0 5 1 5 1 3 6 7 3
Q Q
TEL [phone] QQ 376315150 892498299 TEL [phone] QQ 376315150 892498299
http://www.xiaoyu163.com
http://www.xiaoyu163.com

12
12
ADV-M71
114 VDAC OVideo VDAC output.
115 YUV7 O YUV7 pixel output data.
116 PCLK2XSCN I/O 27 MHz video output pixel clock.
117 PCLKQSCN O 13.5 MHz video output pixel clock.
118 VSYNC# I/O Vertical sync, active low.
119 HSYNC# I/O Horizontal sync, active low.
127:122 HD[5:0] I/O Host data I/O [5:0].
128 HD[6] I/O Host data I/O [6].
131 HD[7] I/O Host data I/O [7].
132 HD[8] I/O Host data bus 8.
133 HD[9] I/O Host data bus line 9.
134 HD[10] I/O Host data bus line 10.
135 HD[11] I/O Host data bus line 11.
136 HD[12] I/O Host data bus line 12.
137 HD[13] I/O Host data bus line 13.
140 HD[14] I/O Host data bus line 14.
141 HD[15] I/O Host data bus line 15.
142 HWRQ# O Host write request.
143 HRRQ# O Host read request.
144 HIRQ I/O Host interrupt.
145 HRST# O Host reset.
146 HIORDY I Host I/O ready.
149 HWR# I/O Host write.
150 HRD# O Host read.
151 HIOCS16# I Device16-bit data transfer.
152 HCS1FX# O Host select 1.
153 HCS3FX# O Host select 3.
158, 155:154 HA[2:0] I/O Host address bus.
160 AUX[0] O I2C DATA.
162 AUX[2] I/O Auxiliary ports 2.
165 AUX[3] I/O Auxiliary ports 3.
169:166 AUX[7:3] I/O Auxiliary ports 7:3.
170 LOE# O Device output enable.
176:173 LCS[3:0]# O Chip select [3:0].
197:194,
191:185, LD[15:0] I/O EPROM device data bus.
182:178
198 LWRLL# O Device low-byte write enable.
199 LWRHL# O Device high-byte write enable.
202 CAMIN0 I Camera YUV 0.
203 CAMIN1 I Camera YUV 1.
FunctionI/O
Pin No. Pin Name
161AUX[1]OI2C CLK.
w w w . x i a o y u 1 6 3 . c o m
Q Q
3
7
6 3
1 5 1 5
0 9 9
2
8 9
4 2
9 8
T E L 1 3 9 4 2 2 9 6 5 1 3 9 9 2 8 9 4 2 9 8 0 5 1 5 1 3 6 7 3
Q Q
TEL [phone] QQ 376315150 892498299 TEL [phone] QQ 376315150 892498299
http://www.xiaoyu163.com
http://www.xiaoyu163.com

13
13
ADV-M71
M5705 (ME: U1)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
AVSS-DS
XSRFIN
XSIPIN
AVDD5-DS
XSDSSLV
XSRSLINT
VDD
XSAWRC
XSRFGC
XSEFGC
XSFOCUS
XSTRACK
XSSLEG
AVDD5-DA
XSMOTOR
AVSS-DA
XSRFRPLP
XSTELP
XSVREF2
XSRFRP
XSTEXI
AVSS-AD
XSTEI
XSFEI
XSAEI
AVDD5-AD
XSSBAD
GND
XSDFCT
XSCSJ
XSCLK
XSDATA
XSLDC
XSFGIN
XSSPDON
XSFLAG(3)
XSFLAG(2)
XSFLAG(1)
XSFLAG(0)
XMP1_7
XMP1_6
GND
NC
XMP1_4
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
XRD(3)
XRD(12)
GND
XRD(2)
XRD(13)
XRD(1)
XRD(14)
XRD(0)
XRD(15)
XHD(7)
XHD(8)
XHD(6)
XHD(9)
XHD(5)
XHD(10)
XHD(4)
XHD(11)
VDD
XHD(3)
XHD(12)
XHD(2)
XHD(13)
GND
XHD(1)
XHD(14)
XHD(0)
XHD(15)
XHDRQ
XHIOWJ
XHIORJ
XHIORDY
XHDACKJ
XHINT
XHCS16J
XHA(1)
XHPDIAGJ
XHA(0)
XHA(2)
XHCS1J
XHCS3J
XHDASPJ
XMA(15)
XMA(14)
XMA(13)
45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
XMP1_3
XMFSCSJ
XMP1_2
XGPIO(2)
XMP1_1
XMRSTJ
XGPO(1) XGPO(0)
XCRSTJ
XMPSENJ
VDD
XMALE
XMP1_0
VDD
XOSC1 XOSC2
GND
XMD(0) XMD(1) XMD(2) XMD(3) XMD(4) XMD(5) XMD(6) XMD(7)
XMCSJ
XMRDJ
XMWRJ
XMINT1J
XMA(11) XMA(10)
VDD
XMA(9) XMA(8) XMA(7) XMA(6) XMA(5) XMA(4) XMA(3) XMA(2) XMA(1) XMA(0)
XMA(12)
GND
176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133
XSAWRCVCO XSVREFO XSPDOFTR2 XSVR_PLL XSFTROPI XSFDO AVSS_PL XSPLLFTR2 AVDD5_PL XSFDIREF XSPDIREF GND XTSLRF XTPLCK VDD XRA(3) XRA(2) XRA(1) XRA(0) XRA(4) XRA(5) XRA(6) GND XRA(7) XRA(10) XRA(11) VDD XRA(8) XRA(9) XROEJ VDD XRCASJ XRRASJ XRSDCLK XRWEJ XRD(7) XRD(8) XRD(6) GND XRD(9) XRD(5) XRD(10) XRD(4) XRD(11)
Data
Separator
ATAPI
&
MPEG
I/F
Digital
Servo
DVD-DSP RAM
Arbiter
Target
Search
ROM
C3 ECC
EDC
MPEG
DEC.
Motor
Driver
PC
4M DRAM
CD-DSP MCU
M
M5705
M5705 Terminal Function
DescriptionPin No. Pin Name Type
2 XSRFIN I/A Analog RF signal input after passing through the equalizer
3 XSIPIN I/A Inverting input pin of data slicer
5 XSDSSLV O/A Slice level output pin
6 XSRSLINT I/A Reference current setting pin for analog data slicer
8 XSAWRC O/A Output for enlarge VCO range. Analog output from DAC buffer
9 XSRFGC O/A RF gain control output
10 XSEFGC O/A E,F gain control output
11 XSFOCUS O/A Output voltage level for focusing buffer IC
12 XSTRACK O/A Output voltage level for tracking buffer IC
13 XSSLEG O/A Output voltage level for sledge buffer IC
15 XSMOTOR O/A Output voltage level for spindle motor buffer IC
17 XSRFRPLP I/A High bandwidth low pass filter input for RFRP
18 XSTELP I/A High bandwidth low pass filter input for TE
19 XSVREF2 I/A 2.1V reference voltage input
20 XSRFRP I/A RF ripple/envelope signal input
21 XSTEXI I/A Tracking zero crossing input signal
23 XSTEI I/A Tracking error input signal
24 XSFEI I/A Focus error input signal
25 XSCEI I/A 1. Center error input signal
2. Photo Interrupt input
w w w . x i a o y u 1 6 3 . c o m
Q Q
3
7
6 3
1 5 1 5
0 9 9
2
8 9
4 2
9 8
T E L 1 3 9 4 2 2 9 6 5 1 3 9 9 2 8 9 4 2 9 8 0 5 1 5 1 3 6 7 3
Q Q
TEL [phone] QQ 376315150 892498299 TEL [phone] QQ 376315150 892498299
http://www.xiaoyu163.com
http://www.xiaoyu163.com

14
14
ADV-M71
DescriptionPin No. Pin Name Type
27 XSSBAD I/A Sub-beam addition signal input
166 XSPDIREF I/A Phase detector reference current generator. Connect a resistor between this pin and
ground to set reference current
167 XSFDIREF I/A Frequency detector reference current generator. Connect a resistor between this pin and
ground to set reference current
169 XSPLLFTR2 I/A Data PLL loop filter pin#2
171 XSFDO O/A Output node of frequency detector charge pump circuit
172 XSFTROPI I/A Input node of loop filter OP circuit
173 XSVR_PLL I/A PLL reference voltage input
174 XSPDOFTR2 I/A Phase detector filter pin#1
175 XSVREFO O/A Reference voltage output
176 XSAWRCVCO I/A Auto Wide Range Control of VCO input pin. For enlarge VCO range in CAV mode
29 XSDFCT I Detect detection signal input
30 XSCSJ O Chip select signal for accessing control registers
31 XSCLK O Clock output for accessing control registers
32 XSDATA I/O Registers data input/output pin
33 XSLDC O Laser diode on/off control output for both CD/DVD
34 XSFGIN I Motor Hall sensor input
35 XSSPDON O Spindle motor on output
36, 37, 38, 39 XSFLAG[3:0] O These pins are used to monitor some status of servo control block
48, 51, 52 XGPIO[2:0] I/O 1. These pins are used as general purpose I/O bus
2. When use internal microcontroller, XGPIO[2] can be used as programmable I/O port 3.6.
40 XMP1_7 I/O Internal microcontroller programmable I/O port 1.7.
41 XMP1_6 I/O Internal microcontroller programmable I/O port 1.6.
43 XMP1_5 I/O This pin is now changed to be NC.
44 XMP1_4 I/O Internal microcontroller programmable I/O port 1.4.
45 XMP1_3 I/O Internal microcontroller programmable I/O port 1.3.
47 XMP1_2 I/O Internal microcontroller programmable I/O port 1.2.
49 XMP1_1 I/O Internal microcontroller programmable I/O port 1.1.
57 XMP1_0 I/O Internal microcontroller programmable I/O port 1.0.
This pin is default used as the A16 (microcontroller address line 16)
46 XMFSCSJ I/O Output chip select connected to external flash ROM chip enable pin
54 XMPSENJ I/O Output program store enable connected to external ROM PSENJ pin.
56 XMALE I/O This signal is used as address latch signal in address/data mux mode
70 XMCSJ I/O 1. This signal must be asserted for all microcontroller accesses to the register of this chip
2. When use internal microcontroller, this signal can be used as programmable I/O port 3.1
71 XMRDJ I/O 1. This signal is used as the Read Strobe signal
2. When use internal microcontroller, this signal can be used as programmable I/O port 3.0
72 XMWRJ I/O This signal is used as the Wire Strobe signal
73 XMINT1J I/O 1. This signal is an interrupt line to the microcontroller
2. When use internal microcontroller, this signal can be used as programmable I/O port 3.7
74, 75, 77, 78,
XMA[15:0] I/O These pins are used as address bus
79, 80, 81, 82,
83, 84, 85, 86,
87, 89, 90, 91
62, 63, 64, 65, XMD[7:0] I/O These pins are used as data bus for the 16-bit processor mode, or the address/data mux
66, 67, 68, 69 bus for the 8-bit processor mode.
163 XTPLCK I/O PLCK test pin
164 XTSLRF I/O SLRF test pin
59 XOSC1 I Crystal input/System clock. The input frequency from outside crystal or oscillator is 33.8688MHz
60 XOSC2 O Crystal output
53 XCRSTJ I Chip Reset. As asserted low input generates a component reset that stops all operations within
the chip and deasserts all output signals. All input/output signals are set to input.
94 XHCS1J I This pin is used to select the command block task file registers
93 XHCS3J I This pin is used to select the control block task file registers
103 XHIORJ I Asserted by the host during a host I/O read operation
104 XHIOWJ I Asserted by the host during a host I/O write operation
105 XHDRQ O
1.
DMA request. This pin is configured as the DMA request signal, and is used during DMA transfer
between the host and the controller. This pin is tri-stated when DMA transfers are not enabled.
2. MPEG acknowledge. This pin is used as the ACKJ signal when MPEG interface mode is selected.
101 XHDACKJ I
1. DMA acknowledge. This pin is configured as DACKJ, and is used as the DMA acknowledge
signal during DMA data transfers.
2. MPEG request. This pin is used as the REQ signal when MPEG interface mode is selected
99 XHCS16J O
1. 16-bit data select. This signal indicates that a 16-bit data transfer is active on the host data
bus. This pin is open-drain tri-state output.
2. MPEG clock. This pin is used as the CLOCK signal when MPEG interface mode is selected.
50 XHRSTJ I Host Reset. The reset of ATA bus
100 XHINT O
1. Host interface request. This tri-state pin is the host interrupt request, and is asserted to
indicate to the host that the controller needs attention.
2. MPEG begin. This pin is used as the BEGIN signal when MPEG interface mode is selected
w w w . x i a o y u 1 6 3 . c o m
Q Q
3
7
6 3
1 5 1 5
0 9 9
2
8 9
4 2
9 8
T E L 1 3 9 4 2 2 9 6 5 1 3 9 9 2 8 9 4 2 9 8 0 5 1 5 1 3 6 7 3
Q Q
TEL [phone] QQ 376315150 892498299 TEL [phone] QQ 376315150 892498299
http://www.xiaoyu163.com
http://www.xiaoyu163.com

15
15
ADV-M71
DescriptionPin No. Pin Name Type
97 XHPDIAGJ I/O This pin is used as the Passed Diagnostics signal, and may be an input or an open-drain output
92 XHDASPJ I/O This pin is used as the Drive Active/Slave Present signal, and is an input or an open-drain
output. This pin is used for Master/Slave drive communication and/or for driving an LED
102 XHIORDY I/O
1. I/O channel ready. This signal is driven low to extend host transfer cycles when the controller
is not ready to respond. This pin will be tri-stated when a read or write is not in progress.
2. MPEG error. This pin is used as the ERROR signal when MPEG interface mode is selected
95, 96, 98 XHA[2:0] I Host address lines. The host address lines A[2:0] are used to access the various host control,
status, and data registers
XHD[15.0] I/O
1. Host data bus. This bus is used to transfer data and status between the host and the controller.
106, 107, 108, 2.
MPEG data bus 7-8. The HD[7:0] are used as the DATA [7:0] when MPEG interface mode is selected.
109, 111, 112, 3. VCD I/F. Bit3-0 are used as VCD I/F signal when VCD function is enabled. The relationship of
113, 114, 116, bit3-0 and VCD I/F is as follow
117, 118, 119, HD0—CD-DATA
120, 121, 122, HD1—CD-LRCK
123 HD2—CD-BCK
HD3—CD-C2PO
143 XRSDCLK O This signal is the clock output for SDRAM
147 XROEJ O This signal is used as the memory output enable for external DRAM buffers. After RSTJ is
asserted, this signal will be low
142 XRWEJ O This signal is asserted low when a buffer memory write operation is active
144 XRRASJ O This signal is used as Row address output to external DRAM buffer. After RSTJ is asserted, this
signal will be high
145 XRCASJ O This signal is used as column address output to external DRAM. After RSTJ is asserted, this
signal will be high
1. RAM address lines. These are bits11-0 for addressing the buffer memory.
2. Hardware setting. The bits6-0 are used as hardware setting for some functions.
RA[9] : FLASH size is 64K/128K
1: FLASH size is 64K
0: FLASH size is 128K
RA[8] : External CPU is 8032/H8
1: 8032
0: H8
RA[7] : Microcontroller programmable I/O port 1 pin control
1: By internal microcontroller
148, 149, 151, 0: By registers to decide input/output
152, 153, 155, RA[6] : System test pin output
156, 157, 158, XRA[11:0] O 1: Normal operation
159, 160, 161 0: System test pin output
RA[5] : For testing purpose, don’t need to set
RA[4] : IDE master/slave
1: Slave
0: Master
RA[3] : For testing purpose, don’t need to set
RA[2] : For testing purpose, don’t need to set
RA[1-0] : MCU Mode selection
11: Normal Mode (internal uP, internal address latch)
10: Outside uP Mode (ICE Mode)
01: Test mode for internal uP testing
00: Internal uP mode with external address latch
124, 125, 126,
XRD[15:0] I/O These signals are the 8-bit parallel data lines to/from the buffer memory.
127, 128, 129,
131, 132, 134,
135, 136, 137,
138, 139, 140,
141
4 AVDD5_DS Analog Power +5V for Data Slicer part
14 AVDD5_DA Analog Power +5V for DAC part
26 AVDD5_AD Analog Power +5V for ADC part
168 AVDD5_PL Analog Power +5V for Data PLL part
7, 55, 58, 76,
VDD Power +3.3V for digital core logic and pad
115, 146,
150, 162
1 AVSS_DS Analog Ground for Data Slicer part
16 AVSS_DA Analog Ground for DAC part
22 AVSS_AD Analog Ground for ADC part
170 AVSS_PL Analog Ground for Data PLL part
28, 42, 61,
GND Digital Ground core logic and pad.
88, 110, 130,
138, 154, 165
w w w . x i a o y u 1 6 3 . c o m
Q Q
3
7
6 3
1 5 1 5
0 9 9
2
8 9
4 2
9 8
T E L 1 3 9 4 2 2 9 6 5 1 3 9 9 2 8 9 4 2 9 8 0 5 1 5 1 3 6 7 3
Q Q
TEL [phone] QQ 376315150 892498299 TEL [phone] QQ 376315150 892498299
http://www.xiaoyu163.com
http://www.xiaoyu163.com

16
16
ADV-M71
M30626FHPGP (MA: IC302)
M30626FHPGP PORT
Pin No. port function Port setting Port name Explanation
1P94 OE2PCS Chip select output to EEPROM
2P93 O 3811 DATA Serial data output to elec.VR
3P92 SO E2P DI Serial data output to EEPROM
4P91 SI E2P DO Serial data input from EEPROM
5P90 SO E2P CK Serial clock output to EEPROM
6 BYTE - Gnd
7 CNVSS - don't use
8P87 O 3811 CLK Serial clock output to elec.VR
9P86 OVMUTE Mute output to video driver
10 RESET RESET Reset input
11 XOUT XOUT Xtal output
12 VSS VSS Gnd
13 XIN XIN Xtal input
14 VCC VCC Vcc
15 NMI - don't use
16 INT2 INT PROTECT Protect signal input L:Protect detect
17 INT1 INT ESS CS Chip select input from ESS
18 INT0 INT DE RXD Serial data input from DENON BUS
19 TA4IN I50/60 Line pulse input(50/60Hz)
20 P80 O PROG/INTE Progressive/Interlace switching signal output
21 P77 IVRJOG-B VR encoder pulse-B input
22 P76 IVRJOG-A VR encoder pulse-A input
23 P75 IFNJOG-B Function encoder pulse-B input
24 P74 IFNJOG-A Function encoder pulse-A input
25 P73 OFLCS Chip select output to FLD driver
w w w . x i a o y u 1 6 3 . c o m
Q Q
3
7
6 3
1 5 1 5
0 9 9
2
8 9
4 2
9 8
T E L 1 3 9 4 2 2 9 6 5 1 3 9 9 2 8 9 4 2 9 8 0 5 1 5 1 3 6 7 3
Q Q
TEL [phone] QQ 376315150 892498299 TEL [phone] QQ 376315150 892498299
http://www.xiaoyu163.com
http://www.xiaoyu163.com

17
17
ADV-M71
Pin No. port function Port setting Port name Explanation
26 CLK2 SO DE CK Serial clock output to DENON BUS
27 RXD2 SI DE RXD Serial data input from DENON BUS
28 TXD2 SO DE TXD Serial data output to DENON BUS
29 TXD1 SO FLDA Serial data output to FLD driver
30 P66 O DSPCOREPOW DSP(Mel100) core power ON/OFF switching H:P-ON
31 CLK1 SO FLCK Serial clock output to FLD driver
32 P64 OFLRST RESET output to FLD driver
33 TXD0 SO ESS DO Serial data output to ESS
34 RXD0 SI ESS DI Serial data input from ESS
35 CLK0 SI ESS CK Serial clock input from ESS
36 P60 I ESS ON ESS"Active" signal input H:Active
37 P57 ODVDRST Forced reset output to DVD drive
38 P56 I HP SW H/P insert detect signal input H:insert
39 P55 O - don't use
40 P54 ＯREQ1 Control signal input from DSP(Mel100)
41 P53 O DVD ON/OFF DVD drive power supply ON/OFF switching H:P-ON
42 P52 O RGB H Conposite/S/RGB switching
43 P51 O VCONT1 Aspect ratio switching-1
44 P50 O - don't use
45 P47 O VCONT2 Aspect ratio switching-2
46 P46 OCODECRST Reset output to CODEC(AD1837)
47 P45 O SEL CLK DSP clock switching
48 P44 O BSE DSP mute output
49 P43 OERRMUTE Mute output at DSP error
50 P42 ODIRCE Chip select output to DIR(LC89057)
51 P41 ODIRRST Reset output to DIR(LC89057)
52 P40 OCLATCH Latch output to DIR(LC89057)
53 P37 OP.ON/OFF Main power ON/OFF switching H:ON
54 P36 OSCARTMUTE Mute output to SCART audio output H:mute-on
55 P35 OSUBON Standby power ON/OFF switching H:OFF
56 P34 O FR-RELAY Front SP relay ON/OFF switching H:ON
57 P33 O EXP OE for port expand
58 P32 O EXP STB for port expand
59 P31 O EXP DA for port expand
60 VCC VCC Vcc
61 P30 O EXP CLK for port expand
62 VSS VSS Gnd
63 P27 I TEMP FAN Temp detect input for fan L: fan-on
64 P26 ISTEREO "STEREO"indicator input from tuner
65 P25 ITUNED Tuned detect input from tuner
66 P24 OTMUTE Mute output to tuner audio signal L:mute-on
67 P23 OTUCE Chip enable output to tuner
68 P22 OTUDI Serial data output to tuner
69 P21 OTUCK Serial clock output to tuner
70 P20 ITUDO Serial data input from tuner
71 INT5 IDFRES Ext reset signal from ESS
72 INT4 I DIR INT1 Interrupt request from DIR
73 INT3 IREMOTE Remote controler signal input
74 P14 O SYR Reset output to RDS IC
75 P13 O DSP1-RST Reset output to DSP
76 P12 OROMRST1 Reset output to DSP ROM
77 P11 O DSPOSCON OSC(for DSP) ON/OFF switching
78 P10 O DSPIOPOWER DSP(Mel100) I/O power ON/OFF switching H:P-ON
79 P07 IO IO8 I/O interface port to DSP
80 P06 IO IO7 I/O interface port to DSP
81 P05 IO IO6 I/O interface port to DSP
82 P04 IO IO5 I/O interface port to DSP
83 P03 IO IO4 I/O interface port to DSP
84 P02 IO IO3 I/O interface port to DSP
85 P01 IO IO2 I/O interface port to DSP
w w w . x i a o y u 1 6 3 . c o m
Q Q
3
7
6 3
1 5 1 5
0 9 9
2
8 9
4 2
9 8
T E L 1 3 9 4 2 2 9 6 5 1 3 9 9 2 8 9 4 2 9 8 0 5 1 5 1 3 6 7 3
Q Q
TEL [phone] QQ 376315150 892498299 TEL [phone] QQ 376315150 892498299
http://www.xiaoyu163.com
http://www.xiaoyu163.com

18
18
ADV-M71
Pin No. port function Port setting Port name Explanation
86 P00 IO IO1 I/O interface port to DSP
87 P107 OR/W Write/Read switching output to ROM for DSP
88 P106 IACK1 Control signal input from DSP(Mel100)
89 P105 I BUSY1 Control signal input from DSP(Mel100)
90 P104 IFLAG3A Control signal input from DSP(Mel100)
91 AN3 AD MODE2 Mode select-2
92 AN2 AD MODE1 Mode select-1
93 AN1 AD KEY-0 KEY A/D input-0
94 AVSS AVSS Gnd
95 AN0 AD KEY-1 KEY A/D input-1
96 VREF VREF Ref voltage of A/D port
97 AVCC AVCC Avcc
98 P96 SI DIR DOUT Serial data input from DIR
99 P97 SO DIR/CODEC DIN Serial data output to DIR/CODEC
100 P95 SO DIR/CODEC CLK Serial clock output to DIR/CODEC
I:Input
O:Output
SI:Serial Input
SO:Serial Output
INT:Interrupt Input
w w w . x i a o y u 1 6 3 . c o m
Q Q
3
7
6 3
1 5 1 5
0 9 9
2
8 9
4 2
9 8
T E L 1 3 9 4 2 2 9 6 5 1 3 9 9 2 8 9 4 2 9 8 0 5 1 5 1 3 6 7 3
Q Q
TEL [phone] QQ 376315150 892498299 TEL [phone] QQ 376315150 892498299
http://www.xiaoyu163.com
http://www.xiaoyu163.com

19
19
ADV-M71
BD3811K1 (MA: IC504)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
25 26
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
27 28 29 30 31 32 33 34 35 36 37 38 39 40
47k
47k
47k
47k
47k
47k
47k
47k
47k
47k
47k
47k
47k
47k
47k 47k
47k
47k
47k 47k 47k
47k
47k 47k
47k 47k
47k 47k
REC
INSW
REC
SW1
Input mute SW
5.1ch Mode SW2 DVD
5.1ch Mode SW1
LINE
R/L
MIX
LINE
R/L
MIX
5.1ch Mode SW2 DSP
RECSW
23
1
3
2
1
3
2
VCC
VEE
BASS
BOOST
LOGIC
TNF2
TNF1
BNF11
BNF21
BNF12
BNF22
BBNF2
OUT2
BBNF1
OUT1
AGND8
AGND7
VCC
AGND6
VEE
AGND5
MUTE
CL
DA
DGND
AGND4
GOUTSR
VINSR
AGND3
IN22 IN21 IN12 IN11 ROUT32 ROUT31 ROUT22 ROUT21 ROUT12 ROUT11 AGND10 GOUT2 VIN2 AGND9 GOUT1 VIN1
IN31
IN32
IN41
IN42
IN51
IN52
IN61
IN62
IN71
IN72
IN81
IN82
INDVDSR
INDVDSL
INDVDC
INDVDSW
OUT2(+)
OUT2(-)
OUT1(+)
OUT1(-)
IN1DSP
IN1MIX
IN2DSP
IN2MIX
INDSPSR
INDSPSL
INDSPC
INDSPSW
AGND1
GOUTSW
VINSW
AGND2
GOUTC
VINC
OUTSW
OUTC
OUTSL
OUTSR
VINSL
GOUTSL
RECSW
TREBLE
BASS
1 IN31 1ch input terminal 3
2 IN32 2ch input terminal 3
3 IN41 1ch input terminal 4
4 IN42 2ch input terminal 4
5 IN51 1ch input terminal 5
6 IN52 2ch input terminal 5
7 IN61 1ch input terminal 6
8 IN62 2ch input terminal 6
9 IN71 1ch input terminal 7
10 IN72 2ch input terminal 7
11 IN81 1ch input terminal 8
12 IN82 2ch input terminal 8
13 INDVDSR DVD surround Rch input terminal
14 INDVDSL DVD surround Lch input terminal
15 INDVDC DVD center speaker input terminal
16 INDVDSW DVD sub woofer input terminal
17 OUT2(+) 2ch (+) A/D output terminal
18 OUT2(-) 2ch (-) A/D output terminal
19 OUT1(+) 1ch (+) A/D output terminal
20 OUT1(-) 1ch (-) A/D output terminal
Pin No. DescriptionPin Name
BD3811K1 Pin Description
()
w w w . x i a o y u 1 6 3 . c o m
Q Q
3
7
6 3
1 5 1 5
0 9 9
2
8 9
4 2
9 8
T E L 1 3 9 4 2 2 9 6 5 1 3 9 9 2 8 9 4 2 9 8 0 5 1 5 1 3 6 7 3
Q Q
TEL [phone] QQ 376315150 892498299 TEL [phone] QQ 376315150 892498299
http://www.xiaoyu163.com
http://www.xiaoyu163.com

20
20
ADV-M71
Pin No. DescriptionPin Name
21 IN1DSP 1ch DSP input terminal
22 IN1MIX 1ch DSP MIX input terminal
23 IN2DSP 2ch DSP input terminal
24 IN2MIX 2ch DSP MIX input terminal
25 INDSPSR DSP surround Rch input terminal
26 INDSPSL DSP surround Lch input terminal
27 INDSPC DVD center speaker input terminal
28 INDSPSW DSP sub woofer input terminal
29 AGND1 Analog ground terminal
30 GOUTSW Sub woofer input gain output terminal
31 VINSW Sub woofer volume input terminal
32 AGND2 Analog ground terminal
33 GOUTC Center speaker input gain output terminal
34 VINC Center speaker volume input terminal
35 OUTSW Sub woofer output terminal
36 OUTC Center speaker output terminal
37 OUTSL Surround Lch output terminal
38 OUTSR Surround Rch output terminal
39 VINSL Surround Lch volume inut terminal
40 GOUTSL Surround Lch input gain output terminal
41 AGND3 Analog ground terminal
42 VINSR Surround Rch volume input terminal
43 GOUTSR Surround Rch input gain output terminal
44 AGND4 Analog ground terminal
45 DGND Ground terminal for comparator.
46 DA Serial data and latch input terminal
47 CL Serial clock input terminal
48 MUTE Mute terminal
49 AGND5 Analog ground terminal
50 VEE (-) Power supply terminal
51 AGND6 Analog ground terminal
52 VCC (+) Powr supply terminal
53 AGND7 Analog ground terminal
54 AGND8 Analog ground terminal
55 OUT1 1ch output terminal
56 BBNF1 1ch bass boost filter terminal
57 OUT2 2ch output terminal
58 BBNF2 2ch bass boost filter terminal
59 BNF22 2ch bass filter terminal 2
60 BNF12 2ch bass filter terminal 1
61 BNF21 1ch bass filter terminal 2
62 BNF11 1ch bass filter terminal 1
63 TNF1 1ch treble filter terminal
64 TNF2 2ch treble filter terminal
65 VIN1 1ch (Lch) volume input terminal
66 GOUT1 1ch (Lch) input gain output terminal
67 AGND9 Analog ground terminal
68 VIN2 2ch (Rch) volume input terminal
69 GOUT2 2ch (Rch) input gain output terminal
70 AGND10 Analog ground terminal
71 ROUT11 1ch REC input and output terminal 1
72 ROUT12 2ch REC input and output terminal 1
73 ROUT21 1ch REC output terminal 2
74 ROUT22 2ch REC output terminal 2
75 ROUT31 1ch REC output terminal 3
76 ROUT32 2ch REC output terminal 3
77 IN11 1ch input terminal 1
78 IN12 2ch input terminal 1
79 IN21 1ch input terminal 2
80 IN22 2ch input terminal 2
w w w . x i a o y u 1 6 3 . c o m
Q Q
3
7
6 3
1 5 1 5
0 9 9
2
8 9
4 2
9 8
T E L 1 3 9 4 2 2 9 6 5 1 3 9 9 2 8 9 4 2 9 8 0 5 1 5 1 3 6 7 3
Q Q
TEL [phone] QQ 376315150 892498299 TEL [phone] QQ 376315150 892498299
http://www.xiaoyu163.com
http://www.xiaoyu163.com