Digital Equipment 21143 User manual

Digital Equipment Corporation
Maynard, Massachusetts
http://www.digital.com/semiconductor
Digital Semiconductor 21143
PCI/CardBus 10/100-Mb/s Ethernet
LAN Controller
Hardware Reference Manual
Order Number: EC–QWC4D–TE
Revision/Update Information: This manual supersedes the Digital Semiconductor
21143 PCI/CardBus 10/100-Mb/s Ethernet LAN
Controller Hardware Reference Manual
(EC–QWC4C–TE).

May 1997
While DIGITAL believes the information included in this publication is correct as of the date of publication, it is
subject to change without notice.
Digital Equipment Corporation makes no representations that the use of its products in the manner described in this
publication will not infringe on existing or future patent rights, nor do the descriptions contained in this publication
imply the granting of licenses to make, use, or sell equipment or software in accordance with the description.
©Digital Equipment Corporation 1997. All rights reserved.
Printed in U.S.A.
DIGITAL, Digital Semiconductor, SecureON, and the DIGITAL logo are trademarks of Digital Equipment
Corporation.
CardBus is a trademark of Personal Computer Memory Card International Association.
IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.
Magic Packet is a trademark of Advanced Micro Devices, Inc.
MicroWire is a registered trademark of BankAmerica Corporation.
All other trademarks and registered trademarks are the property of their respective owners.

iii
Contents
Preface
1 Introduction
1.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
1.3 Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3
2 Signal Descriptions
2.1 21143 Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
2.2 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3
3 Registers
3.1 Configuration Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
3.1.1 Configuration Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
3.1.2 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3
3.1.2.1 Configuration ID Register (CFID–Offset 00H) . . . . . . . . . . . . . . . . . . . . 3–3
3.1.2.2 Command and Status Configuration Register (CFCS–Offset 04H) . . . . 3–4
3.1.2.3 Configuration Revision Register (CFRV–Offset 08H). . . . . . . . . . . . . . . 3–7
3.1.2.4 Configuration Latency Timer Register (CFLT–Offset 0CH) . . . . . . . . . . 3–8
3.1.2.5 Configuration Base I/O Address Register (CBIO–Offset 10H) . . . . . . . . 3–9
3.1.2.6 Configuration Base Memory Address Register (CBMA–Offset 14H) . . . 3–10
3.1.2.7 Configuration Card Information Structure Register (CCIS–Offset 28H). 3–11
3.1.2.8 Subsystem ID Register (CSID–Offset 2CH). . . . . . . . . . . . . . . . . . . . . . 3–12
3.1.2.9 Expansion ROM Base Address Register (CBER–Offset 30H). . . . . . . . 3–13
3.1.2.10 Configuration Interrupt Register (CFIT–Offset 3CH) . . . . . . . . . . . . . . . 3–14
3.1.2.11 Configuration Device and Driver Area Register (CFDD–Offset 40H). . . 3–15
3.2 CSR Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–17
3.2.1 Control and Status Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–17

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3.2.2 Host CSRs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–18
3.2.2.1 Bus Mode Register (CSR0–Offset 00H). . . . . . . . . . . . . . . . . . . . . . . . . 3–18
3.2.2.2 Transmit Poll Demand Register (CSR1–Offset 08H) . . . . . . . . . . . . . . . 3–22
3.2.2.3 Receive Poll Demand Register (CSR2–Offset 10H). . . . . . . . . . . . . . . . 3–23
3.2.2.4 Descriptor List Base Address Registers (CSR3–Offset 18H and
CSR4–Offset 20H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–23
3.2.2.5 Status Register (CSR5–Offset 28H). . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–25
3.2.2.6 Operation Mode Register (CSR6–Offset 30H). . . . . . . . . . . . . . . . . . . . 3–33
3.2.2.7 Interrupt Enable Register (CSR7–Offset 38H) . . . . . . . . . . . . . . . . . . . . 3–41
3.2.2.8 Missed Frames and Overflow Counter Register (CSR8–Offset 40H). . . 3–45
3.2.2.9 Boot ROM, Serial ROM, and MII Management Register
(CSR9–Offset 48H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–46
3.2.2.10 Boot ROM Programming Address Register (CSR10–Offset 50H) . . . . . 3–49
3.2.2.11 General-Purpose Timer Register (CSR11–Offset 58H). . . . . . . . . . . . . 3–50
3.2.2.12 SIA Status Register (CSR12–Offset 60H) . . . . . . . . . . . . . . . . . . . . . . . 3–51
3.2.2.13 SIA Connectivity Register (CSR13–Offset 68H). . . . . . . . . . . . . . . . . . . 3–54
3.2.2.14 SIA Transmit and Receive Register (CSR14–Offset 70H) . . . . . . . . . . . 3–55
3.2.2.15 SIA and General-Purpose Port Register (CSR15–Offset 78H) . . . . . . . 3–60
3.2.2.16 SIA and MII Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–64
4 Host Communication
4.1 Data Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
4.2 Descriptor Lists and Data Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
4.2.1 Receive Descriptors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3
4.2.1.1 Receive Descriptor 0 (RDES0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4
4.2.1.2 Receive Descriptor 1 (RDES1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–8
4.2.1.3 Receive Descriptor 2 (RDES2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9
4.2.1.4 Receive Descriptor 3 (RDES3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9
4.2.1.5 Receive Descriptor Status Validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–10
4.2.2 Transmit Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–10
4.2.2.1 Transmit Descriptor 0 (TDES0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–11
4.2.2.2 Transmit Descriptor 1 (TDES1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–14
4.2.2.3 Transmit Descriptor 2 (TDES2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–17
4.2.2.4 Transmit Descriptor 3 (TDES3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–17
4.2.2.5 Transmit Descriptor Status Validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–18
4.2.3 Setup Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–18
4.2.3.1 First Setup Frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–19
4.2.3.2 Subsequent Setup Frames. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–19
4.2.3.3 Perfect Filtering Setup Frame Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–19
4.2.3.4 Imperfect Filtering Setup Frame Buffer . . . . . . . . . . . . . . . . . . . . . . . . . 4–22
4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–27
4.3.1 Reset Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–27
4.3.2 Power-Saving Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–28
4.3.2.1 Sleep Power-Saving Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–28

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4.3.2.2 Snooze Power-Saving Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–29
4.3.3 Arbitration Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–30
4.3.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–32
4.3.5 Startup Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–33
4.3.6 Receive Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–34
4.3.6.1 Descriptor Acquisition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–34
4.3.6.2 Frame Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–34
4.3.6.3 Receive Process Suspended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–35
4.3.6.4 Receive Process State Transitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–36
4.3.7 Transmit Process. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–37
4.3.7.1 Frame Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–37
4.3.7.2 Transmit Polling Suspended. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–38
4.3.7.3 Transmit Process State Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–39
5 Host Bus Operation
5.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1
5.2 Bus Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2
5.3 Bus Slave Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2
5.3.1 Slave Read Cycle (I/O or Memory Target). . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3
5.3.2 Slave Write Cycle (I/O or Memory Target). . . . . . . . . . . . . . . . . . . . . . . . . . . 5–4
5.3.3 Configuration Read and Write Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5
5.4 Bus Master Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–6
5.4.1 Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–7
5.4.2 Memory Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–8
5.4.3 Memory Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–9
5.5 Termination Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–10
5.5.1 Slave-Initiated Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–10
5.5.1.1 Disconnect Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–11
5.5.1.2 Retry Termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–12
5.5.2 Master-Initiated Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–13
5.5.2.1 21143-Initiated Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–13
5.5.2.2 Memory-Controller-Initiated Termination . . . . . . . . . . . . . . . . . . . . . . . . 5–15
5.6 Parity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–18
5.7 Parking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–19
6 Network Interface Operation
6.1 MII/SYM Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1
6.1.1 100BASE-T Terminology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1
6.1.2 Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2
6.1.2.1 Signal Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2
6.1.2.2 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4
6.2 10BASE-T and AUI Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5

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6.2.1 Receivers and Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–6
6.2.2 Manchester Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–6
6.2.3 Manchester Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–6
6.2.4 Oscillator Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–6
6.2.5 Smart Squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7
6.2.6 Autopolarity Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7
6.2.7 Network Port Autosensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8
6.2.8 10BASE-T Link Integrity Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–9
6.3 Media Access Control Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–9
6.3.1 MAC Frame Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–9
6.3.1.1 Ethernet and IEEE 802.3 Frames. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–10
6.3.1.2 Ethernet Frame Format Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–10
6.3.2 Ethernet Reception Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–12
6.3.3 Detailed Transmit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–13
6.3.3.1 Transmit Initiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–13
6.3.3.2 Frame Encapsulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14
6.3.3.3 Initial Deferral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14
6.3.3.4 Collision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–15
6.3.3.5 Terminating Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–15
6.3.3.6 Transmit Parameter Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–16
6.3.4 Detailed Receive Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–17
6.3.4.1 Receive Initiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–17
6.3.4.2 Preamble Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–17
6.3.4.2.1 MII/SYM, 10BASE-T, or AUI Mode Preambles . . . . . . . . . . . . . . . . 6–17
6.3.4.2.2 100BASE-TX or 100BASE-FX Mode Preambles . . . . . . . . . . . . . . 6–18
6.3.4.3 Address Matching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–18
6.3.4.4 Frame Decapsulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–19
6.3.4.5 Terminating Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–19
6.3.4.6 Frame Reception Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–20
6.4 Loopback Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–21
6.4.1 Internal Loopback Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–21
6.4.2 External Loopback Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–22
6.4.3 Driver Entering Loopback Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–22
6.4.4 Driver Restoring Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–23
6.5 Full-Duplex Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–24
6.6 Autonegotiation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–25
6.7 Capture Effect–A Value-Added Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–26
6.7.1 What Is Capture Effect?. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–26
6.7.2 Resolving Capture Effect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–28
6.7.3 Enhanced Resolution for Capture Effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–29
6.8 Jabber and Watchdog Timers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–29
7 External Ports
7.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–1

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7.2 Boot ROM and Serial ROM Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–1
7.3 Boot ROM Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–3
7.3.1 Byte Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–3
7.3.2 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–4
7.3.3 Dword Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–5
7.4 Serial ROM Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–6
7.4.1 Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–7
7.4.2 Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–10
7.5 External Register Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–13
7.6 General-Purpose Port and LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–14
8 Remotely Waking Up the LAN
8.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–1
8.2 Remote Wake-Up Controller Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–1
8.3 Remote Wake-Up-LAN Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–3
8.3.1 Remote Wake-Up-LAN Mode with Main System Power Off . . . . . . . . . . . . . 8–3
8.3.2 Remote Wake-Up-LAN Mode with Main System Power On . . . . . . . . . . . . . 8–4
8.4 Invalid Password Limiter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–5
8.5 Configuration Revision Register (CFRV–Offset 08H). . . . . . . . . . . . . . . . . . . . . . 8–5
8.6 SIA and General-Purpose Port Register (CSR15–Offset 78H). . . . . . . . . . . . . . . 8–7
8.7 PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–11
8.7.1 Configuration Wake-Up-LAN IEEE Address 0 Register
(CWUA0–Offset 44H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–12
8.7.2 Configuration Wake-Up-LAN IEEE Address 1 Register
(CWUA1–Offset 48H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–14
8.7.3 Configuration Wake-Up Command Register (CWUC–Offset 54H) . . . . . . . . 8–15
8.7.4 SecureON™ Password Register (SOP0–Offset 4CH). . . . . . . . . . . . . . . . . . 8–17
8.7.5 SecureON Password Register (SOP1–Offset 50H). . . . . . . . . . . . . . . . . . . . 8–18
8.8 Remote Wake-Up-LAN Data Block in the SROM . . . . . . . . . . . . . . . . . . . . . . . . . 8–20
8.8.1 Remote Wake-Up-LAN IEEE Address and Command (SROM) . . . . . . . . . . 8–21
8.9 21143 Magic Packet Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–24
A Joint Test Action Group—Test Logic
A.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–1
A.2 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–2
A.2.1 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–2
A.2.2 Bypass Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–3
A.2.3 Boundary-Scan Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–3
A.2.4 Test Access Port Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–4

viii
B DNA CSMA/CD Counters and Events Support
B.1 CSMA/CD Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–1
C Hash C Routine
C.1 Little Endian Architecture Hash C Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C–1
C.2 Big Endian Architecture Hash C Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C–1
D Port Selection Procedure
D.1 MII Port Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–1
D.2 SYM Port Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–2
D.3 10BASE-T Port Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–2
D.4 AUI Port Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–3
E General-Purpose Port and LED Programming
E.1 Input Port Selection with Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E–1
E.2 Input Port Selection Without Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E–1
E.3 Output Port Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E–2
E.4 LED/Control Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E–2
F Support, Products, and Documentation
Index

ix
Examples
4–1 Perfect Filtering Buffer........................................................................................... 4–21
4–2 Imperfect Filtering Buffer....................................................................................... 4–24
8–1 21143 Magic Packet Fields ................................................................................... 8–25

x
Figures
1–1 21143 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5
2–1 21143 Pinout Diagram (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
3–1 CFID Register Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3
3–2 CFCS Register Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4
3–3 CFRV Register Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–7
3–4 CFLT Configuration Latency Timer Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8
3–5 CBIO Register Bit Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9
3–6 CBMA Register Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10
3–7 CCIS Register Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–11
3–8 CSID Register Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–12
3–9 CBER Register Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–13
3–10 CFIT Register Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–14
3–11 CFDD Register Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–15
3–12 CSR0 Bus Mode Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–18
3–13 CSR1 Register Bit Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–22
3–14 CSR2 Register Bit Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–23
3–15 CSR3 Register Bit Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–24
3–16 CSR4 Register Bit Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–25
3–17 CSR5 Register Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–26
3–18 CSR6 Register Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–33
3–19 CSR7 Register Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–41
3–20 CSR8 Missed Frames and Overflow Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–45
3–21 CSR9 Register Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–47
3–22 CSR10 Register Bit Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–49
3–23 CSR11 Register Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–50
3–24 CSR12 Register Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–51
3–25 CSR13 Register Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–54
3–26 CSR14 Register Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–55
3–27 CSR15 Register Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–60
4–1 Descriptor Ring and Chain Structure Examples . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2
4–2 Receive Descriptor Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3
4–3 RDES0 Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4
4–4 RDES1 Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–8
4–5 RDES2 Bit Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9
4–6 RDES3 Bit Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9
4–7 Transmit Descriptor Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–11
4–8 TDES0 Bit Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–11
4–9 TDES1 Bit Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–14
4–10 TDES2 Bit Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–17
4–11 TDES3 Bit Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–17
4–12 Perfect Filtering Setup Frame Buffer Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–20
4–13 Imperfect Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–22
4–14 Imperfect Filtering Setup Frame Buffer Format. . . . . . . . . . . . . . . . . . . . . . . . . . . 4–23
5–1 Slave Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–4

xi
5–2 Slave Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5
5–3 Configuration Read Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–6
5–4 Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–7
5–5 Memory Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–9
5–6 Memory Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–10
5–7 21143-Initiated Disconnect Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–11
5–8 21143-Initiated Retry Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–12
5–9 Normal Completion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–14
5–10 Master Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–15
5–11 Target Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–16
5–12 Target Disconnect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–17
5–13 Target Retry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–18
5–14 Parity Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–19
6–1 Ethernet Frame Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–10
6–2 Preamble Recognition Sequence in 10BASE-T or AUI Mode. . . . . . . . . . . . . . . . 6–18
7–1 Boot ROM, Serial ROM, and External Register Connection. . . . . . . . . . . . . . . . . 7–2
7–2 Boot ROM Byte Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–4
7–3 Boot ROM Byte Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–5
7–4 Boot ROM Dword Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–6
7–5 Read Cycle (Page 1 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–8
7–6 Read Cycle (Page 2 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–9
7–7 Read Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–10
7–8 Write Cycle (Page 1 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–11
7–9 Write Cycle (Page 2 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–12
7–10 Write Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–13
8–1 21143 Remote Wake-Up Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 8–2
8–2 CFRV Register Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–6
8–3 CSR15 Register Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–7
8–4 CWUA0 Register Bit Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–13
8–5 CWUA1 Register Bit Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–14
8–6 CWUC Register Bit Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–15
8–7 SOP0 Register Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–17
8–8 SOP1 Register Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–19

xii
Tables
2–1 Functional Description of 21143 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
3–1 Configuration Registers Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
3–2 CFID Register Bit Fields Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3
3–3 CFID Register Access Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3
3–4 CFCS Register Bit Fields Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5
3–5 CFCS Register Access Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6
3–6 CFRV Register Bit Fields Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–7
3–7 CFRV Register Access Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–7
3–8 CFLT Register Bit Fields Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8
3–9 CFLT Access Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8
3–10 CBIO Register Bit Fields Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9
3–11 CBIO Register Access Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9
3–12 CBMA Register Bit Fields Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10
3–13 CBMA Register Access Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10
3–14 CCIS Register Bit Fields Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–11
3–15 CCIS Register Access Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–12
3–16 CSID Register Bit Fields Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–12
3–17 CSID Register Access Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–13
3–18 CBER Register Bit Fields Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–13
3–19 CBER Register Access Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–14
3–20 CFIT Register Bit Fields Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–14
3–21 CFIT Register Access Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–15
3–22 CFDD Register Bit Fields Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–16
3–23 CFDD Register Access Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–16
3–24 CSR Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–17
3–25 CSR0 Register Bit Fields Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–18
3–26 Transmit Automatic Polling Intervals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–21
3–27 CSR0 Access Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–21
3–28 Cache Alignment Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–21
3–29 CSR1 Register Bit Field Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–22
3–30 CSR1 Register Access Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–22
3–31 CSR2 Register Bit Field Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–23
3–32 CSR2 Register Access Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–23
3–33 CSR3 Register Bit Fields Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–24
3–34 CSR3 Register Access Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–24
3–35 CSR4 Register Bit Fields Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–25
3–36 CSR4 Register Access Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–25
3–37 CSR5 Register Bit Fields Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–27
3–38 Fatal Bus Error Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–31
3–39 Transmit Process State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–31
3–40 Receive Process State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–32
3–41 CSR5 Register Access Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–32
3–42 CSR6 Register Bit Fields Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–34
3–43 Transmit Threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–38

xiii
3–44 Port and Data Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–38
3–45 Loopback Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–39
3–46 Filtering Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–39
3–47 CSR6 Register Access Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–40
3–48 CSR7 Register Bit Fields Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–42
3–49 CSR7 Register Access Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–45
3–50 CSR8 Register Bit Fields Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–46
3–51 CSR8 Register Access Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–46
3–52 CSR9 Register Bit Fields Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–47
3–53 CSR9 Register Access Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–49
3–54 CSR10 Register Bit Field Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–49
3–55 CSR10 Register Access Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–49
3–56 CSR11 Register Bit Fields Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–50
3–57 CSR11 Register Access Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–51
3–58 CSR12 Register Bit Fields Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–51
3–59 CSR12 Register Access Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–54
3–60 CSR13 Register Bit Fields Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–54
3–61 CSR13 Register Access Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–55
3–62 CSR14 Register Bit Fields Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–56
3–63 CSR14 Register Access Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–59
3–64 Twisted-Pair Compensation Behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–59
3–65 CSR15 Register Bit Fields Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–61
3–66 CSR15 Register Access Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–64
3–67 Programming MII/SYM Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–64
3–68 Programming 10BASE-T, AUI, and BNC Operating Modes . . . . . . . . . . . . . . . . . 3–65
4–1 RDES0 Bit Fields Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5
4–2 RDES1 Bit Fields Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–8
4–3 RDES2 Bit Field Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9
4–4 RDES3 Bit Field Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9
4–5 Receive Descriptor Status Validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–10
4–6 TDES0 Bit Fields Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–12
4–7 TDES1 Bit Fields Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–14
4–8 Filtering Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–16
4–9 TDES2 Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–17
4–10 TDES3 Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–17
4–11 Transmit Descriptor Status Validity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–18
4–12 Arbitration Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–31
4–13 Receive Process State Transitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–36
4–14 Transmit Process State Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–39
5–1 Bus Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2
6–1 IEEE 802.3 and MII/SYM Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2
6–2 Crystal Oscillator Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7
6–3 Ethernet Frame Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–10
6–4 Frame Format Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–11
6–5 Ethernet Receive Address Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–12
6–6 Transmit Parameter Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–16
6–7 Destination Address Bit 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–18

xiv
6–8 Autonegotiation Modes Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–25
6–9 Capture-Effect Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–28
6–10 2–0 Backoff Algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–29
7–1 LED Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–14
8–1 CFRV Register Bit Fields Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–6
8–2 CFRV Register Access Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–6
8–3 CSR15 Register Bit Fields Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–8
8–4 CSR15 Register Access Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–11
8–5 Remote Wake-Up-LAN Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . 8–12
8–6 Remote Wake-Up-LAN Registers in the PCI Configuration Space. . . . . . . . . . . . 8–12
8–7 CWUA0 Register Bit Fields Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–13
8–8 CWUA0 Register Access Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–13
8–9 CWUA1 Register Bit Fields Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–14
8–10 CWUA1 Register Access Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–14
8–11 CWUC Register Bit Fields Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–15
8–12 CWUC Register Access Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–17
8–13 SOP0 Register Bit Fields Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–18
8–14 SOP0 Register Access Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–18
8–15 SOP1 Register Bit Fields Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–19
8–16 SOP1 Register Access Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–19
8–17 Data Block in the SROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–20
8–18 Remote Wake-Up-LAN Data Block in the SROM. . . . . . . . . . . . . . . . . . . . . . . . . 8–21
8–19 Magic Packet Format for the 21143 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–24
A–1 Instruction Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–2
B–1 CSMA/CD Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–1

xv
Preface
Purpose and Audience
The Digital Semiconductor 21143 PCI/CardBus 10/100-Mb/s Ethernet LAN
Controller Hardware Reference Manual describes the operation of the Digital
Semiconductor 21143 10/100-Mb/s Ethernet LAN Controller (also referred to
as the 21143). This manual is for designers who use the 21143.
Manual Organization
This manual contains eight chapters, six appendixes, and an index.
•Chapter 1, Introduction, includes a general description of the 21143. It also
provides an overview of the 21143 hardware components.
•Chapter 2, Signal Descriptions, provides the physical layout of the 21143 and
describes each of the input and output signals.
•Chapter 3, Registers, provides a complete bit description of the 21143 command
and status registers (CSRs) and the configuration registers.
•Chapter 4, Host Communication, describes how the 21143 communicates with
the host by using descriptor lists and data buffers. It also describes the transmit
and receive processes.
•Chapter 5, Host Bus Operation, provides a description of the read, write, and
termination cycles.
•Chapter 6, Network Interface Operation, describes the MII, 10BASE-T, and AUI
ports. It includes a complete description of media access control (MAC)
operations. It also provides detailed transmitting and receiving operation
information.
•Chapter 7, External Ports, describes the interface and operation of the
MicroWire serial ROM, the boot ROM, the general-purpose port, and the
network activity LEDs.

xvi
•Chapter 8, Remotely Waking Up the LAN, describes how to remotely power up
a sleeping workstation.1
•Appendix A, Joint Test Action Group—Test Logic, provides descriptions of
testing, observing, and modifying circuit activity during normal operation.
•Appendix B, DNA CSMA/CD Counters and Events Support, describes features
that support the driver in implementing and reporting the specified counters and
events.
•Appendix C, Hash C Routine, provides an example of a C routine that generates
a hash index for a given Ethernet address.
•Appendix D, Port Selection Procedure, provides information about selecting the
MII, 10BASE-T, AUI, and BNC ports.
•Appendix E, General-Purpose Port and LED Programming, contains information
about general-purpose port and LED programming.
•Appendix F, Support, Products, and Documentation, contains information about
technical support and ordering information.
Document Conventions
Some tables use the values 1, 0, and X. An X signifies a don’t care (1 or 0)
convention, which can be determined by the system designer.
In Chapters 3, 4, and 8, all shaded bits in the figures are reserved and should be
written by the driver as 0.
1This feature is not supported on the 21143–PA and the 21143–TA.

Introduction 1–1
1
Introduction
This chapter provides a general description of the Digital Semiconductor 21143
10/100-Mb/s PCI/CardBus Ethernet LAN Controller (21143), its features, and an
overview of the hardware.
1.1 General Description
The 21143 is an Ethernet LAN controller for both 100-Mb/s and 10-Mb/s data rates,
which provides a direct interface to the peripheral component interconnect (PCI)
localbus or the CardBus. The 21143 interfaces to the host processor by using onchip
command and status registers (CSRs) and a shared host memory area, set up mainly
during initialization. This minimizes processor involvement in the 21143 operation
during normal reception and transmission.
Large FIFOs allow the 21143 to efficiently operate in systems with longer latency
periods. Bus traffic is also minimized by filtering out received runt frames and by
automatically retransmitting collided frames without a repeated fetch from the host
memory. The 21143 provides an upgradable boot ROM interface.
The 21143 provides three network ports: a 10BASE-T 10-Mb/s port, an attachment
unit interface (AUI) 10-Mb/s port, and a media-independent/symbol interface
(MII/SYM) 10/100-Mb/s port. The 10BASE-T port provides a direct Ethernet
connection to the twisted-pair (TP) interface. The AUI port provides a direct
Ethernet connection to the AUI. The 10/100-Mb/s port supports two operational
modes:
•MII mode—A full implementation of the MII standard
•SYM mode—Symbol interface to an external 10/100-Mb/s front-end decoder
(ENDEC). In this mode the 21143 uses an onchip physical coding sublayer
(PCS) and a scrambler/descrambler circuit to enable a low-cost 100BASE-T
implementation.
The 21143 is capable of functioning in a full-duplex environment for the MII/SYM
and 10BASE-T ports.

1–2 Introduction
Features
1.2 Features
The 21143 has the following features:
•Contains onchip PCS and scrambler/descrambler for 100BASE-TX
•Contains onchip integrated AUI port and a 10BASE-T transceiver
•Supports autodetection between 10BASE-T, AUI, and MII/SYM ports
•Supports IEEE 802.3 autonegotiation algorithm of full-duplex and half-duplex
operation for 10 Mb/s and 100 Mb/s (NWAY)
•Contains large independent receive and transmit FIFOs
•Provides an upgradable boot ROM interface up to 256KB
•Supports PCI and CardBus interfaces
•Supports the advanced PCI read multiple, read line, and write and invalidate
commands
•Includes a powerful onchip direct memory access (DMA) with programmable
burst size, providing low CPU utilization
•Supports an unlimited PCI burst
•Supports early interrupt on transmit and receive
•Contains a variety of flexible address filtering modes
•Offers a unique, patented solution to Ethernet capture-effect problem
•SupportsPCI clock speed frequency from dc to 33 MHz; network operation with
PCI clock from 20 MHz to 33 MHz
•Supports automatic loading of subvendor ID and CardBus card information
structure (CIS) pointer from serial ROM to configuration registers
•Supports big or little endian byte ordering for buffers and descriptors
•Supports full-duplex operation on both MII/SYM and 10BASE-T ports
•Implements power management with two power-saving modes (sleep and
snooze)
– Powers up in sleep mode
– Requires less than 70 mA of supply current after power-up
•Provides internal and external loopback capability on all network ports

Introduction 1–3
Microarchitecture
•Provides MicroWire interface for serial ROM (1K and 4K EEPROM)
•Provides LED support for various network activity indications
•Supports interrupts from two general-purpose pins
•Implements test-access port (JTAG-compatible) with boundary-scan pins
•Implements low-power, 3.3-V CMOS technology
•Enables automatic detection and correction of 10BASE-T receive polarity
•Implements unique, patent-pending intelligent arbitration between DMA
channels to minimize underflow or overflow
•Supports three network ports: 10BASE-T (10 Mb/s), AUI (10 Mb/s), and
MII/SYM (10/100 Mb/s)
•Contains a 4-bit, general-purpose programmable register and corresponding I/O
pins
•Supports IEEE 802.3 and ANSI 8802-3 Ethernet standards
•Supports remote wake-up-LAN, which is a feature based upon Advanced Micro
Device’s Magic Packet technology that allows sleeping workstations to be
remotely powered-up.1
•Supports SecureON,™ which is a security feature that can be added to the
Advanced Micro Device’s Magic Packet technology.1
1.3 Microarchitecture
The following list describes the 21143 hardware components, and Figure 1–1 shows
a block diagram of the 21143:
•PCI/CardBus interface—Includes all interface functions to the PCI or CardBus
bus, handles all interconnect control signals, and executes DMA and I/O
transactions
•Boot ROM port—Provides an interface to perform read and write operations to
the boot ROM, supports accesses to bytes or longwords (32-bit), and provides
the ability to connect an external 8-bit register to the boot ROM port
1This feature is not supported on the 21143–PA and the 21143–TA.

1–4 Introduction
Microarchitecture
•Serial ROM port—Provides a direct interface to a MicroWire ROM for storage
of the Ethernet address and system parameters
•General-purpose register—Enables software use for input or output functions
and LEDs
•DMA—Contains independent receive and transmit controller and handles data
transfers between CPU memory and onchip memory
•FIFOs—Contains independent FIFOs for receive and transmit and supports
automatic packet deletion on receive (runt packets or after a collision) and
packet retransmission after a collision on transmit
•RxM—Handles all CSMA/CD1receive operations and transfers the data from
the ENDEC to the receive FIFO
•TxM—Handles all CSMA/CD MAC2transmit operations, and transfers data
from transmit FIFO to the ENDEC for transmission
•SIA interface—Performs 10-Mb/s physical layer network operations and
implements the AUI and 10BASE-T functions, including the Manchester
encoder and decoder functions
•NWAY—Implements the IEEE 802.3 autonegotiation algorithm
•Physical coding sublayer—Implements the encoding and decoding sublayer of
the 100BASE-TX (CAT5) specification, including the squelch feature
•Scrambler/descrambler—Implements the twisted-pair physical layer medium
dependent (TP-PMD) scrambler/descrambler scheme for 100BASE-TX
•Three network interfaces—An AUI interface, a 10BASE-T interface, and an
MII/SYM interface provide a full MII signal interface and direct interface to the
100-Mb/s ENDEC for CAT5
1Carrier-sense multiple access with collision detection
2Media access control