Digital Equipment PDP-11 Series User manual

•
. .
.'
d.r· i'taJ
- -.' . ~.
•
1972
edition
•
digital equipmentcorporation
•
I

CONTENTS
PART I
Chapter 1· Programming Peripherals...............................................................1
Chapter 2· Basic I/O Terminals........................................................................5
Chapter 3· Magnetic Tape Options...................................................................33
Chapter 4· Display Terminals........................................................................... 55
Chapter 5· Disk Storage Devices ......................................................................63
Chapter 6· Clocks............................................................................................. 91
Chapter 7· Bus Extension Options................................................................... 97
Chapter 8· Communications Options..............................................................109
Chapter 9· Data Aquisition and Control Options............................................153
PART II
Chapter 1- Unibus Theory and Operation.......................................................179
Chapter 2· Interface Circuits ........................................................................... 201
Chapter 3· Interface Exaniples........................................................................245
APPENDICES
Appendix A· Device Registers......................................................................... 281
Appendix B· UNIBUS Pin Assignments......................................................... 289

iv

INTRODUCTION
This Handbook is intended for users of any PDP-ll family system. It describes
standard
PDP-ll peripherals and options and provides detailed information on
interfacing to the PDp·ll UNIBUS.
This Handbook supplements information contained each of the PDP-ll family
p)'ocesso)' hantll2oak.s..
Part I describes each PDp·ll peripheral device and includes programming infor-
mation. Part II covers the operation of the PDP-ll UNIBUS and describes inter-
~a~\~% \~'l-.~\~'U'C'5.
v
I

vi

1
PERIPHERALS AND OPTIONS
vii

viii

PART I
Chapter 1· PROGRAMMING PERiPHERALS........:.................................................1
Chapter 2· BASIC INPUT /OUTPUT DEVICES .......................................................5
TELETYPE ...................................
.- ..............................................................6
HIGH SPEED READER/PUNCH, PCII ...................................................... 11
HIGH SPEED LINE PRINTER, LPll .......................................................... I8
CARD READERS, CMll, CR11..................................................................23
DECWRITER, LA30...................................................................................
28
Chapter 3 . MAGNETIC TAPE OPTIONS............................................................... 33
DECTAPE, TCl1/TU56 ............................................................................. 35
MAGTAPE, TM 11 /TU 10............................................................................ 44
Chapter 4· DISPLAY TERMINALS .......................................................................55
STORAGE DISPLAY, VT01A ......................................................................56
OSCILLOSCOPE, VR01A ...........................................................................56
POINT PLOT DISPLAY, VR14....................................................................57
ALPHANUMERIC TERMINAL, VT05..........................................................58
DECLINK TERMINAL, RTOI ...................................................................... 60
Chapter 5· DISK STORAGE DEVICES ..................................................................63
DECDISK MEMORY, RCII/RS64 ..............................................................63
DISK AND CONTROL, RFII/RSIl.. ..........................................................73
DECPACK DISK CARTRIDGE SYSTEM, RKll·C/RK02, RK03 ................... 81
Chapter 6· CLOCKS ............................................................................................ 91
PROGRAMMABLE REAL TIME CLOCK, KWII·P ....................................... 91
LINE TIME CLOCK, KW11-L...................................................................... 93
Chapter 7 - BUS EXTENSION OPTIONS...............................................................97
BUS.REPEATER, DB11 .............................................................................97
BUS SWITCHES, DT11-A, DT11-B...........................................................100
ix

Chapter 8 -COMMUNICATIONS OPTIONS .................................... "" ................109
ASYNCHRONOUS LINE INTERFACE, DCll ............................................109
AUTOMATIC CALLING UNIT INTERFACE, DNll ....................................116
SYNCHRONOUS INTERFACE, DPll .......................................................122
ASYNCHRONOUS 16·LlNE SINGLE SPEED
MULTIPLEXER, DMll ..........................................131
FULL DUPLEX 8-BIT ASYNCHRONOUS :
LINE INTERFACE, KLll.. ....................................151
ASYNCHRONOUS NULL MODEM, H312A...............................................152
Chapter 9 -DATA ACQUISTION AND CONTROL OPTIONS ................................153
LOW LEVEL ANALOG INPUT SUBSYSTEM, AFCll .................................153
ANALOG TO DIGITAL CONVERSION
SUBSYSTEM, ADOID
............................................158
DIGITAL TO ANALOG CONVERSION
SUBSYSTEM,AAIID
.............................................161
UNIVERSAL DIGITAL CONTROL
SUBSYSTEM,
UDCll.. ....................................163
x

1.1 PROGRAMMING
PART I
Chapter 1
Programming Peripherals
Programming of peripherals is extremely simple in the PDP-II -- a special class of
instructions to deal with
input/output operations is unnecessary. The UNIBUS
permits a unified addressing structure in which control, status, and data registers
for peripheral devices
are directly addressed as memory locations. Therefore all
operations on these registers, such as transferring information into or out of
them or manipulating data within them, are performed
by normal memory refer-
ence instructions.
The use of all memory reference instructions on peripheral device registers
greatly increases the flexibility of
input/output programming. For example, infor-
mation in a device register can be compared directly with a value and a branch
made on the result:
CMP PRB, # 101
BEQ SERVICE
In this case, the program looks for laIR in the paper tape 'reader data buffer
(PRB), and branches if it finds it. There is no need to transfer the information
into
an intermediate register for comparison.
When the character is of interest, amemory reference instruction can transfer the
character into a user buffer in core
or to another peripheral device. The instruc-
tion:
MOV PRB,LOC
transfers a character from the paper tape buffer into a user-defined "location.
All arithmetic operations can be performed on a peripheral device register. For ex-
ample, the instruction ADD # la, DSX will add la, to a display's x-deflection reg-
ister.
All peripheral device registers can be treated as accumulators. There is no need to
funnel all data transfers, arithmetic operations, and comparisions through a
single
or small number of accumulator registers.
1.2 DEVICE REGISTERS
All peripheral devices are specified by a set of registers which are addressed as
core memory and manipulated as flexibly as an accumulator. There are two types
of registers associated with
each device: 1) control and status registers: 2) data
registers.
1

1.2.1 Control and Status Registers
Each peripheral has one or more control and status registers that contain all the
information necessary to communicate with that device.
The general form, shown
below does not necessarily apply to every device, but is presented as a guide.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 a
~~~;::l-:C-T=I=:t_! _!_J_~_!---.J! I : (ll~f' ~I' I
DONE OR READY-------------'
INTERRUPT ENABLE
MEMORY EXTENSION
DEVICE FUNCTION
ENABLE--------------------------------'
Many devices require less than sixteen status bits. Other devices will require more
than sixteen bits and therefore will require additional status and control registers.
The bits in the control and status registers are generally assigned as follows:
BIT NAME
15·12 Errors
11 Busy
10-8 Unit Select
7 Done or Ready
DESCRIPTION
Generally there is an individual bit asso-
ciated with a specific error. When more
bits are requi
red for errors, they can be
obtained by expanding the error section in
the word or by using another status word.
Generally Bit 15
is the inclusive OR of all
other error bits (if there is more than one).
Most devices will
have "hard"error condi-
tions which will cause an interrupt if bit 6
is set. Some may also have "soft"errors
(warning types) which do not cause imme-
diate interrupts. All errors are generally in-
dicated by individual status bits.
Indicates that a step IS being performed.
Some peripheral systems have more than
one device per control. For example, a disk
system
can have multiple surfaces per
control and an analog-to-digital converter
can have multiple channels. The
unit bits
select the proper surface
or channel.
The register can contain a DONE bit, a
READY bit or a DONE-BUSY pair of bits,
depending
on the device. These bits are
set and cleared
by the hardware, but may
be queried by the program to determine
the availability
of the device. For example,
the teleprinter status register (TPS) has a
READY bit (7) that is cleared on request
for output and then set when output
is
2

6
5-4
3-1
o
Interrupt Enable
Memory Extension
Device Function Bits
Enable
complete. The keyboard status register
(TKS) has a DONE-BUSY pair (bits 7 and
11)
that distinguish between no input
(DONE = BUSY = 0), input under way
(DONE = 0, BUSY = 1), AND INPUT COM-
PLETE (DONE = 1, BUSY = 0).
The DONE bit could be used to control an
input loop for reading from the paper tape
reader
a's follows:
LOOP: TSTB PRS ;test low byte
;of paper tape
;status
;register
BPL LOOP ;branch back if
;DONE (bit 7)
;is
not set
Independently programmable. If
bit 6 is
set, an
interrupt will occur as a result of a
function done
or error condition. To in-
itiate an interrupt routine to read from the
paper tape reader, the instruction
MOV # 101,PRS
could be used. This sets bit 0 and bit 6 of
the paper tape reader control and status
register (PRS). Setting bit 0 starts the read
operation and setting bit 6 enables an in-
terrupt to occur when the read operation
is complete.
Will allow devices to use a full 18 bits to
specify addresses on the bus.
Specify operations that a device is to per-
form. For example, a paper tape read
function could
be "read one character".
An operation for a disk could be "read a
block of words from memory and store
them on
the disk."
When set, enables the device.
NOTE
The "unused"and "Ioad"only bits are always read as
zeroes. Loading "unused"or "read only" bits has no
effect
on the bit position. The mnemonic "INIT"refers
to the initialization signal issued by the processor.
Data Buffer Registers
Each device has at least one buffer register for temporarily storing data to be
transferred into or out of the computer. The number and type of data registers is
a function of the device. The paper tape reader and punch use single 8-bit data
buffer registers. A disk would use 16·bit data registers and some devices may
use
two 16-bit registers for data buffers.
3

1.2.2 Interrupt Structure
If the appropriate interruptenable bit is set, in the control and status register of a
device, transition from 0 to 1
of the READY or ERROR bit causes an interrupt
request to
be issued to the processor. Also if READY or ERROR is a 1when the in-
terrupt enable is turned on, an interrupt request is made. If the device makes the
request at a priority greater than that at which the processor
is running and no
other conflicts exist, the request
is granted and the interrupt sequence takes
place:
a. the current program counter (PC) and processor status CPS) are pushed onto
the processor stack;
b. the new PC and PS are loaded from a pair of locations (the interrupt vector) in
addressed memory, unique to the interrupting device.
Since
each device has a unique interrupt vector which dispatches control to the
appropriate interrupt handling routine immediately, no device polling is required.
Furthermore, since the
PS contains the processor priority, the priority at which an
interrupt request is serviced can be set under program control and is independent
of the priority
of the interrupt request. The Return from Interrupt Instruction
CRT!) is used to reverse the action of the interrupt sequence. The top two words
on the stack are popped into the PC and PS, returning control to the interrupted
sequence.
1.2.3 Programming Example
A paper tape reader interrupt service could appear as follows:
First the user must initialize the service routine by specifying an address pointer
and a word count
INIT: MOV # BUFADR,POINTER ;set address pointer
MOV #COUNT,COUNTR
MOV # 101,PRS
;set counter
;enable reader program continues until in-
terrupt
When the interrupt occurs and is acknowledged, the processor stores the current
PC and PS on the stack. Next it goes to the interrupt vector and picks up the new
PC and PS beginning at location 70. When the program was loaded the address of
PRSER would be put in location 70 and 200& in 72 (to set priority at 4). The next
instruction executed is the first instruction of the device service routine at
PRSER.
PRSER: TST PRS
BMIERROR
MOVB PRB,@POINTR
INC POINTR
DEC COUNTR
BEQ DONE
INC PRS
DONE: RT[
;test for error
;branen if bit 15 set
;move character to buffer
;increment pointer
;decrement character count
;branch when input dOne
;start reader for next character
;retum
to interrupt program
4

2.1 INTRODUCTION
PART I
Chapter 2
Basic I/O Terminals
This chapter describes the simplest and most common devices for entering data
to and receiving data
from a PDP-ll system: teleprinters, paper tape punches
and readers, line printers and card readers.
The ASR 33 Teletype (DEC model number LT33-DC) is provided as standard
equipment with some basic
PDP-ll Family systems. It will type or print informa-
tion at a rate of up to'lO characters per second and is equipped with low speed
paper punch and reader (10 cps). A Teletype with keyboard and printer but with-
out paper tape reader and punch (KSR) is also available. The LA30 DECwriter, a
teleprinter completely designed
by DEC, answers the need for a fast reliable, low-
cost terminal and is particularly appropriate for systems requiring large numbers
of highly reliable printerIterminals. It prints
at speeds of up to 30 characters per
second with low noise levels.
The PC11 High Speed Paper Tape Reader and Punch is available for users who
need faster paper tape reading speeds than those offered by the standard ASR 33
Teletype. The
PCll reads perforated tape at rates of up to 300 characters per
second and punches tape at
50 characters per second.
The LPll high speed line printer, one of the few line printers available with 80-
column width, will print a maximum of 356 full lines per minute (80-column, 64-
character model). A 132 column model is also available as are 96 character sets
giving upper and lower
case printing.
Any combinations of these
devices may be used with a PDP-ll. For example, the
RSTS-ll
BASIC-PLUS timesharing system can accommodate up to 16 teleprinter
terminals, in addition
to other 1/0 devices.
DEC devices utilize American National Standard Code for Information Inter-
change (ANSCII), 1968 version, code.
The eight-bit code used by the Model ASR Teletype is ASCII modified. To convert
ANSCII code to Teletype code, add 200 octal (ASCII +200. = Teletype). This code
is read in the normal octal form used in the computer. .
On paper tape, bits are numbered from right to left, from 0 through 7, with bits 0
through 2 containing the least significant octal number. H01es corresponding to
bits 2 and 3
are separated by a row of small feed holes for moving the tape.
2.2 TELETYPE
The standard ASR 33 Teletype can be used to type in or print out information, or
to
read in or punch out perforated paper tape. Printing, punching and reading are
5

ASR 33 TELETYPE
performed at rates of up to 10 characters per second. The KL11-A Teletype Con-
trol assembles or disassembles Teletype serial information for parallel transfer
to, or from, the UNIBUS.
2.2.1 Operation
When the processor addresses the bus, the Teletype Control decodes the address
to determine
if the Teletype is the selected device and, if selected, whether it is to
perform an input or output operation. Signals transferred between the Teletype
and the control logic are standard serial,
ll-unit code Teletype signals. They con-
sist of "marks" and "spaces" which correspond to bias and idle current in the
Teletype serial line, and
l's and O's in the control and computer. The 11-bit code
consists of a start bit, 8 data bits, and 2 halt bits.
2.2.2 Programming
The Teletype Control has four addressable registers. They have memory ad-
dresses and can be read or loaded using any PDP11 instruction that refers to
their address.
REGISTER
Reader Status Register (TKS)
Reader Buffer Register (TKB)
Punch Status Register (TPS)
Punch Buffer Register (TPB)
ADDRESS
777560
777562
777564
777566
The bit assignments for the registers are shown below. The "unused" and "load
only" bits are always read as zeros. Loading "unused" or "read only" bits has no
effect on the bit position. The mnemonic "'NIT" refers to the initialization signal
issued by on, power
up. console start, or RESET.
6

Reader Status Register
15 14 13 12 11 10 9 8 7 6 54321 0
rAt
~~~~------f-l,l I
INTERRUPT ENABLE-------------'
READER ENABLE ____________________ --1
BIT NAME
DESCRI PTION
15-12 Not Used
11 Busy Indicates
that the Teletype Control is re-
.ceiving a start bit or information bits.
Cleared by INIT, set by
start bit, cleared
after reception of first halt bit. Read only.
10-08
Not used
7 Done Character available
in buffer. Cleared by
IN IT, cleared by referencing data buffer,
causes
interrupt when INTR ENB =
1.
Read only. Cleared when RDR ENB is set.
6 Reader Interrupt Enable Interrupts Enable. Enables Error or Done
to cause an interrupt. Cleared by INIT.
5-1 Not used
0 Reader Enable Enables reader (not keyboard)
to read one
character. Cleared by INIT; cleared when
legitimate
start bit is detected. Load only.
Reader Buffer (TKB)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
.....
DATA-----------------~t
BIT
15-8
7-0
NAME
Data
DESCRI PTION
Not used
Holds character
read_ Cleared by start bit.
Read only.
Any reference to TKB (as word
or byte) or TKB +1 clears DONE.
7

P.unch Status Register (TPS)
15 14 13 12 11 10 9 8 7 6 5 4 3 2
READY -------------~ 1
INTERRUPT ENA8LE---------~--',
MAINTENANCE--------c---------------'
1 0
-
BIT NAME DESCRIPTION
15-8
7
6
5-3
2
1-0
Ready
Interrupt Enable
Maintenance
Not used
Punch available. Set by INIT, cleared when
buffer is loaded, set when punching com-
plete. Caused interrupt if INTR ENB = 1.
Read only.
Enables READY
to cause interrupt.
Cleared by INIT.
Not used
Maintenance function.'Disables serial line
input from Teletype unit and enables se-
rial output of punch to feed into reader
buffer. Cleared by INIT.
Not used
Punch Buffer Register (TPS)
15 14 13 12 11 10 9 8 7 6 5 A 3 2 0
-
''- _____ ---. ,-------'
DATA--------------------------~T
BIT
15-8
7-0
NAME
Data
DESCRIPTION
Not used
Holds character to
be punched. Cleared by
INIT. Load only.
Any instruction
that could modify TPB as a byte or word, clears READY and in-
itiates punching. Other reference to either byte or word have no effect on the
punch.
8

2.2.3 Programming Examples
Reading a Character (from reader or keyboard):
READ: INC TKS
LOOP: TSTB TKS
BPLLOOP
MOVB TKB,RO
;Set
RDR ENB
;Look
for DONE
;Wait if DONE = 0
;Read character
Programming Example: Punching a Character
PU NCH: TSTB TPS
BPL PUNCH
MaYS
RO,TPB
;Test for READY
;Wait if READY = 0
;Punch character
Programming Example: Echoing Keyboard
ECHO: TSTB TKS ;Character available?
BPL ECHO ;Wait if DON E = 0
LOOP:
TSTB TPS
;Is punch ready?
BPL LOOP
;Wait if READY = 0
MOVB TKB,TPB ;Punch character
BR ECHO ;Repeat for next character
Programming Example: Reading 10 Characters (by means of an interrupt)
START: MOV # 10,RD.
MOV #2000,Rl
MOV # 101,TKS
STALL:
BR STALL
60: RDRINT
62: 000200
;Set up counter
;Set up buffer pointer
;Set INTR ENS and RDR ENS
;Hang up here until
;block is read
;Start of reader service
;routine
;Raise processor to priority
;level4
. 9

RDRINT:
MOVS TKS,(Rl) + ;Put character into buffer
DEC RO
;Decrement counter
SEQ END
;If count = 0, get out
INC TKS ;Enable reader again
RTI
;Return from interrupt
END:
TST (SP) + ,(SP) + ;Reset stack
CLR TKS
JMP STALL +2
2.2.4 Specifications
Space Requirement:
Weight:
Interrupt Vector Address:
Priority Level:
Operatihg Temperature:
Humidity:
KL 11A Control:
;Clear INT
ENS
;Sack to program
Requires a floor space
of approximately 22 1/2
inches wide by 18 1/2 inches deep. The standard
Teletype cable length restricts its location
to within
8 feet of the side of the computer.
70lbs
Keyboard 1 printer: 60
Teleprinter Ipunch: 64
SR4 (Teletype keyboard has precedence over Tele·
type printer.
50 ·110 F
20% to 80%
Humidity: 20% to 90%
Temperature: 55 to 100 F.
The KUlA is capable of driving up to to 1,500 feet of cable if necessary.
10
,.