Enclustra Mercury KX1 User manual

Mercury KX1 FPGA Module
User Manual
Purpose
The purpose of this document is to present the characteristics of Mercury KX1 FPGA module to the user, and
to provide the user with a comprehensive guide to understanding and using the Mercury KX1 FPGA module.
Summary
This document first gives an overview of the Mercury KX1 FPGA module followed by a detailed description
of its features and configuration options. In addition, references to other useful documents are included.
Product Information Code Name
Product ME-KX1 Mercury KX1 FPGA Module
Document Information Reference Version Date
Reference / Version / Date D-0000-411-002 07 16.02.2021
Approval Information Name Position Date
Written by DIUN Design Engineer 10.06.2016
Verified by GLAC Design Expert 24.06.2016
Approved by DIUN Manager, BU SP 16.02.2021
Enclustra GmbH – Räffelstrasse 28 – CH-8045 Zürich – Switzerland
Phone [phone] – www.enclustra.com

Copyright Reminder
Copyright 2021 by Enclustra GmbH, Switzerland. All rights are reserved.
Unauthorized duplication of this document, in whole or in part, by any means is prohibited without the prior
written permission of Enclustra GmbH, Switzerland.
Although Enclustra GmbH believes that the information included in this publication is correct as of the date
of publication, Enclustra GmbH reserves the right to make changes at any time without notice.
All information in this document is strictly confidential and may only be published by Enclustra GmbH,
Switzerland.
All referenced trademarks are the property of their respective owners.
Document History
Version Date Author Comment
07 16.02.2021 DIUN Cleaned-up product variants, added Mercury+ ST1 to accesories sec-
tion, added information on FPGA fuses and warranty, on differential
I/Os, on voltage monitoring outputs, other style updates
06 25.07.2019 DIUN Added information on voltage monitoring, power supplies, heat sink,
updated DDR memory types and EEPROM map description, other
style updates
05 21.08.2018 DIUN Minor corrections and style updates
04 04.05.2017 DIUN Updated EEPROM map, block diagram and footprint information
03 27.12.2016 DIUN Added tool support information
02 02.08.2016 DIUN Version 02, added information on MGTs
01 05.07.2016 DIUN Version 01
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Table of Contents
1 Overview 5
1.1 General ................................................... 5
1.1.1 Introduction ................................................ 5
1.1.2 Warranty .................................................. 5
1.1.3 RoHS .................................................... 5
1.1.4 DisposalandWEEE ............................................ 5
1.1.5 Safety Recommendations and Warnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1.6 ElectrostaticDischarge .......................................... 6
1.1.7 Electromagnetic Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2 Features................................................... 6
1.3 Deliverables ................................................ 7
1.4 Accessories................................................. 7
1.4.1 ReferenceDesign ............................................. 7
1.4.2 Mercury+PE1BaseBoard ........................................ 7
1.4.3 Mercury+ST1BaseBoard ........................................ 8
1.5 XilinxToolSupport ............................................ 8
2 Module Description 9
2.1 BlockDiagram............................................... 9
2.2 Module Configuration and Product Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3 Article Numbers and Article Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4 TopandBottomViews .......................................... 13
2.4.1 TopView .................................................. 13
2.4.2 BottomView................................................ 13
2.5 Top and Bottom Assembly Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5.1 TopAssemblyDrawing .......................................... 14
2.5.2 BottomAssemblyDrawing........................................ 14
2.6 ModuleFootprint ............................................. 15
2.7 MechanicalData.............................................. 16
2.8 ModuleConnector ............................................ 16
2.9 UserI/O................................................... 17
2.9.1 Pinout.................................................... 17
2.9.2 DifferentialI/Os .............................................. 18
2.9.3 I/OBanks.................................................. 18
2.9.4 VREFUsage................................................. 19
2.9.5 VCC_IOUsage ............................................... 19
2.9.6 SignalTerminations ............................................ 21
2.9.7 AnalogInputs ............................................... 21
2.10 Multi-Gigabit Transceiver (MGT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.11 Power.................................................... 23
2.11.1 PowerGenerationOverview ....................................... 23
2.11.2 PowerEnable/PowerGood........................................ 23
2.11.3 VoltageSupplyInputs........................................... 24
2.11.4 VoltageSupplyOutputs ......................................... 24
2.11.5 PowerConsumption............................................ 25
2.11.6 HeatDissipation.............................................. 25
2.11.7 VoltageMonitoring ............................................ 25
2.12 ClockGeneration ............................................. 26
2.13 Reset .................................................... 26
2.14 LEDs..................................................... 27
2.15 DDR3SDRAM ............................................... 27
2.15.1 DDR3SDRAMType ............................................ 28
2.15.2 SignalDescription............................................. 28
2.15.3 Termination................................................. 28
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2.15.4 Parameters................................................. 28
2.15.5 DDR3LowVoltageOperation ...................................... 29
2.16 QSPIFlash ................................................. 29
2.16.1 QSPIFlashType .............................................. 29
2.16.2 SignalDescription............................................. 30
2.17 DualGigabitEthernet........................................... 31
2.17.1 EthernetPHYType............................................. 31
2.17.2 SignalDescription............................................. 31
2.17.3 ExternalConnectivity ........................................... 31
2.17.4 MDIOAddress............................................... 31
2.17.5 PHYConfiguration............................................. 31
2.18 CypressFX3USB3.0Controller ..................................... 32
2.18.1 CypressFX3Type ............................................. 32
2.18.2 CypressFX3Pinout ............................................ 32
2.18.3 FunctionalDescription .......................................... 32
2.19 Real-TimeClock(RTC)........................................... 33
2.19.1 RTCType .................................................. 33
2.20 SecureEEPROM .............................................. 34
2.20.1 EEPROMType ............................................... 34
3 Device Configuration 35
3.1 ConfigurationSignals........................................... 35
3.2 ConfigurationMode............................................ 36
3.3 Pull-UpDuringConfiguration ...................................... 36
3.4 JTAG..................................................... 38
3.4.1 JTAGonModuleConnector ....................................... 38
3.4.2 ExternalConnectivity ........................................... 38
3.4.3 FX3JTAGConnector............................................ 38
3.5 MasterSerialConfiguration ....................................... 38
3.5.1 SignalDescription............................................. 39
3.6 SlaveSerialConfiguration ........................................ 39
3.6.1 SignalDescription............................................. 39
3.7 QSPI Flash Programming via JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.8 QSPI Flash Programming from an External SPI Master . . . . . . . . . . . . . . . . . . . . . . . . 40
3.8.1 SignalDescription............................................. 41
3.9 Enclustra Module Configuration Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4 I2C Communication 42
4.1 Overview .................................................. 42
4.2 SignalDescription............................................. 42
4.3 I2CAddressMap ............................................. 42
4.4 SecureEEPROM .............................................. 43
4.4.1 MemoryMap ............................................... 43
5 Operating Conditions 46
5.1 AbsoluteMaximumRatings ....................................... 46
5.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6 Ordering and Support 47
6.1 Ordering .................................................. 47
6.2 Support................................................... 47
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1 Overview
1.1 General
1.1.1 Introduction
The Mercury KX1 FPGA module combines the Xilinx Kintex-7® All Programmable FPGA device with fast
DDR3 SDRAM, USB 3.0 controller and PHY, dual Gigabit Ethernet, multi-gigabit transceivers, high-speed
LVDS I/O, and is available in industrial temperature range, forming a complete and powerful embedded
processing system.
The use of the Mercury KX1 FPGA module, in contrast to building a custom FPGA hardware, significantly
simplifies system design and thus shortens time to market and decreases the development effort of your
product.
Together with Mercury base boards, the Mercury KX1 FPGA module allows the user to quickly build a system
prototype and start with application development.
1.1.2 Warranty
Please refer to the General Business Conditions, available on the Enclustra website [1].
Warning!
Please note that the warranty of an Enclustra module is voided if the FPGA fuses are blown. This
operation is done at own risk, as it is irreversible. Enclustra cannot test the module in case of a warranty
product return.
1.1.3 RoHS
The Mercury KX1 FPGA module is designed and produced according to the Restriction of Hazardous Sub-
stances (RoHS) Directive (2011/65/EC).
1.1.4 Disposal and WEEE
The Mercury KX1 FPGA module must be properly disposed of at the end of its life.
The Waste Electrical and Electronic Equipment (WEEE) Directive (2002/96/EC) is not applicable for the Mer-
cury KX1 FPGA module.
1.1.5 Safety Recommendations and Warnings
Mercury modules are not designed to be “ready for operation” for the end-user. These can only be used in
combination with suitable base boards. Proper configuration of the hardware before usage is required.
Ensure that the power supply is disconnected from the board before inserting or removing the Mercury KX1
FPGA module, connecting interfaces, or connecting jumpers.
Touching the capacitors of the DC-DC converters can lead to voltage peaks and permanent damage; over-
voltage on power or signal lines can also cause permanent damage to the module.
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Warning!
It is possible to mount the Mercury KX1 FPGA module the wrong way round on the base board - always
check that the mounting holes on the base board are aligned with the mounting holes of the Mercury
KX1 FPGA module.
The base board and module may be damaged if the module is mounted the wrong way round and
powered up.
Warning!
Certain older revisions of the Mercury KX1 FPGA module cannot be used in combination with Mercury+
base boards (with three module connectors), due to a mechanical collision caused by large capacitors
on the bottom side of the module.
Always check that the mounting holes on the Mercury+ PE1 base board are aligned with the mount-
ing holes of the Mercury KX1 FPGA module. If the module cannot be mounted correctly due to the
mechanical collision, please contact Enclustra support.
1.1.6 Electrostatic Discharge
Electronic boards are sensitive to electrostatic discharge (ESD). Please ensure that the product is handled
with care and only in an ESD-protected environment.
1.1.7 Electromagnetic Compatibility
The Mercury KX1 FPGA module is a Class A product (as defined in IEC 61000-3-2 standard) and is not
intended for use in domestic environments. The product may cause electromagnetic interference, for which
appropriate measures must be taken.
1.2 Features
•Xilinx Kintex-7 28 nm FPGA XC7K160T/XC7K325T, FFG676/FBG676 package
•178 user I/Os up to 3.3 V
•158 FPGA I/Os (single-ended, differential or analog)
•20 MGT signals (clock and data)
•FBG package devices: 4 MGTs @ 6.6 Gbit/sec and 2 reference input clock differential pairs
•FFG package devices: 4 MGTs @ 10.3125 Gbit/sec and 2 reference input clock differential pairs
•PCIe Gen2 ×4 (Xilinx integrated PCIe block)
•Up to 2 GB + 512 MB DDR3 SDRAM
•64 MB quad SPI flash
•Cypress EZ-USB FX3 USB 3.0 device controller
•Dual Gigabit Ethernet
•Real-time clock
•High-power 16 A core power supply
•5 to 15 V supply voltage
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1.3 Deliverables
•Mercury KX1 FPGA module
•Mercury KX1 FPGA module documentation, available via download:
•Mercury KX1 FPGA Module User Manual (this document)
•Mercury KX1 FPGA Module Reference Design [2]
•Mercury KX1 FPGA Module IO Net Length Excel Sheet [3]
•Mercury KX1 FPGA Module FPGA Pinout Excel Sheet [4]
•Mercury KX1 FPGA Module User Schematics (PDF) [5]
•Mercury KX1 FPGA Module Known Issues and Changes [6]
•Mercury KX1 FPGA Module Footprint (Altium, Eagle, Orcad and PADS) [7]
•Mercury KX1 FPGA Module 3D Model (PDF) [8]
•Mercury KX1 FPGA Module STEP 3D Model [9]
•Mercury Mars Module Pin Connection Guidelines [10]
•Mercury Master Pinout [11]
•Mercury Heatsink Application Note [15]
1.4 Accessories
1.4.1 Reference Design
The Mercury KX1 FPGA module reference design features an example configuration for the Kintex-7 FPGA
device, together with an example top level HDL file for the user logic.
A number of software applications are available for the reference design, that show how to initialize the
peripheral controllers and how to access the external devices. Pre-compiled binaries are included in the
archive, so that the user can easily check that the hardware is functional.
The reference design can be downloaded from Github: https://github.com/enclustra.
1.4.2 Mercury+ PE1 Base Board
•168-pin Hirose FX10 module connectors (PE1-200: 2 connectors; PE1-300/400: 3 connectors)
•System controller
•Power control
•System monitor (PE1-300/400)
•Current sense (PE1-300/400)
•Low-jitter clock generator (PE1-300/400)
•microSD card holder
•User EEPROM
•eMMC managed NAND flash (PE1-300/400)
•PCIe ×4 interface
•USB 3.0 device connector
•USB 2.0 host connector (PE1-200: 1 connector; PE1-300/400: 4 connectors)
•Micro USB 2.0 device (UART, SPI, I2C, JTAG) connector
•2×RJ45 Gigabit Ethernet connectors
•mPCIe/mSATA card holder (USB only) (PE1-300/400)
•SIM card holder (optional, PE1-300/400 only)
•SMA clock and data in/out (optional, PE1-300/400 only)
•1×FMC LPC connector (PE1-200)
•1×FMC HPC connector (PE1-300)
•2×FMC LPC connector (PE1-400)
•2×40-pin Anios pin header
•3×12-pin IO headers
•5 to 15 V DC supply voltage
•USB bus power (with restrictions)
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Please note that the available features depend on the equipped Mercury module type and on the selected
base board variant.
1.4.3 Mercury+ ST1 Base Board
•168-pin Hirose FX10 module connectors (3 connectors)
•2×MIPI D-PHY connectors: CSI and CSI/DSI (requires FPGA support)
•Mini DisplayPort connector (requires FPGA support)
•HDMI connector (requires FPGA support)
•SFP+ connector
•Low-jitter clock generator
•USB 3.0 device connector
•USB 3.0 host connector
•FTDI USB 2.0 device controller with micro USB device connector (UART, SPI, I2C, JTAG)
•2×RJ45 Gigabit Ethernet connectors
•1×FMC HPC connector (note: not all pins are available)
•2×40-pin Anios pin header
•3×12-pin IO headers
•microSD card holder
•5 to 15 V DC supply voltage
•Form factor: 100 ×120 mm
Please note that the available features depend on the equipped Mercury module type.
1.5 Xilinx Tool Support
The FPGA devices equipped on the Mercury KX1 FPGA module are supported by the Vivado HL WebPACK
Edition or by the Vivado HL Design Edition software, depending on the device’s density. Table 1 presents
the correspondence between devices and tools. Please contact Xilinx for further information.
Module Xilinx Tool Support Costs
ME-KX1-160 Vivado HL WebPACK Edition Free of charge
ME-KX1-325 Vivado HL Design Edition Paid license required
Table 1: Xilinx Tool Support
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2 Module Description
2.1 Block Diagram
Figure 1: Hardware Block Diagram
The main component of the Mercury KX1 FPGA module is the Xilinx Kintex-7 FPGA device. Most of its I/O
pins are connected to the Mercury module connectors, making 158 regular user I/Os available to the user.
Further, four multi-gigabit transceivers with support for PCIe Gen2 ×4 are available on the module connector.
The FPGA device can be configured with a bitstream residing in the on-board QSPI flash, via Cypress FX3
USB 3.0 controller fitted on the module, via an external microcontroller or via the JTAG interface connected
to Mercury module connector.
The memory subsystem is built from a 64 MB QSPI flash and up to 2 GB + 512 MB DDR3 SDRAM in the
standard configuration.
Further, the module is equipped with two Gigabit Ethernet PHYs, making it ideal for communication appli-
cations.
A Cypress FX3 USB 3.0 controller is fitted on the module to easily implement a communication link to a host
PC.
A real-time clock is available on the module and is connected to the global I2C bus.
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On-board clock generation is based on a 100 MHz crystal oscillator and on a 200 MHz LVDS oscillator.
The module’s internal supply voltages are generated from a single input supply of 5 - 15 V DC. Some of
these voltages are available on the Mercury module connectors to supply circuits on the base board.
Four LEDs are connected to the FPGA pins for status signaling. Another LED is connected to the Cypress
FX3 USB 3.0 controller user pin for the same purpose.
2.2 Module Configuration and Product Codes
Table 2 describes the available standard module configurations. Custom configurations are available; please
contact Enclustra for further information.
Product Code FPGA DDR3/DDR3L SDRAM USB 3.0 Temperature
Range
ME-KX1-160-1C-D10 XC7K160T-1FBG676C 1024 + 256 MB X0 to +70◦C
ME-KX1-325-2I-D11-P XC7K325T-2FFG676I 2048 + 512 MB X-40 to +85◦C
Table 2: Standard Module Configurations
The product code indicates the module type and main features. Figure 2 describes the fields within the
product code.
Figure 2: Product Code Fields
Please note that for the first revision modules or early access modules, the product code may not respect
entirely this naming convention. Please contact Enclustra for details on this aspect.
2.3 Article Numbers and Article Codes
Every module is uniquely labeled, showing the article number and serial number. An example is presented
in Figure 3.
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Figure 3: Module Label
The correspondence between article number and article code is shown in Table 3. The article code repre-
sents the product code, followed by the revision; the R suffix and number represent the revision number.
The revision changes and product known issues are described in the Mercury KX1 FPGA Module Known
Issues and Changes document [6].
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Article Number Article Code
EN100029 ME-KX1-160-1C-D10-R2
EN100004 ME-KX1-325-2I-D11-P-R2
EN100089 ME-KX1-325-1C-D10-R2
EN100590 ME-KX1-410-2I-D11-P-R2
EN100871 ME-KX1-410-2C-D11-P-R2
EN101015 ME-KX1-160-1C-D10-R3
EN101421 ME-KX1-160-1C-D10-R3
EN101017 ME-KX1-325-2I-D11-P-R3
EN101515 ME-KX1-325-2C-D10-P-R3
EN101018 ME-KX1-410-2I-D11-P-R3
EN101422 ME-KX1-325-1C-D10-R4
EN101016 ME-KX1-325-1C-D10-R4
EN101519 ME-KX1-160-1C-D10-R4.1
EN101520 ME-KX1-325-2I-D11-P-R4.1
EN101424 ME-KX1-410-2I-D11-P-R4.1
EN101816 ME-KX1-160-1C-D10-R5
EN101921 ME-KX1-325-2C-D10-P-R5
EN101818 ME-KX1-325-2I-D11-P-R5
EN101819 ME-KX1-410-2I-D11-P-R5
Table 3: Article Numbers and Article Codes
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2.4 Top and Bottom Views
2.4.1 Top View
Figure 4: Module Top View
2.4.2 Bottom View
Figure 5: Module Bottom View
Please note that depending on the hardware revision and configuration, the module may look slightly dif-
ferent than shown in this document.
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2.5 Top and Bottom Assembly Drawings
2.5.1 Top Assembly Drawing
Figure 6: Module Top Assembly Drawing
2.5.2 Bottom Assembly Drawing
Figure 7: Module Bottom Assembly Drawing
Please note that depending on the hardware revision and configuration, the module may look slightly dif-
ferent than shown in this document.
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2.6 Module Footprint
Figure 8 shows the dimensions of the module footprint on the base board.
Enclustra offers Mercury and Mercury+ modules of various geometries having widths of 56, 64, 65, 72 or 74
mm and having different topologies for the mounting holes. If different module types shall be fixed on the
base board by screws, additional mounting holes may be required to accommodate different modules. The
footprints of the module connectors for the base board design are available for different PCB design tools
(Altium, PADS, Eagle, Orcad) [7] and include the required information on the module sizes and holes.
The maximum component height on the base board under the module is dependent on the connector type.
Please refer to the Hirose FX10 series product website for detailed connector information [12].
The two connectors are called A (J700) and B (J701).
Figure 8: Module Footprint - Top View
Warning!
It is possible to mount the Mercury KX1 FPGA module the wrong way round on the base board - always
check that the mounting holes on the base board are aligned with the mounting holes of the Mercury
KX1 FPGA module.
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2.7 Mechanical Data
Table 4 describes the mechanical characteristics of the Mercury KX1 FPGA module. A 3D model (PDF) and a
STEP 3D model are available [8], [9].
Symbol Value
Size 72 ×54 mm
Component height top 4.0 mm
Component height bottom 1.45 mm
Weight 32 g
Table 4: Mechanical Data
2.8 Module Connector
Two Hirose FX10 168-pin 0.5 mm pitch headers with a total of 336 pins have to be integrated on the base
board. Up to four M3 screws may be used to mechanically fasten the module to the base board. Do not
use excessive force to tighten the screws, as this could damage the module.
The pinout of the module connector is found in the Mercury Master Pinout Excel Sheet [11]. The connector
is available in different packaging options and different stacking heights. Some examples are presented in
Table 5. Please refer to the connector datasheet for more information.
Reference Type Description
Mercury module connector FX10A-168S-SV Hirose FX10, 168-pin, 0.5 mm pitch
Base board connector FX10A-168P-SV(71) Hirose FX10, 168-pin, 0.5 mm pitch, 4 mm stacking
height
Base board connector FX10A-168P-SV1(71) Hirose FX10, 168-pin, 0.5 mm pitch, 5 mm stacking
height
Table 5: Module Connector Types
Figure 9 indicates the pin numbering for the Mercury module connectors from the top view of the base
board. The connector pins are numbered as follows:
•Connector A: from J700-1 to J700-168
•Connector B: from J701-1 to J701-168
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Figure 9: Pin Numbering for the Module Connector
Warning!
Do not use excessive force to latch a Mercury module into the Mercury connectors on the base board,
as this could damage the module and the base board; always make sure that the module is correctly
oriented before mounting it into the base board.
2.9 User I/O
2.9.1 Pinout
Information on the Mercury KX1 FPGA module pinout can be found in the Enclustra Mercury Master Pinout
[11], and in the additional document Enclustra Module Pin Connection Guidelines [10].
Warning!
Please note that the pin types on the schematics symbol of the module connector and in the Master
Pinout document are for reference only. On the Mercury KX1 FPGA module it may be possible that
the connected pins do not have the targeted functions (such as primary clocks, differential pins, MGT
signals, etc).
The naming convention for the user I/Os is:
IO_B<BANK>_L<PAIR>_<SPECIAL_FUNCTION>_<PACKAGE_PIN>_<POLARITY>
For example, IO_B15_L12_MRCC_AD5_E17_N is located on pin E17 of I/O bank 15, pair 12, it is an MRCC (Multi-
Region Clock Capable) pin and also an XADC auxiliary analog input capable pin, and it has negative polarity,
when used in a differential pair.
The multi-region clock capable pins are marked with “MRCC”, while the single region clock capable pins are
marked with “SRCC” in the signal name. For details on their function and usage, please refer to the Xilinx
documentation.
Table 6 includes information related to the total number of I/Os available in each I/O bank and possible
limitations.
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Signal Name Signals Pairs Differential Single-ended I/O Bank
IO_B12_<...> 48 24 In/Out In/Out 12
IO_B13<...> 18 9 In/Out In/Out 13
IO_B15<...> 44 22 In/Out In/Out 15
IO_B16<...> 48 24 In/Out In/Out 16
Total 158 79 - - -
Table 6: User I/Os
Please note that for the 7 Series FPGAs there are restrictions on the VCCO voltage when using LVDS I/Os;
refer to Xilinx AR# 43989 for details.
2.9.2 Differential I/Os
When using differential pairs, a differential impedance of 100 Ωmust be matched on the base board, and
the two nets of a differential pair must have the same length.
The information regarding the length of the signal lines from the FPGA device to the module connector is
available in Mercury KX1 FPGA Module IO Net Length Excel Sheet [3]. This enables the user to match the
total length of the differential pairs on the base board if required by the application.
Warning!
Please note that the trace length of various signals may change between revisions of the Mercury
KX1 FPGA module. Please use the information provided in the Mercury KX1 FPGA Module IO Net
Length Excel Sheet [3] to check which signals are affected. The differential signals will still be routed
differentially in subsequent product revisions.
2.9.3 I/O Banks
Table 7 describes the main attributes of the FPGA I/O banks, and indicates which peripherals are connected
to each I/O bank. All I/O pins within a particular I/O bank must use the same I/O (VCC_IO) and reference
(VREF) voltages.
Bank Connectivity VCC_IO VREF
MGT Bank 115 Not connected 1.2 V -
MGT Bank 116 Module connector 1.2 V -
Bank 0 Configuration (JTAG, QSPI) User selectable -
VCC_CFG_B13
Bank 12 Module connector User selectable IO_B12_L6_VREF_W21_N
VCC_IO_B12 IO_B12_L19_VREF_AE21_N
Bank 13 Module connector, I2C, User selectable -
Ethernet PHYs VCC_CFG_B13
Continued on next page...
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Bank Connectivity VCC_IO VREF
Bank 14 QSPI flash, FX3 USB 3.0 controller User selectable -
VCC_CFG_B13
Bank 15 Module connector, LEDs User selectable IO_B15_L6_VREF_D16_N
VCC_IO_B15 IO_B15_L19_A21_VREF_J20_N
Bank 16 Module connector User selectable IO_B16_L6_VREF_H11_N
VCC_IO_B16 IO_B16_L19_VREF_C13_N
Bank 32 DDR3B User selectable1 -
VCC_DDR3L
Bank 33 DDR3B User selectable1 0.5 ×VCC_DDR3L
VCC_DDR3L
Bank 34 DDR3A User selectable1 0.5 ×VCC_DDR3L
VCC_DDR3L
Table 7: I/O Banks
1
2.9.4 VREF Usage
I/O standards referenced using VREF can be used on the Mercury module connector. The reference voltage
has to be applied to all VREF pins of the respective I/O banks. If a bank is configured to use an I/O standard
that does not need a reference voltage, the VREF pins of this bank on the module connector are available
as user I/O pins.
The VREF pins are listed in the Mercury Master Pinout Excel Sheet [11].
Warning!
Use only VREF voltages compliant with the equipped FPGA device; any other voltages may damage
the equipped FPGA device, as well as other devices on the Mercury KX1 FPGA module.
Do not leave a VREF pin floating when the used I/O standard requires a reference voltage, as this may
damage the equipped FPGA device, as well as other devices on the Mercury KX1 FPGA module.
2.9.5 VCC_IO Usage
The VCC_IO voltages for the I/O banks located on the module connector are configurable by applying the
required voltage to the VCC_IO_B[x] or VCC_CFG_[x] pins. All VCC_IO_B[x] or VCC_CFG_[x] pins of the same
bank must be connected to the same voltage.
For compatibility with other Enclustra Mercury modules, it is recommended to use a single I/O voltage per
module connector.
1The DDR3 SDRAM supports voltages of 1.5 or 1.35 V. Please refer to Section 2.15 for details.
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Signal Name FPGA Pins Supported Voltages Connector A Pins Connector B Pins
VCC_IO_B12 VCCO_12 1.0 V - 3.3 V ±5% 38, 41 -
VCC_CFG_B13
VCCO_0
1.8 V2, 2.5 V - 3.3 V ±5% 74, 77 -
VCCO_13
VCCO_14
VCC_IO_B15 VCCO_15 1.0 V - 3.3 V ±5% - 140, 143
VCC_IO_B16 VCCO_16 1.0 V - 3.3 V ±5% - 64, 67, 88, 95
Table 8: VCC_IO Pins
Note that the CFGBVS_0 pin is set automatically to GND (if VCC_CFG_B13 is less than or equal to 1.8 V) or to
VCCO (if VCC_CFG_B13 is 2.5 V or 3.3 V).
Warning!
Use only VCC_IO voltages compliant with the equipped FPGA device; any other voltages may damage
the equipped FPGA device, as well as other devices on the Mercury KX1 FPGA module.
Do not leave a VCC_IO pin floating, as this may damage the equipped FPGA device, as well as other
devices on the Mercury KX1 FPGA module.
Warning!
Do not power the VCC_IO pins when PWR_GOOD and PWR_EN signals are not active. If the module
is not powered, you need to make sure that the VCC_IO voltages are disabled (for example, by using a
switch on the base board, which uses PWR_GOOD as enable signal). Figure 10 illustrates the VCC_IO
power requirements.
Figure 10: Power-Up Sequence - VCC_IO in Relation with PWR_GOOD and PWR_EN Signals
21.8 V support is only available for modules of revision 3 and newer.
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