Enclustra Mercury Plus XU9 User manual

Mercury+ XU9 SoC Module
User Manual
Purpose
The purpose of this document is to present the characteristics of Mercury+ XU9 SoC module to the user,
and to provide the user with a comprehensive guide to understanding and using the Mercury+ XU9 SoC
module.
Summary
This document first gives an overview of the Mercury+ XU9 SoC module followed by a detailed description
of its features and configuration options. In addition, references to other useful documents are included.
Product Information Code Name
Product ME-XU9 Mercury+ XU9 SoC Module
Document Information Reference Version Date
Reference / Version / Date D-0000-463-001 04 05.09.2022
Approval Information Name Position Date
Written by DIUN, MMOS Design Engineer 20.05.2019
Verified by MMOS, GKOE Design Expert 24.05.2019
Approved by SJOK Product Manager 05.09.2022
Enclustra GmbH – Räffelstrasse 28 – CH-8045 Zürich – Switzerland
Phone [phone] – www.enclustra.com

Copyright Reminder
Copyright 2022 by Enclustra GmbH, Switzerland. All rights are reserved.
Unauthorized duplication of this document, in whole or in part, by any means is prohibited without the
prior written permission of Enclustra GmbH, Switzerland.
Although Enclustra GmbH believes that the information included in this publication is correct as of the
date of publication, Enclustra GmbH reserves the right to make changes at any time without notice.
All information in this document is strictly confidential and may only be published by Enclustra GmbH,
Switzerland.
All referenced trademarks are the property of their respective owners.
Document History
Version Date Author Comment
04 05.09.2022 TKAU Updated for revision 2.1 modules: added information on discon-
tinuation of support for power converter switching frequency syn-
chronisation, changes on base board descriptions
03 16.02.2021 DIUN Added information on Mercury heatsinks, added Mercury+ ST1 to
accesories section, added information on FPGA fuses and warranty,
on differential I/Os, on voltage monitoring outputs, removed 15
Gbps limitation on MGTs due to Hirose connector, other style up-
dates
02 15.11.2019 MMOS Added information on revision 1 and 2 modules, other minor cor-
rections
01 03.06.2019 DIUN Version 01, preliminary
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Table of Contents
1 Overview 6
1.1 General................................................... 6
1.1.1 Introduction................................................ 6
1.1.2 Warranty .................................................. 6
1.1.3 RoHS .................................................... 6
1.1.4 DisposalandWEEE............................................ 6
1.1.5 Safety Recommendations and Warnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1.6 ElectrostaticDischarge.......................................... 7
1.1.7 Electromagnetic Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2 Features .................................................. 7
1.3 Deliverables ................................................ 8
1.4 Accessories................................................. 8
1.4.1 ReferenceDesign............................................. 8
1.4.2 EnclustraBuildEnvironment ...................................... 8
1.4.3 PetalinuxBSP ............................................... 8
1.4.4 EnclustraHeatSink............................................ 9
1.4.5 Mercury+PE1BaseBoard........................................ 9
1.4.6 Mercury+PE3BaseBoard........................................ 9
1.4.7 Mercury+ST1BaseBoard........................................ 9
1.5 XilinxToolSupport ............................................ 10
2 Module Description 11
2.1 BlockDiagram............................................... 11
2.2 Module Configuration and Product Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3 EN-NumbersandPartNames...................................... 12
2.4 TopandBottomViews.......................................... 14
2.4.1 TopView .................................................. 14
2.4.2 BottomView................................................ 14
2.5 Top and Bottom Assembly Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.5.1 TopAssemblyDrawing.......................................... 15
2.5.2 BottomAssemblyDrawing ....................................... 15
2.6 ModuleFootprint............................................. 16
2.7 MechanicalData ............................................. 17
2.8 ModuleConnector ............................................ 17
2.9 UserI/O................................................... 18
2.9.1 Pinout.................................................... 18
2.9.2 I/OPinExceptions ............................................ 19
2.9.3 DifferentialI/Os.............................................. 21
2.9.4 I/OBanks.................................................. 21
2.9.5 VCC_IOUsage............................................... 22
2.9.6 SignalTerminations............................................ 23
2.9.7 MultiplexedI/O(MIO)Pins ....................................... 24
2.9.8 AnalogInputs ............................................... 25
2.10 Multi-Gigabit Transceiver (MGT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.11 Power.................................................... 27
2.11.1 PowerGenerationOverview....................................... 28
2.11.2 PowerEnable/PowerGood ....................................... 29
2.11.3 VoltageSupplyInputs .......................................... 29
2.11.4 VoltageSupplyOutputs ......................................... 30
2.11.5 PowerConsumption ........................................... 30
2.11.6 HeatDissipation.............................................. 30
2.11.7 VoltageMonitoring............................................ 31
2.12 ClockGeneration ............................................. 32
2.13 Reset .................................................... 32
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2.14 LEDs..................................................... 33
2.15 DDR4SDRAM(PS) ............................................ 33
2.15.1 DDR4SDRAMType............................................ 34
2.15.2 SignalDescription ............................................ 34
2.15.3 Termination ................................................ 34
2.15.4 Parameters................................................. 34
2.16 DDR4SDRAM(PL) ............................................ 35
2.16.1 DDR4SDRAMType............................................ 36
2.16.2 SignalDescription ............................................ 36
2.16.3 Termination ................................................ 36
2.16.4 Parameters................................................. 36
2.17 QSPIFlash ................................................. 37
2.17.1 QSPIFlashType.............................................. 37
2.17.2 SignalDescription ............................................ 37
2.17.3 Configuration ............................................... 38
2.17.4 QSPIFlashCorruptionRisk ....................................... 38
2.18 eMMCFlash ................................................ 38
2.18.1 eMMCFlashType............................................. 38
2.18.2 SignalDescription ............................................ 39
2.19 SDCard................................................... 39
2.20 DualGigabitEthernet .......................................... 39
2.20.1 EthernetPHYType ............................................ 39
2.20.2 SignalDescription ............................................ 39
2.20.3 ExternalConnectivity........................................... 40
2.20.4 MDIOAddress............................................... 40
2.20.5 PHYConfiguration ............................................ 40
2.20.6 RGMIIDelaysConfiguration....................................... 41
2.21 USB2.0................................................... 41
2.21.1 USBPHYType............................................... 41
2.21.2 SignalDescription ............................................ 42
2.22 USB3.0................................................... 42
2.23 DisplayPort ................................................ 43
2.24 Real-TimeClock(RTC) .......................................... 43
2.25 SecureEEPROM.............................................. 44
2.25.1 EEPROMType ............................................... 44
3 Device Configuration 45
3.1 ConfigurationSignals .......................................... 45
3.2 ModuleConnectorCDetection .................................... 46
3.3 Pull-UpDuringConfiguration...................................... 46
3.4 Power-onResetDelayOverride .................................... 47
3.5 BootMode................................................. 47
3.6 JTAG..................................................... 48
3.6.1 JTAGonModuleConnector....................................... 48
3.6.2 ExternalConnectivity........................................... 49
3.6.3 JTAGBootMode ............................................. 49
3.7 eMMCBootMode ............................................ 50
3.8 QSPIBootMode ............................................. 50
3.9 SDCardBootMode ........................................... 50
3.10 eMMCFlashProgramming ....................................... 50
3.11 QSPI Flash Programming via JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.12 QSPI Flash Programming from an External SPI Master . . . . . . . . . . . . . . . . . . . . . . . 51
3.13 Enclustra Module Configuration Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4 I2C Communication 52
4.1 Overview.................................................. 52
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4.2 SignalDescription ............................................ 52
4.3 I2CAddressMap ............................................. 52
4.4 SecureEEPROM.............................................. 53
4.4.1 MemoryMap ............................................... 53
5 Operating Conditions 56
5.1 AbsoluteMaximumRatings....................................... 56
5.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6 Ordering and Support 58
6.1 Ordering .................................................. 58
6.2 Support................................................... 58
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1 Overview
1.1 General
1.1.1 Introduction
The Mercury+ XU9 SoC module combines the Xilinx Zynq® UltraScale+ MPSoC (Multiprocessor System-
on-Chip) device with USB 3.0, PCIe® Gen3 ×16, PCIe® Gen2 ×4, two USB 2.0 PHYs, two Gigabit Ethernet
PHYs, DDR4 SDRAM with Error Correction Code (ECC), eMMC flash, multi-gigabit transceivers, high-speed
LVDS I/O, and is available in industrial temperature range, forming a complete and powerful embedded
processing system.
The use of the Mercury+ XU9 SoC module, in contrast to building a custom MPSoC hardware, signif-
icantly reduces development effort and redesign risk and improves time-to-market for the embedded
system.
Together with Mercury+ base boards, the Mercury+ XU9 SoC module allows the user to quickly build a
system prototype and start with application development.
The Enclustra Build Environment [16] is available for the Mercury+ XU9 SoC module. This build system
allows the user to quickly set up and run Linux on any Enclustra SoC module. It allows the user to choose
the desired target and download all the required binaries, such as bitstream and FSBL (First Stage Boot
Loader). It downloads and compiles all required software, such as U-Boot, Linux, and BusyBox based root
file system.
1.1.2 Warranty
Please refer to the General Business Conditions, available on the Enclustra website [1].
Warning!
Please note that the warranty of an Enclustra module is voided if the FPGA fuses are blown. This
operation is done at own risk, as it is irreversible. Enclustra cannot test the module in case of a warranty
product return.
1.1.3 RoHS
The Mercury+ XU9 SoC module is designed and produced according to the Restriction of Hazardous
Substances (RoHS) Directive (2011/65/EC).
1.1.4 Disposal and WEEE
The Mercury+ XU9 SoC module must be properly disposed of at the end of its life.
The Waste Electrical and Electronic Equipment (WEEE) Directive (2002/96/EC) is not applicable for the
Mercury+ XU9 SoC module.
1.1.5 Safety Recommendations and Warnings
Mercury+ modules are not designed to be “ready for operation” for the end-user. These can only be used
in combination with suitable base boards. Proper configuration of the hardware before usage is required.
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Ensure that the power supply is disconnected from the board before inserting or removing the Mercury+
XU9 SoC module, connecting interfaces, or connecting jumpers.
Touching the capacitors of the DC-DC converters can lead to voltage peaks and permanent damage;
over-voltage on power or signal lines can also cause permanent damage to the module.
1.1.6 Electrostatic Discharge
Electronic boards are sensitive to electrostatic discharge (ESD). Please ensure that the product is handled
with care and only in an ESD-protected environment.
1.1.7 Electromagnetic Compatibility
The Mercury+ XU9 SoC module is a Class A product (as defined in IEC 61000-3-2 standard) and is not
intended for use in domestic environments. The product may cause electromagnetic interference, for
which appropriate measures must be taken.
1.2 Features
•Xilinx Zynq® UltraScale+™ MPSoC
•XCZU4CG/XCZU4EV/XCZU5EV/XCZU7EV device
•FBVB900 package
•Dual-/Quad-core ARM® Cortex™-A53 MPCore™ up to 1.333 GHz
•Dual-core ARM® Cortex™-R5 MPCore™ up to 533 MHz
•Mali-400 MP2 GPU (not for CG variants)
•H.264 / H.265 Video Codec (only for EV variants)
•Xilinx 16nm FinFET+ FPGA fabric
•192 user I/Os
•14 ARM peripheral I/Os (SPI, SDIO, CAN, I2C, UART)
•78 FPGA I/Os (single-ended, differential or analog)
•30 HP I/Os
•26 I/Os at 1.2 V (fixed voltage)
•4 I/Os up to 3.3 V (routed via level shifters)
•48 HD I/Os (up to 3.3 V)
•100 MGT signals (clock and data)
•80 GTH MGT signals
•20 GTR MGT signals
•Speedgrade 1 devices: 16 GTH MGTs @ 12.5 Gbit/sec and 8 reference input clock differential pairs
•Other devices: 16 GTH MGTs @ 16.375 Gbit/sec and 8 reference input clock differential pairs
•PCIe Gen3 ×16 (Xilinx built-in PCIe integrated block using GTH lines)
•4 GTR MGTs @ 6 Gbit/sec and 2 reference input clock differential pairs
•PCIe Gen2 ×4 (Xilinx built-in PCIe hard block using GTR lines)
•Up to 4 GB DDR4 SDRAM with ECC on PS side
•Up to 2 GB DDR4 SDRAM on PL side
•64 MB quad SPI flash
•16 GB eMMC flash
•2×Gigabit Ethernet PHY (one PHY shared with one of the USB PHYs)
•2×USB 2.0 PHYs
•PHY0 configured as host or device
•PHY1 configured as host (shared with one of the Gigabit Ethernet PHYs)
•USB 3.0 (Xilinx built-in USB 3.0 hard block using GTR lines)
•Real-time clock
•CAN, UART, SPI, I2C, SDIO/MMC
•5 to 15 V supply voltage
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1.3 Deliverables
•Mercury+ XU9 SoC module
•Mercury+ XU9 SoC module documentation, available via download:
•Mercury+ XU9 SoC Module User Manual (this document)
•Mercury+ XU9 SoC Module Reference Design [2]
•Mercury+ XU9 SoC Module IO Net Length Excel Sheet [3]
•Mercury+ XU9 SoC Module FPGA Pinout Excel Sheet [4]
•Mercury+ XU9 SoC Module User Schematics (PDF) [5]
•Mercury+ XU9 SoC Module Known Issues and Changes [6]
•Mercury+ XU9 SoC Module Footprint (Altium, Eagle, Orcad and PADS) [7]
•Mercury+ XU9 SoC Module 3D Model (PDF) [8]
•Mercury+ XU9 SoC Module STEP 3D Model [9]
•Mercury Mars Module Pin Connection Guidelines [10]
•Mercury Master Pinout [11]
•Mercury Heatsink Application Note [20]
•Enclustra Build Environment [16] (Linux build environment; refer to Section 1.4.2 for details)
•Enclustra Build Environment How-To Guide [17]
•Petalinux BSP and Documentation [18]
1.4 Accessories
1.4.1 Reference Design
The Mercury+ XU9 SoC module reference design features an example configuration for the Zynq Ultra-
Scale+ MPSoC device, together with an example top level HDL file for the user logic.
A number of software applications are available for the reference design, that show how to initialize the
peripheral controllers and how to access the external devices. Pre-compiled binaries are included in the
archive, so that the user can easily check that the hardware is functional.
The reference design can be downloaded from Github: https://github.com/enclustra.
1.4.2 Enclustra Build Environment
The Enclustra Build Environment (EBE) [16] enables the user to quickly set up and run Linux on any En-
clustra SoC module or system board. It allows the user to choose the desired target, and download all
the required binaries, such as bitstream and FSBL. It downloads and compiles all required software, such
as U-Boot, Linux, and BusyBox based root file system.
The Enclustra Build Environment features a graphical user interface (GUI) and a command line interface
(CLI) that facilitates the automatic build flow.
The Enclustra Build Environment How-To Guide [17] describes in more detail how to use the EBE to cus-
tomize the provided software for the user application. The document provides information on the con-
figuration options for U-boot, Linux kernel and Buildroot, debugging possibilities for Linux applications,
customization of device trees and integration of existing or new kernel drivers.
1.4.3 Petalinux BSP
The Enclustra Petalinux BSPs enable the user to quickly set up a Petalinux project and to run Linux on the
Enclustra SoC module or system board.
The documentation [18] describes the build process in detail and allows a user without Petalinux knowl-
edge to build and run the desired design on the target hardware.
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1.4.4 Enclustra Heat Sink
For Mercury modules an Enclustra heat sink is available for purchase along with the product. Please refer
to section 2.11.6 for further information on the available cooling options.
1.4.5 Mercury+ PE1 Base Board
The Mercury+ PE1 is a versatile PCIe® x4 base board equipped with a multitude of I/O interfaces for use
with the Mercury/Mercury+ family of FPGA and SoC modules, providing a head start for building custom
FPGA and SoC based hardware systems.
It is compatible with a multitude of FMC boards from different suppliers to use in data acquisition systems,
motor control, display and camera interfaces, software defined radio and more. The board is equally well
suited for rapid prototyping and for building FPGA systems without designing custom hardware.
For more information visit
https://www.enclustra.com/en/products/base-boards/mercury-pe1-200-300-400/.
Please note that the available features depend on the equipped Mercury module type and on the selected
base board variant.
Warning!
Due to the pinout assignments (pin types and I/O voltage levels) on module connectors B and C,
affecting the FMC interfaces, the compatibility of the Mercury+ XU9 SoC module to the Mercury+ PE1
base board is limited. It is recommended to check the FMC card pinout in detail with the Enclustra
Mercury Master Pinout and with the module and base board schematics.
1.4.6 Mercury+ PE3 Base Board
The Mercury+ PE3 is a versatile PCIe® x8 base board equipped with a multitude of I/O interfaces for use
with the Mercury/Mercury+ family of FPGA and SoC modules, providing a head start for building custom
FPGA and SoC based hardware systems.
This high performance base board provides a versatile set of I/O connectivity options, specialized for
high-speed communication and video applications, including SFP+, QSFP+, HDMI, USB Type-C and Fire-
fly. The board is equally well suited for rapid prototyping and for building FPGA systems without design-
ing custom hardware.
For more information visit https://www.enclustra.com/en/products/base-boards/mercury-pe3/.
Please note that the available features depend on the equipped Mercury module type and on the selected
base board variant.
1.4.7 Mercury+ ST1 Base Board
The Mercury+ ST1 board is a compact, low-cost base board equipped with a multitude of I/O interfaces
for use with the Mercury/Mercury+ family of FPGA and SoC modules.
It provides a versatile set of I/O connectivity options, specialized for video applications, including MIPI,
HDMI and SFP+. The board is equally well suited for rapid prototyping and for building FPGA systems
without designing custom hardware.
For more information visit https://www.enclustra.com/en/products/base-boards/mercury-st1/.
Please note that the available features depend on the equipped Mercury module type and on the selected
base board variant.
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1.5 Xilinx Tool Support
The MPSoC devices equipped on the Mercury+ XU9 SoC module are supported by the Vivado HL Web-
PACK Edition software, which is available free of charge. Please contact Xilinx for further information.
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2 Module Description
2.1 Block Diagram
Figure 1: Hardware Block Diagram
The main component of the Mercury+ XU9 SoC module is the Xilinx Zynq UltraScale+ MPSoC device. All
available I/O pins (which are not routed to on-board peripherals) are connected to the Mercury+ module
connector, making 92 regular user I/Os available to the user. Further, twenty MGT pairs are available
on the module connector, making possible the implementation of several high-speed protocols such as
PCIe Gen3 ×16, PCIe Gen2 ×4 and USB 3.0 (simultaneous usage of all the interfaces is limited to the
available hardware resources i.e. number of transceivers and lane mapping).
The MPSoC device can boot from the on-board QSPI flash, from the eMMC flash or from an external SD
card. For development purposes, a JTAG interface is connected to Mercury module connector.
The available standard configurations include a 16 GB eMMC flash, a 64 MB quad SPI flash, up to 4 GB
DDR4 SDRAM with ECC connected to the Processing System (PS) and up to 2 GB DDR4 SDRAM connected
to the Programmable Logic (PL).
Further, the module is equipped with two Gigabit Ethernet PHYs and two USB 2.0 PHYs, making it ideal
for communication applications.
A real-time clock is available on the Xilinx Zynq UltraScale+ MPSoC device.
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On-board clock generation is based on a 33.33 MHz crystal oscillator and a 100 MHz LVDS oscillator
providing a clock for the PL and a reference clock for the MGT GTR lines. In addition to this, another 27
MHz oscillator delivers a reference clock for the MGT GTR lines.
The module’s internal supply voltages are generated from a single input supply of 5 - 15 V DC. Some of
these voltages are available on the Mercury module connectors to supply circuits on the base board.
Five LEDs are connected to the MPSoC pins for status signaling.
2.2 Module Configuration and Product Models
Table 1 describes the available standard module configurations. Custom configurations are available;
please contact Enclustra for further information.
Product Model MPSoC DDR4 ECC DDR4 Temperature
SDRAM (PS) SDRAM (PL) Range
ME-XU9-4CG-1E-D11E XCZU4CG-1FBVB900E 2 GB 2 GB 0 to +85◦C
ME-XU9-5EV-1I-D12E-L11 XCZU5EV-1FBVB900I 4 GB 2 GB -40 to +85◦C
ME-XU9-7EV-2I-D12E-L11 XCZU7EV-2FBVB900I 4 GB 2 GB -40 to +85◦C
Table 1: Standard Module Configurations
The product model indicates the module type and main features. Figure 2 describes the fields within the
product model.
Figure 2: Product Model Fields
Please note that for the first revision modules or early access modules, the product model may not respect
entirely this naming convention. Please contact Enclustra for details on this aspect.
2.3 EN-Numbers and Part Names
Every module is uniquely labeled, showing the EN-number and serial number. An example is presented
in Figure 3.
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Figure 3: Module Label
The correspondence between EN-number and part name is shown in Table 2. The part name represents
the product model, followed by the revision; the R suffix and number represent the revision number.
The revision changes and product known issues are described in the Mercury+ XU9 SoC Module Known
Issues and Changes document [6].
EN-Number Part Name
EN105161 ME-XU9-4CG-1E-D11E-R2.1
EN105162 ME-XU9-5EV-1I-D12E-L11-R2.1
EN105166 ME-XU9-7EV-2I-D12E-L11-R2.1
Table 2: EN-Numbers and Part Names
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2.4 Top and Bottom Views
2.4.1 Top View
Figure 4: Module Top View
2.4.2 Bottom View
Figure 5: Module Bottom View
Please note that depending on the hardware revision and configuration, the module may look slightly
different than shown in this document.
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2.5 Top and Bottom Assembly Drawings
2.5.1 Top Assembly Drawing
Figure 6: Module Top Assembly Drawing
2.5.2 Bottom Assembly Drawing
Figure 7: Module Bottom Assembly Drawing
Please note that depending on the hardware revision and configuration, the module may look slightly
different than shown in this document.
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2.6 Module Footprint
Figure 8 shows the dimensions of the module footprint on the base board.
Enclustra offers Mercury and Mercury+ modules of various geometries having widths of 56, 64, 65, 72 or
74 mm and having different topologies for the mounting holes. If different module types shall be fixed
on the base board by screws, additional mounting holes may be required to accommodate different
modules. The footprints of the module connectors for the base board design are available for different
PCB design tools (Altium, PADS, Eagle, Orcad) [7] and include the required information on the module
sizes and holes.
The maximum component height under the module is dependent on the connector type - refer to Section
2.8 for detailed connector information.
Figure 8: Module Footprint - Top View
Warning!
It is possible to mount the Mercury+ XU9 SoC module the wrong way round on the base board - always
check that the mounting holes on the base board are aligned with the mounting holes of the Mercury+
XU9 SoC module.
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2.7 Mechanical Data
Table 3 describes the mechanical characteristics of the Mercury+ XU9 SoC module. A 3D model (PDF)
and a STEP 3D model are available [8], [9].
Symbol Value
Size 74 ×54 mm
Component height top 3.00 mm
Component height bottom 1.35 mm
Weight 32 g
Table 3: Mechanical Data
2.8 Module Connector
Three Hirose FX10 168-pin 0.5 mm pitch headers with a total of 504 pins have to be integrated on the
base board. Up to four M3 screws may be used to mechanically fasten the module to the base board.
Do not use excessive force to tighten the screws, as this could damage the module.
The pinout of the module connector is found in the Mercury Master Pinout Excel Sheet [11]. The con-
nector is available in different packaging options and different stacking heights. Some examples are
presented in Table 4. Please refer to the connector datasheet for more information.
Reference Type Description
Mercury module connector FX10A-168S-SV Hirose FX10, 168-pin, 0.5 mm pitch
Base board connector FX10A-168P-SV(71) Hirose FX10, 168-pin, 0.5 mm pitch, 4 mm
stacking height
Base board connector FX10A-168P-SV1(71) Hirose FX10, 168-pin, 0.5 mm pitch, 5 mm
stacking height
Table 4: Module Connector Types
Figure 9 indicates the pin numbering for the Mercury module connectors from the top view of the base
board. The connector pins are numbered as follows:
•Connector A: from J800-1 to J800-168
•Connector B: from J801-1 to J801-168
•Connector C: from J900-1 to J900-168
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Figure 9: Pin Numbering for the Module Connector
Warning!
Do not use excessive force to latch a Mercury module into the Mercury connectors on the base board,
as this could damage the module and the base board; always make sure that the module is correctly
oriented before mounting it into the base board.
2.9 User I/O
2.9.1 Pinout
Information on the Mercury+ XU9 SoC module pinout can be found in the Enclustra Mercury Master
Pinout [11], and in the additional document Enclustra Module Pin Connection Guidelines [10].
Warning!
Please note that the pin types on the schematics symbol of the module connector and in the Master
Pinout document are for reference only. On the Mercury+ XU9 SoC module it may be possible that
the connected pins do not have the targeted functions (such as primary clocks, differential pins, MGT
signals, etc).
The naming convention for the user I/Os located in HP banks is:
IO_B<BANK>_L<PAIR><_SPECIAL_FUNCTION>_<PACKAGE_PIN>_<POLARITY>.
For example, IO_B65_L6_AD6_AF10_P is located on pin AF10 of I/O bank 65, pair 6, it is a System Monitor
differential auxiliary analog input capable pin and it has positive polarity, when used in a differential pair.
The HD banks are numbered differently depending on the MPSoC device equipped on the module:
•Bank N represents:
•I/O bank 46 for ZU4/ZU5 devices
•I/O bank 47 for ZU7 devices
•Bank O represents:
•I/O bank 45 for ZU4/ZU5 devices
•I/O bank 48 for ZU7 devices
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The naming convention for the user I/Os located in HD banks is:
IO_B<BANK_LETTER>_L<PAIR><_SPECIAL_FUNCTION>_<PACKAGE_PIN>_<POLARITY>
For example, IO_BN_L7_HDGC_AD5_E13_N is located on pin E13 of I/O bank N, pair 7, it is a System
Monitor differential auxiliary analog input capable pin and also a clock capable pin and it has negative
polarity, when used in a differential pair.
The global clock capable pins are marked with “GC” (HP I/O banks) or with “HDGC” (HD I/O banks) in the
signal name. For details on their function and usage, please refer to the Xilinx documentation.
Table 5 includes information related to the total number of I/Os available in each I/O bank and possible
limitations.
Signal Name Sign. Pairs Differential Single- I/O Bank
ended
IO_B64_<...> 4 0 - In/Out 64 (HP)1
IO_B65_<...> 20 10 In/Out In/Out 65 (HP)1
IO_B66_<...> 6 0 - In/Out 66 (HP)1
IO_BN_<...> 24 12 In/Out (no LVDS/LVPECL outputs
supported; internal differential
termination not supported)
In/Out 46 (HD)1for ZU4/ZU5
47 (HD)1for ZU7
Refer to Section 2.9.3 for details.
IO_BO_<...> 24 12 In/Out (no LVDS/LVPECL outputs
supported; internal differential
termination not supported)
In/Out 45 (HD)1for ZU4/ZU5
48 (HD)1for ZU7
Refer to Section 2.9.3 for details.
Total 78 34 - - -
Table 5: User I/Os
The multi-gigabit transceiver (MGT) are described in section 2.10.
2.9.2 I/O Pin Exceptions
The I/O pin exceptions are pins with special functions or restrictions (for example, when used in combi-
nation with certain Mercury boards they may have a specific role).
PCIe Reset Signal (PERST#)
Table 6 lists the I/O pin exceptions on the Mercury+ XU9 SoC module related to the PCIe reset connection.
1HD = high density pins, HP = high performance pins; Refer to the Zynq UltraScale+ MPSoC Overview [25] for details.
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I/O Name Module Connector Pin Description
PS_MIO42_PERST# A-104 When the pin has a low value, its value is routed
via a 1 kΩresistor to ETH0_TXD3_PS_PERST# pin
(MIO30) and via a 47 kΩresistor and a level shifter
to PL_PERST#_LS (MPSoC package pin AF2) for PCIe
PERST# connection implementation
Table 6: I/O Pin Exceptions - PERST#
When the Mercury+ XU9 SoC module is used in combination with a Mercury+ PE1 base board as a PCIe
device, the PERST# signal coming from the PCIe edge connector on the module connector pin A-104
(PS_MIO42_PERST#) is driven further to PL_PERST#_LS and to ETH0_TXD3_PS_PERST# (MIO30) when its
value is low.
When a PCIe block on the PL side is used, the PERST# signal is connected to the MPSoC pin PL_PERST#_LS
via a 47 kΩresistor and a level shifter.
When a PCIe block on the PS side is used, the PERST# signal is routed via a 1 kΩresistor to MIO30. This
is the default MIO pin used for the reset signal of the PCIe PS built-in block, therefore it was chosen for
the reset implementation. The Ethernet controller 0 is disabled when the PCIe hard block is used; note
that any other valid position for PERST# would have resulted in having the Ethernet controller disabled.
Using a PCIe block in the PL simultaneously with Gigabit Ethernet 0 interface on the PS side is possible.
Simultaneous usage of two PCIe endpoints on the PL and PS sides is not supported and was not tested
on Enclustra side.
In situations in which PCIe functionality is not required, PS_MIO42_PERST# pin can be used in the same
manner as a regular MIO pin.
For root complex applications the PERST# signal can be placed on any unused MIO pin (the restriction
on MIO30/42 does not apply in this case).
I/O Pins with Level Shifter
There are four signals on the Mercury+ XU9 SoC module that are routed from the FPGA banks to the
module connector via level shifters - these are presented in Table 7.
I/O Name Module Connector Pin Description
IO_B64_AF17_LS A-88
These pins have a level shifter from VCC_1V2
IO_B64_AC19_LS A-90
to VCC_CFG_MIO
IO_B64_AH16_LS A-92
IO_B64_AG19_LS A-94
Table 7: I/O Pin Exceptions - Level Shifters
The level shifters used for the I/O pins mentioned in Table 7 are NXP NTB0104 and the maximum achiev-
able data rate on these pins is 30 Mbit/sec.
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