Facit 4431 Original operating manual

I

'DETAILED

LIST

OF

CONTENT

AT

PAGES

42-43

~

SERVICE INSTRUCTION 4431

Edition 1

Pub

1•

No.

1160

82

17-12/8

Eng.

DECEMBER

1982

K.F.

Printed

in Sweden

VIDEO TERMINAL ......

__

Facit

AB

·

Technical

Service

Department

·

S-597

00

ATVIDABERG

·SWEDEN

2

SCOPE

OF

THE

MANUAL

The

information contained in

this

manual

is

in-

tended

for

the maintenance group,

other

avail-

able documents are:

Facit

4431

Technical Description

Facit

4431

Operator

Guide

INT

R 0

DUCT

I 0 N

_______

_

As

with

any

electronic

equipment,

all

standard

safety

precautions should

be

observed while

servicing

the

Facit

4431

Video

Terminal.

Any

servicing

which

requires

opening the

cabinet

must

be

performed only

by

qualified

service

personnel.

***********************************************

WARNING

Hazardous voltages are exposed

when

the

cabinet

top

is

removed.

Use

extreme caution

when

servi-

cing the monitor assembly or

power

supply.

Un-

der

certain

conditions dangerous

potentials

may

exist

even

when

the

power

is

off

due

to the

cathode ray tube.

***********************************************

In

the

text

and

on

the schematics,

locations

are referenced in the following manner:

Part

number

(IC

number)

(:pin

number)

(Signal

name)

(Schematic page).

Example:

Reference

to

19

of

D71

located

at

page

MEM

Circuit

Diagram:

D71:19

RD

ATT.(MEM)

Acronyms

and

Abbreviations:

Main

Logic

Board

Schematic Drawings:

IJO

Input/output

interface

KBD

Keyboard

interface

MEM

Display Refresh

RAM

CPU

Processor

SG

Sync

Generator

VG

Video

Generator

Devices:

CPU

CRT

CRTC

EAR

OM

EPROM

LED

RAM

ROM

SIO/DART

Central Processing Unit

Cathode

Ray

Tube

CRT

Controller

Electrically

Alterable

Read-Only

Memory

Eraseable Programmable Read-Only

Memory

Light Emitting

Diode

Random

Access

Memory

Read

Only

Memory

Serial

Input/output or

Dual

channel

Asynchronous Receiver/Transmitter

1.1

DESIGN

The

terminal

consists

of

three

major physical

subassemblies:

the

Main

Logic

Board

(MLB)

the Keyboard

(KBD)

the Monitor assembly

and

the

Power

Supply

(PS)

The

majority

of

servicable

components are

on

the

Main

Logic Board,

which

provides

six

(6)

major

circuit

functions:

1.

Keyboard

Interface

2. Microprocessor Control

3. Input/Output

Interfaces

4. Display Refresh

Memory

5. Synchronization Generator

6.

Video

Generator

Chapter 6 contains a general

circuit

descrip-

tion

and

each of

these

circuits

are described

in

detail

in Section 7 of

this

manual. A block

diagram showing the

main

functional components

of

the

terminal

is

given in Fig

7.1.

The

rest

of

Section 7 describes

how

these

components

combine

to

perform

all

terminal

operations.

1.2

SPECIFICATIONS

Monitor

Screen

capacity

Characters per

line

Number

of

lines

Screen

Tube

size

Veiwing

area

Character

size

Referesh

rate

Scan

method

Character generator

Frequency

Interface

CCITT

V24/RS-232-C

Current

Loop

(Optional)

1920/3168

characters

80/132

25(24 +

status

line)

Green

phosphor,

P42

C

Non

glare

with

medium

short

percistance

(300uS)

30.5

cm

(12") diago-

nal

310

sq.

cm

(48

sq.in.)

20

cm

x

15

cm

(8"x6")

rectangele

(centered

on

screen)

+/-0,2"

(80col)

5mm

high x 2

mm

wide(0.2"x0.08")

(132col)

5mm

high x

2mm

wide

(0.2"x0.05")

50

or

60Hz

Raster

128

displayable

char.

(inc.

space)

Alterna-

tiv

set

possible

7 x

9

character

defini-

tion

with 2 dot sepa-

ration

between cha-

racters.

15

700Hz

+/-

500Hz

Composite video output (Optional)

Protocols

Environmental Conditions

Temperature

Voltages

Frequencies

Consumption

Dimensions

Display Unit

Width

Depth

Height

Keyboard

Width

Depth

Height,

rear

Height,

front

Total weight

Data

format

Data

bits

Data

bit

8

Parity

Data

transfer

rate

Operator

controls

Switches:

ON/OFF

X-ON/X-OFF

protocol

10°

to

4o

0c

rational)

-10°

to

6o

0c

(storage)

117V

220V

49-61Hz

65

Watts

32.6cm

(12.8")

40.2cm

(15.8")

37cm

(14.7")

43.8cm

(17.25")

26cm

(10.2")

6.4cm

(2.5")

1.0cm

(0.4")

20

Kg

(44lb)

(ope-

8 or 7 asynchronous

0 or deleted

Odd,even

or

inhibited

75

to 19.200

bits/-

sec.

2 R E C E I V I N

G,

U NP A C K I NG

AND I NS

PE

CT I 0 N

_____

_

The

Facit

4431

terminals are

carefully

packed

to insure

safety

during shipment, however,

when

the terminal

arrives

check

the following:

• the invoice against your

original

purchase

order

•

examine

the outside of the shipping

contai-

ner

closely

for signs of abuse or

damage

in

transit

A chrushed or punctured carton

naturally

calls

for a careful inspection of the contents,

if

any

damage

is

found

inform the delivery agent

about

any

damage

found.

3

2.1

POWER

AND

SIGNAL

WIRING

The

4431

terminal wiring

consists

of

an

AC

po-

wer

cord

which

is

included with the display

unit.

The

keyboard

is

connected

to

the display

unit

by

a

flexible

coiled cable.

The

V24/RS232C

sig-

nal cables are provided

by

the customer.

2.2

POWER

ON/PERFORMANCE

CHECK

Inspection before

power

on:·

• check

that

the

model

plate

corresponds to

order

and

packing case marking

• check for proper keyset

• check

that

accessories

and

documentation are

supplied

• check,

and

if

not appropriate, modify the

power

connection to your national standard.

Make

sure

that

proper grounding

is

performed

and

that

proper voltage

is

selected.

Also

check fuse value, should

be

0.5Amp

slow

at

220/240Volts

and

1Amp

at

115Volt.

Power

On

This

test

require a Test gear such

as

Facit

Text Generator or a

4208

Casset Drive with spe-

cial

Demo

or Test program.

NOTE:

Before connecting the terminal to

ANY

external data source, see to

it

that

the

ter-

minal

is

connected to the

Mains

with proper

grounding,

this

procedure will take care of

any

eventuall high voltage discharge through the

interface

cable causing

damage

to the Line

dri-

ver/Receiver

circuits.

• wait approx. 1 minute to observe

normal

screen illumination (the

raster

may

be

vi-

sible

during

few

minutes of

warm

up).

•

upon

power-up

all

seven

LED's

will

be

lit

for

about 0.5 sec.

The

country/product se-

lect

code

is

displayed

on

the

LED's

for

ap-

prox. 1 second (See the country/product se-

lect

table

below).

LED's

Meaning

xxx

xxOO

4420

xxx

xx10

4430

xxx

xx11

4431

000

xx

us

001

xxxx

Swe/Fin

010

xx

Germany

011

xxxx

Denmark

100

xx

Britain

101

xx

Spain

110

xxxx

France

111

xxxx

Norway

4

NOTE

If

during

initialization

a suspected

fault

is

detected, the bell will ring 5 times

and

an

error

code

will

be

displayed in the

up-

per

left

portion of the screen.

If

the terminal

halts

with

all

the

LED's

on,

then the processor

has

determined

that

the scratchpad

RAM

D72

is

defective

and

no

furhter

tests

are attempted.

ERROR

CODES:

2

4

display

memory

fault

EAROM

parity

error

EAROM

checksum

error

(For

instruction

how

to

repair,

see Chapter

10)

• disconnect the keyboard

from

the terminal

and

power

on

the terminal,

after

approx. 5

sec. a presentation of the terminal

program

revision

is

shown

at

the upper

left

corner

of the display.

Ex.

FACIT

4431

rev.

"D.X."

9/82

1

if

no

fault

is

detected

you

may

continue

with the performance check,

first

enter

Set-

Up

mode

and

do

as

follows: (use the Operator

Guide

as

reference

if

necessary)

1

SET-UP

A.

a

change

the brightness

setting

using cursor

up

for increased brightness

and

cursor

down

to

reduce the brightness,

minimum

brightness

should

be

with the half

intensity

area

just

visible,

if

the

intensity

need

adjustment, see

chapter 9 for

instructions.

b depress

key

(3) to

clear

all

tabs,

move

the

cursor

and

depress

key

(2) to toggle

Change

Tabs,

set

the tabs in

random

positions. Reset

the terminal

and

check

that

the

Tabs

are in

proper positions again,

when

entering the

SETUP

A

mode.

c depress

key

(9)

to

enter

into

132

column

mode,

control

that

the

left

or

right

margins of

the screen

does

not fold back,

if

so

adjustment

is

needed

and

is

explained in chapter 9. Enter

80

column

mode

again.

d depress

PF1

and

PF2

and

to

change

pages, see

upper

right

corner of the screen.

e

enter

SET-UP

B,

depress

key

(5),

move

cursor

and

toggle the displayed switches

by

using

key

(6),

set

all

(1) to (0)

and

all

(O)

to (1) (no-

te

that

in

column

3 switch 4

can

not

be

changed

from

0)

and

change the T

SPEED

and

R

SPEED

to

75

by

depressing of

key

(7)

and

(8). Recall fac

tory

settings

by

depressing the

Shift

key

and

R

at the

same

time,

(SHIFT)+(R).

Return to

SET-UP

B

mode.

f depress

key

(5) to enter

SET-UPC

mode.

Make

the

same

procedure

as

above

with the displayed

switches

and

the

printer

speed.

Note

that

in

column

4,

switches 2,3,

and

4

can

not

be

chang-

ed

from

0.

g

reset

the terminal. Enter

SET-UP

A

and

set

the terminal in

LOCAL

MODE,

depress

key

(4).

h depress

(ESC)

(Shift

+

3)

(8)

(The

termi-

nal

must

be

in

ANSI

mode).

This

command

fills

the

entire

screen area (exept

row

25)

with E's

for screen focus

and

screen geometry alignment.

If

any

adjustment

is

necessary see chapter 9

for advice. Reset the terminal.

i with the terminal in local

mode,

test

all

keys

for proper

movement

and

function.

j connect a

suitable

data source to the 1/0

connector

and

a

Printer

to the

Printer

connec-

tor,

use

speciall

test

program

or

demo

program

for

this

test.

k depress

(ESC)

(5B)

(2)

(;)

(9) (y).

Note

that

the

key

for the

5B

Hex

code

is

to

be

se-

lected

by

the aid of National version keyboard

code

and

command

summary

listing

in the Techni-

cal description

for

the

4431

terminal. This

com

mand

initiates

a

series

of special

tests

for

use

by

servicing personnel.

The

test

is

repea-

ted

until

a

failure

occurs or

until

the

power

is

switched

off.

•

Finally,

fill

in

and

send the

test

report

to

Facit

AB,

Technical Service

Department

S-597

00

Atvidaberg

SWEDEN

3

INSTALLATION

_______

_

3.1

INITIAL

SETTING-UP

The

Fa~it

4431

display unit should

be

positioned

on

a firm surface; the display unit

tilts

on

its

stand to allow the user to optimise the viewing

an~le.

The

keyboard connector

(at

the

end

of the

coiled connector lead) plugs into the

rear

of

the display

unit,

in the lefthand socket (viewed

from

the read, see Fig).

The

keyboard

may

then

be

positioned to

suit

the user.

~nsure

~hat

the

mains

supply lead

is

terminated

in

a

suitable

plug for the local

power

outlet

(a

ground

connection

must

be

incorporated).

Refer to section 4 for

interface

connections

to

both the host

and

local

printer

(if

required).

3.2

ACCESS

TO

MAIN

LOGIC

BOARD

IN

DISPLAY

UNIT

The

user will

need

access

to

the

main

logic

board

to

alter

the

setting

of jumpers described

in sections

to

and

access in gained

as

follows:

Switch

off

the

unit

and

disconnect

from

the

mains

supply.

2 There are four slot-head

fixing

screws

which

retain

the display unit top cover. These are

located

at

the bottom of the cover, under the

lip,

close to

where

the stand

enters

the

dis-

play

unit

body.

The

screws

can

be

accessed

from

below

by

means

of a short screw-driver.

To

remove

the cover the screws

must

be

scre-

wed

IN

(clockwise)

as

far

as

they will

go.

3

Grasp

the

lip

of the cover

on

each

side,

pull

outwards

and

simultaneously

lift

the cover.

4 Access to the jumpers

on

the

main

logic board

is

now

possible.

5 Replacement of the cover

is

the reverse of

the removal.

The

retaining

screws

must

then

be

screwed

OUT

(anticlockwise) as

far

as they

wil 1

go.

5

FIG

3.1

5

3.3

ACCESS

TO

KEYBOARD

PCB

The

user will

need

access

to

the keyboard

p.c.b.

to allow the

setting

of jumpers described in

sections

and

access

is

gained as follows:

Switch

off

the unit

and

disconnect the key-

board

from

the display

unit.

2

Remove

the

two

retaining

screws

at

the

right

hand

end

of the keyboard,

and

then

remove

the

end

cap.

3 Slide out the printed

circuit

board (discon-

necting the loudspeaker lead

if

necessary)

and

lift

off

the top

plate.

4

The

jumpers

and

associated

components

are

to

be

found

along the top of the

p.c.b.

5 Reassembly of the keyboard

is

the reverse of

the above. Ensure

that

the

p.c.b.

and

top

plate

slide

in the

retaining

grooves in the

keyboard housing.

3.4

KEYCLICK/BELL

VOLUME

ADJUSTMENT

The

audible tones produced

by

the

unit

are gene-

rated

by

a small loudspeaker

mounted

in the key-

board.

The

level of

sound

produced

may

be

adju-

sted

by

rotating

(by

means

of a small screw-dri-

ver) the

SPKR

VOL

ADJ

potentiometer. This

is

located in the

left

hand

top corner of the key-

board

p.c.b.

1

Rear

panel

2

Top

cover

3 Monitor

(CRT)

retaining

screws

4 Front panel

5

Volume

adj. pot

6

End

cap

screw

-<111111@

6

---c@

6

3.5

JUMPERS

ON

THE

MAIN

LOGIC

BOARD

Jumper

W1.

With

jumper

W1

inserted,

+5V

is

app-

lied

to the

I/0

connector pin 18.

Jumper

W3.

This jumper

makes

it

possible

to

choose

either

2716

or

2732

as

character genera-

tor

(D40).

See

Fig 3.3

for

details.

Jumper

W4.

Inserted Test

mode,

(factory

test

only).

Jumper

W5.

Inserted

EROM

Write Enable.

3.5.1

KEYBOARD

PCB

Two

groups of jumpers are

fitted

to the keyboard

PCB.

3.5.1.1

Facit

4431

Selection

(W2)

Jumper

W2

on

the keyboard

PCB

must

be

fitted

for

Facit

4431

operation.

Jumper

W1

is

not

fitted.

O

SPKR

VOL

ADT

W1

W2

:I'~

SET

UP

BREAK

3.5.1.2

National

Keyboard

Selection (W4,5,6)

Jumpers

W4,

W5

and

W6

on

the keyboard

PCB

are

used

to

select

which

country the keyboard

is

for

use

in.

Jumper

W3

is

not

fitted.

The

table

below

shows

the possible combinations.

The

keyboard

will

be

supplied

set

to

one

particular

configu-

ration

with appropriate keytops

fitted.

If

a

change

is

made

to the

jumper

settings

the key-

tops should also

be

changed

(and

a

new

character

generated

ROM

fitted).

Country

U.S. (ASCII)

Sweden/Finland

Germany

Denmark

Britain

Spain

France

Norway

E

W4

WS

0

C::::>

Ill

W4

Down

Up

Down

Up

Jumper

W5

W6

Down Down

Up

Down

Up

Down

Up

Down

Up

Up Up

Down

Up

FIG

3.2 Keyboard

PCB

Jumper Locations

3.5.2

MAIN

LOGIC

PCB

There are 4 jumpers

fitted

to the

main

logic

board

as

shown

in Fig 3.3.

3.5.2.1

+5V

on

I/0

Connector

18

(W1)

18

on

the

I/0

connector

may

be

linked to

+5V

by

fitting

jumper

W1.

+5V

on

18

is

required

by

the

Facit

5165/66 Current

Loop

Adapter.

When

the

jumper

is

not

fitted

18

is

connected in-

ternally.

3.5.2.2

Standard/Extended Character Generator

(W3)

When

the standard

character

generator

PROM

is

fitted

(type

2716)

the jumper

W3

must

link the

centre

and

right

hand

pins (see Fig

3.3).

When

extended

character

generator

is

used (type

2732)

the jumper

must

link

the

centre

and

left

hand

pins.

7

3.5.2.3

Production Test

(W4)

This jumper

is

used only during production.

It

must

not

be

fitted

during

normal

operation.

3.5.2.4

Disable/Enable

Save

(W5)

The

user

may

prevent the operator saving

alterna

tive

Set-up parameter values (using the

SAVE

function)

by

removing the jumper

W4.

When

this

jumper

is

fitted

the

SAVE

function

works

as

de-

scribed in

section

5.

~----------------------------·--------------

DODD

~Ows

DD

.

1

on

I I

L__J

D

DDlJ

DOD

CJ

D

~

I I

D

[l D I I

On I I

LJ

DD

D

DD

Do

D

DODD[

W1

= =

FIG

3.3 Main Logic Board

8

4 I NT E R F A C E

INFORMATION=

The

interface

connectors

at

the rear of

terminal are

shown

below.

4.1

V.24/RS-232-C

COMMUNICATION

INTERFACE

the

The

pin assignments for the 25-pin

male

V.24/RS

-232-C

communication

connector are

as

follows:

Connector

Host Terminal

1 Ground

2 Serial Data

Out

_..3 Serial Data In

~

-4.

4 RTS (always high)

5 CTS (Required) -note

-..

.....

6 DSR (Ignored)

7 Signal Ground

8 CD (Ignored,

but

monitored)

-.. 18

+5V

-note 3

-4.

19

READY/BUSY

-note 2

...._

20

-...-

DTR

(Alw'!Y._s

hj_g_h)

NOTES:

(1)

CTS

signal

must

be

present

at

the

terminal (high) before data

can

be

sent to the host.

(2)

READY

=

High

BUSY

=

Low

(3)

+5V

for Facit

5166

current

loop

adapter, supplied

by

fitting

a

jum-

per

on

the

main

logic board.

4.2

V.24/RS-232-C

PRINTER

INTERFACE

The

pin assignments for the female

V.24/RS-232

-C

printer

connector are

as

follows:

Connector

Printer Terminal

1 Ground

2 Data In

(X-ON/X-OFF

from

printer)

3 Data

Out

7 Signal Ground

18 Not used

~~~~~~~~~~~-

19 Printer

READY/BUSY

-note

NOTES:

READY

High

BUSY

Low

4.3

CURRENT

LOOP

INTERFACE

Current loop

interface

adapter

may

be

fitted

onto the

I/0

interface

connector

(Facit

5166)

of the

Facit

4431.

The

terminal connectors

may

be

internally

linked (via jumper), to provide a

+5V

supply to the adapter,

which

is

all

that

is

required

for

passive/passive operation.

Where

the user wishes to

employ

an

active

transmitter

an

external

12V

supply

must

be

provided.

4.4

COMPOSITE

VIDEO

OUTPUT

The

Facit

4431

provides a composite video

for

use with

an

external video device.

The

compo-

site

signal

is

a combination of the video

sig-

nal

and

horizontal

and

vertical

synchronisation

signals.

Connection

is

via a female

phono

con-

nector.

The

output

impedance

is

75

ohms.

The

video signal

is

of the

RS170

type.

5 S E T - U P

FEATURES

___

_

5.1

GENERAL

FEATURES

OF

SET-UP

MODE

Set-Up

mode

is

entered

by

depressing the

(SET-

UP)

key

on

the keyboard.

Initially

the

SET-UP

A

display

is

shown.

At

any

time in the

SET-UP

mode

the operator

may

adjust the brightness of the screen, switch

between

on-line

and

local operation, change or

recall

the

EAROM

values or

reset

the terminal

to

its

initial

state.

Exit

from

Set-Up

mode

(A,

B or

C)

may

be

at

any

time pressing the

(SET-UP)

key

again.

On

exit

from

SET-UP

mode,

the parameter value are pre-

served

and

will

be

displayed again

whenever

SET-UP

mode

is

entered (exept

after

Power

Off)

You

will find a

detailed

information about the

SET-UP

mode

in the Technical Description.

5.2

SET-UP

MODE

SUMMARY

GENERAL

SET-UP FEATURES

(SET-UP

A,

Band

C)

Line/Local

Screen Brightness

Save Set-up Features

Recall Set-up Features

Recall Factory Settings

Recall Factory Tabs

Reset Terminal

SET-UP B

[4]

to

toggle

[t1

to

increase

[

~

1

to

decrease

[SHIFT] +[SJ

[SHIFT].+[R]

[SHIFT] +[DJ

[SHIFT] +[T]

[OJ

SET-UP A

Change Tabs

Clear

All

Tabs

80/132

Column

Page 1/Page 2

Set-up B

[2]

to

toggle

[3]

[9]

to

toggle

[PF1] I [PF2]

(80 column, 2 page mode)

[5]

Set PF Keys sequence

Set Answerback message

T0ggle displayed switches.

[SHIFT] +[PFx] [delimiter] sequence[delimiter]

(x"'

1

to

4)

[SHIFT] +[A] [delimiter] message[delimiter]

Increment T SPEED

Increment R SPEED

Set-up C

SET-UPC

[6]

[7]

[8]

[5]

Toggle displayed switches [6]

Increment PRINTER SPEED -

Set-up A [7]

or

[8]

[6] 1) DISCARD "XOFF/XON

FROM

HOST"(O•OFF,1•0N)

2) CHARACTER

TO

HOST

(limited

to60cps/unlimited

9

10

6

GENERAL

BLOCK

DIAGRAM-

0

ES

CR

IP

TI

0 N

________

_

6.1

MICRO-PROCESSOR

CONTROL

UNIT

The

Facit

4431

terminal

is

based

upon

the

Z80A

Microprocessor.

The

principal function

is

to

decode each character

as

it

is

received (from

keyboard or host computer),

detect

characters

and

character sequences representing terminal

commands,

and

obey

these

commands.

The

micro-

processor also performs background tasks of

keyboard scanning,

character

and

cursor

blin-

king, bell generation, loading the

display

re-

fresh

RAM

starting

address

for

each of the

25

display

rows,

and

various other

real-time

functions.

The

microprocessor

controls

all

communication

on

the

CPU

bus, reading data

from

the

EPROMS,

EAROM,

display

refresh

RAM,

SIO,

and

the keyboard,

and

writing

to

the

dis-

play

refresh

RAM,

SIO,

CTC,

CRTC,

EAROM,

and

various hardware

latches.

A block diagram of the Microprocessor control

unit

is

shown

in Fig 6.1.

TO

OTHER

CIRCUITRY

~

TO

OTHER

{

CIRCUITRY

•

• 3

•

POWER

ON

RESET

NMI

FROM

(SG)

INT.

FROM

.---

(

I/O)

_t_

~

ZBO

A

.._

DATA

BUS

~

ADD

BUS

:-

CPU

CONTROL

4

..

D42

• •

_t_

CLOCK

• •

..

1-8

SCRATCHPAD

....

1-11

...

RAM

~

D72

2k

x 8

PROGRAM

8 •

...

PROMS

16

-

....

12

(24)k x 8

-

D73,74,75

•

WAIT

STATE

J

GENERATION

14-

MEM

SHARE

ADDRESS

~

Dl4,31,32

Dl7

D9

DECODING

&

CONTROL

ro

(KBD)

4---

D26,24,25,36,15,34,16

~

EAR

OM

~

EAR

OM

TO

(I

Io

4----------j

ET.

AL

D63

JJ

CONTROL

TO

(SG)

-.

LATCH

D65,64

TO

(VG)

4-

TO

M

4-

( )

FIG

6.1

MICROPROCESSOR

CONTROL

UNIT

6.2

DISPLAY

REFRESH

MEMORY

The

Display Refresh

Memory

stores

code

and

video

attribute

status

of

ter

to

be

diplayed

on

the screen.

4431

has

4k

(4096)

12

bit

words

of

mory

to provide 2 pages of

memory

MEM.

ADDRESS

FROM

MULTIPLEXOR

12

BANK

SEL

12

10

_..,

--

r------.

ASCII

RAM

4k

x 8

D51,52

ATTR

RAM

4k

x 4

the

ASCII

each chara-

The

Facit

display

me-

in the

80

14

..

D26

D68,69,67,66

FIG

6.2

6.3

SYNCHRONIZATION

GENERATOR

4

Figure

6.3

is

a block diagram

of

the

Sync

Gene-

rator

Circuits.

•

Z80

ADDRESS

BUS

•

Z80

DATA

BUS

CRT

REFRESH

CONTROLLER

..

4

12

-"'

ADDRESS

r

11

column

mode,

or 1 page of

memory

in the

132

column

mode.

Access to the

display

memory

by

the

CPU

(to

write

and

read data)

is

controlled

by

the

DISPLAY

ACCESS

HANDLER

circuitry.

A

block diagram of the Display Refresh

Memory

is

shown

in Fig

6.2.

TO

(VG)

•

18 •

TO

(VG)

•

1 4

4

_..

..

DISPLAY

MEMORY

ASCII

BUFFERS

D54,55

ATTR

BUFFER

D70,71,53

14

8

_..,

--

14

.,t_4

--

...

CPU

OATA

BUS

CPU

DATA

BUS

The

Sync

Generator

circuit

provides

all

timing

signals

required

to:

-"'

r

_,.,

r

COLUMN

ADDRESS

COUNTERS

12-"'

MULTIPLEXORS

8_..

r-

~

r

..

12

~

D49

i.._

D29,30

Dl2,ll

,28 Dl3,10,27

-t +

MEM

SHA

SCREEN

RE

CONTROL

i.._

-4

CHARACTER

RATE

CLOCK

D30

• •

NM!

GENERATION

80/132

OOT

MEMORY

FOR

SCROLLING

AND

COLUMN

______.

OSCILLATOR

SHARE

LOADING

ROW

ADDRESS

SELECT

SIGNAL

D23,8

GENERATION

FIG

6.3

SYNCHRONIZATION

GENERATOR

• address the

display

refresh

memory

to

ex-

tract

extract

characters

to

be

passed

on

to

the video generator

circuit.

•

indicate

to the video generator

circuit

the

presence of double

wide

and/or double high

character

rows.

12

• provide

shift

and

load

commands

to

the

video

shift

registers.

•

interrupt

the

Z80A

every

vertical

retrace,

and

every

10

horizontal scans to

request

row

start

information.

The

Sync

80

and

troll

er,

tor,

and

lexer.

CPU

DATA

BUS

CONTROL

FROM

(SG)

&

(P)

ASCII

DATA

FROM

(M)

ATTR

DATA

FROM

(M)

& (

SG

)

Generator

circuitry

consists

of the

132

column

dot

oscillators,

CRT

Con-

Interrupt

Generator,

MEMSHARE

Genera-

the Refresh Address Generator/Multip-

.L

•

SCAN

LINE

8 ..

COUNTER

&

CONTROL

..

D18,19,21

.

ASCII

LATCH

.

8 ..

D41

ATTR

LATCH

..

D46

CONTROL

FROM

(SG)

t---

4

__..

...

CHARACTER

8

__..

GENERATOR

...

D40

.

-'--

1 -

ATTR

!BUTE

5

GENERATOR

--'

r

SCREEN

AHR.CONTROL

FROM

(M)

&

(SG)

[)57

5

6.4

VIDEO

GENERATOR

The

Video

Generator

circuit

uses the outputs

of the

Sync

generator

and

the

display

memory

circuits

to

create

the

appropriate

video

sig-

nals

for

each

character

to

be

displayed.

The

ASCII

character

code

from

the

display

memory,

the scan

line

count,

and

the double high/doub-

le

wide

control

lines

are

combined

to generate

the address in the

character

generator

EPROM

where

the dot

pattern

for

the

character

to

be

displayed

is

stored.

The

dot

pattern

is

then

converted to

serial

form

by

the video

shift

registers

and

combined

with the

attribute

data

before geing sent to the monitor. A block

dia-

gram

of the

Video

Generator

is

shown

in

Fig

6.4.

Z80

A

DATA

BUS

P)

l

FROM

(

l

VIDEO

DIGITAL

SHIFT

BRIGHTNESS

..

CONTROL CONTROL

D22 D56

y

4

~

-·

VIDEO VIDEO

SHIFT

OUTPUT

SIGNAL

VIDEO

i--------

REGISTERS

SIGNAL

-

GENERATOR

i--.

COMPOS

!TE

VIDEO

OUTPUT

D39,38

~5

__....

D60,35,44

ATTR

5

LATCH

--'

t-

058

FIG

6.4

VIDEO

GENERATOR

6.5

INPUT/OUTPUT

INTERFACE

Figure 6.5

is

a block diagram of the Input/

Output

Interfaces.

Communication

between the

Facit

4431

and

the host computer

and

local

printer

is

through

bidirectional,

asynchronous

serial

V24/RS-232-C

ports.

A dual channel

SIO

(Serial

Input/output

controller)

performs the

parallel/serial

data conversion required

to

adapt

and

synchronize the terminals

internal

parallel

data

to

the

serial

format of the ex-

Z80

A ,

SID

-

4

048

--r

!--------,

.

~

4

Z80

A 8

UART

DATA

8

CLOCKS

BUS

.....

.

~

..

3

CONTROL

8 I

& .

-

ADDRESS

••

Z80A

CTC

f

13

CLOCK.

___.

COUNTER

..

02

050

5

--

..

13

ternal

devices.

Communications

parameters such

as

data

rate

,

parity,

and

word

lenght are se-

lected

by

the operator in the

SET-UP

MODE,

and

stored

from

one

session

to

the next in the

non-volatile

EAROM.

The

Z80A

CPU

reads these

parameters

from

the

EAROM

upon

power-up,

and

uses

this

data to configure the

SIO

and

the

baude

rate

clock generators.

TTL

TO

RS232C

LINE

DRIVERS

061

....

RS232C

i.-

TO

TTL

i.._

LINE

:

RECEIVERS

14-

062

__..

__:

--

.....

'-+

I/O

SER.

OUT

I/O

DTR

I/O

RTS

I/O

SER.

IN

I/O

DSR

I/O

CTS

I/O

PORT

P.

SER

OUT

}

PRINTER

P.

SER

IN

PORT

P.

ROY

--

INT

--

REQUEST

FIG

6.5

INPUT/OUTPUT,

PRINTER

INTERFACES

6.6

KEYBOARD

SYSTEM

The

keyboard

is

a seperate item connected to

the

display

unit

by

a

flexible

coiled cable.

To

simplify the connection, the keyboard enco-

ding

is

performed

on

the keyboard

itself

pro-

ducing a

serial

code

which

is

received

by

a

UART

on

the

Main

Logic board of the terminal.

The

keyboard logic

is

based

on

the

INTEL

8035

microprocessor using

2k

byte program.National

character

versions are jumper

selectable.

Key-

board encoding

is

done

using

an

encoder

ROM.

Depression of each encoded

key

or

key

combina-

tion

produces a unique

ROM

address,

and

in

each

ROM

location

is

the

code

for

associated

key

depression(s).

The

selected

code

is

then

transmitted

in

serial

form

to the keyboard

UART

in the display

unit.

A block diagram of

the

Keyboard

system

is

shown

in Fig

6.6.

SERIAL

MOD-

KEYS

STRAPS

8

SEL

2x8195

8

KEY

MATRIX

96

KEYS

IN

OUT-----;

STRAPS

2

FIG

6.6

KEYBOARD

XTAL

CPU

8035

ROM

8

2716 8

(2Kx8)

8

14

7

DETAILED

FUNCTIONAL

DESCRIPTION

_____________

_

1/0

PORTS

SET-UP

MODE

--------------

PRINTER

~.---1-/D-~

- - -

-1

EAR

OM

PROGRAM

ROM

(12k x 8)

SCREEN

MAP

RAM

VIDEO

ATT

(4k

x 4)

1/0

LOGIC

AND

SIO

~~M~~~

!

2k

t---------.----C_PU_Bu_s

____

~-----~

INTERFACE

IRAM

CHARACTER

GENERATOR

ROM

I

EXTENDED

STANDARD

1

(OPTIONAL)

DISPLAY

GENERATOR

SYNC

GEN'R_

KEYBOARD

UART

L

_________________

_ _

_____

_J

VIDEO

SYNC

SERIAL

ASCII

,-

-----

11--

---~LLAN~

I I I

~-~-~

KEYCLICKER

I

KEYBOARD

VIDEO

COMBINER

CIRCUIT

I I

LOGIC

AND

I I I

ENCODER

L

________

_JI

COMPOSITE

VIDEO

OUTPUT

I

;E\Y~~~~~x

KEYBOARD

LEDs

I I

L

_________

J

FIG

7. 1 Functional Block Diagram

7.1

MICRO-PROCESSOR

CONTROL

UNIT

Familiarity

with microprocessor terminology

and

procedures

is

necessary for understanding

this

section. Specific

knowledge

of the

Z80A

proces-

sor

is

desirable but not absolutely

essential.

The

Facit

4431

uses a

Z80A

microprocessor

(D42)

to control

all

terminal operations based

on

the

instructions

contained in the

program

EPROMs

(D73,74,75).

The

processor

has

access to

all

memory

and

I/0

mapped

devices

on

the bus, in-

cluding the

2k

scratchpad

RAM

(D72), the

Z80

SIO

(D48-DART-)and

CTC

(D50)

(see section

7.5),

the

EAROM

(D63), various hardware

latches,

and

under control of the

bus

arbitration

circuitry,

the display

refresh

RAM

(051,52)

and

the

attri-

bute

RAM

(D68,69,67

and

D66).

Address decoding

for

all

devices exept the pro-

gram

EPROMs

and

display refresh

memory

is

pro-

vided

by

D36

(write)

and

015

(read). Address

decoding

for

program

EPROMs

is

described in

section 7.1.3 ,

and

decoding

for

the display

refresh

RAM

is

described in section 7.2.

7.1.1

CPU

CLOCK

Crystal

B3

and

D9

(a

74LSOO

NANO

gate) are

used

to generate the

4MHz.,

50%

duty cycle system

clock signal

for

the microprocessor

and

the

other

Z80

family chips. Transistor

V101

provi-

des

an

active pull-up for the clock

by

taking

the

normal

TTL

level

(which

ranges

from

3.6 to

4

volts)

and

pulling

it

up

to

full

5

volts,

while maintaining the standard

TTL

rise

time.

(Z80

family chips other than the processor are

discussed in section 7.3 of

this

manual.)

7.1.2

POWER

ON

RESET

During

power

up

it

is

necessary to hold the

reset

pin of the

Z80

family chips

at

the logi-

cal 0 level

until

the 5 Volt

power

supply

is

stabilized

to insure

that

the microprocessor

begins executing

instructions

at address 0,

and

that

the

Z80

peripheral chips are

reset

to a

known

state.

After the 5 volt supply

has

stabi-

1ized,

this

reset

line

must

rize

cleanly.

The

reset

circuit

consisit

of

capacitor

C1

(22uF), charged through a

22k

resistor

(R24),

diode

V1,

and

D17.

The

votage across

C1

is

coupled

to

a noninverting

CMOS

gate

D17

through

a

12k

resistor

(R22).

The

output of gate

is

fed

back

to

the input through a

82k

resistor

(R23),

which

guarantees

that

the

circuit

will not

jit-

ter

when

passing the switching threshold

(which

is

approximately

half

the

power

supply voltage

for

CMOS).

Diode

V1

quickly discharges

C1

to

ensure

that

the processor will

go

through

its

reset

procedure

and

start

up

at

address 0 in

the event of a

brief

power

failure.

7.1.3

PROGRAM

MEMORY

ACCESS

The

design of Facit

4431

allows the use of

ei-

ther

2732

or

2764

EPROMs

for the

Z80

program

memory,

resulting

in a

maximum

of

24k

when

3

2764s

are used.

Program

memory

decoding

is

ac-

complished in

D17,

which

is

enabled

by

D34-11

(the

OR

of read

and

memory

request).

Address

line

A15

allows the processor to access

program

memory

when

low,

or to access the screen

re-

fresh

RAM

when

high.

7.1.4

SCREEN

ATTRIBUTE

LATCH

Octal

latch

D64

is

used to

write

data

and

control information to the

EAROM

(see section

7.1.5)

and

to

latch

data

that

controls the

dis-

play

attributes.

When

the screen saver

feature

is

enabled

and

approximately 9 minutes

have

elapsed without reception of data

from

either

the host or keyboard

D64-16

will

go

high

to

blank the display.

The

level of

D64-19

selects

either

80

or

132

column

mode

(low=80). Finnaly,

D64-2

is

used to

kill

interrupts

as

discussed

in the

Synch

Generator portion of

this

manual

(Section

7.4).

7.1.5.

EAROM

In

the

Facit

4431, operational

characteristics

which

are defined in

most

other terminals

by

switches or jumpers are

selected

in Set-Up

Mode

and

are saved

from

one

operating session

to

the

next in the

EAROM

D63.

The

EAROM

is

accessed

during power-up, terminal

reset,

and

when

a

Save

or Recall

Set-Up

Features operation

is

performed.

At

all

other times the

EAROM

is

in

the standby

mode

with pins 6, 7, 8,

and

9

at

12V

potentials.

All

data

and

control informa-

tion

from

the

CPU

is

latched in

D64

and

passes

through the

open

collector

gates of

D65,

which,

through the pull-up

resistors

of

R34,

provide

the additional

current

required

by

the

EAROM.

The

control

lines

D63-7,

8

and

9

select

the

read/write

address/data

modes

of the

EAROM.

The

EAROM

contains

one

hundred

14

bit

words

which

are accessed

serially

through pin 12.

During

any

EAROM

access operation (read,

erase,

or write) a

14KHz

clock signal appears

on

pin 6

and

control signals

on

pins 7, 8

and

9.

Due

to

the

critical

timing

constraints

of the

EAROM,

15

the

CPU

must

suspend

all

other operations while

generating the clock, data

and

control

signals.

To

insure

that

non-maskable

interrupts

are

dis-

abled, the

CPU

latches a high to

D64-2

for

the

duration of the

EAROM

access.

EAROM

read/write

operations access the

entire

device address

space

and

take about 2.5 seconds

for

a read

and

6.5 seconds for a

write.

The

data

last

written

to the device

is

retained

when

power

is

removed

Transistor

V105

guarantees

that

~he

-23 Volt

supply

is

removed

in sequence before

the

+12

volt

supply to

protect

the

EAROM

during power-

down.

7.2

DISPLAY

REFRESH

MEMORY

The

Facit

4431

was

designed to allow the pro-

cessor transparent access to the display

ref-

resh

memory

when

the display

is

not

active.

Without

this

means

of resolving

potential

con-

flicts

between

the

CPU

and

the

refresh

memory

circuitry,

both could attempt to access the

display refresh

RAM

during the active display

interval,

resulting

in

a chaotic display.

The

Display Access

Handle

circuitry

controls

CPU

access to the display

refresh

RAM

in the

follo-

wing

manner:

The

MEMSHARE

signal (see Section 7.4.3)

allo-

cates

one

half

of each character time to the

CPU

to access the display

memory

and

the other

half

to the refresh

circuitry.

If

the

CPU

attempts to access the display

refresh

memory

during the

refresh

portion of the

MEMSHARE

sig-

nal the Display Access Handler

circuitry

places

the processor in the wait

state

until

at

least

one

character position cycle

is

completed,

at

which

time the

MEMSHARE

signal will again

be

in

the

CPU

phase.

When

the

Z80

enters

the

WAIT

state,

it

holds the address, data

and

read or

write

lines

at

the active level

until

the

end

of the

WAIT

state,

at

which

time

it

completes

the read or write cycle.

7.2.1

WAIT

STATE

GENERATION

The

MREQ

signal

from

the processor

is

inverted

in

D31

and

ANDed

with the

MI

signal

so

that

the

output

at

D32-11

represents

an

attempt

by

the

processor to access

memory

other the the pro-

gram

EPROMs.

This signal

is

then

ANDed

with ad-

dress

line

A15

so

that

the output

at

D32-3

sig-

nifies

an

attempt

by

the

CPU

to access the

dis-

play

RAM.

This output

is

tied

to

D14-1,

which

takes

shift

register

D14

out of the load

state

so

that

the next

CPU

clock

on

D14-2

will cause

D14-9

to

go

low,

as

the

parallel

data

is

seri-

ally

shifted

out.

The

low

D14-9

goes

to

D32-5,

which

results

in

D32-6

going

low

and

placing

the

CPU

in

the

WAIT

state.

The

low

at

D14-9

al-

so

goes

to the D input of the

F/F

D31-12,

which

will

be

clocked with the next

rising

edge of

the

MEMSHARE

signal to appear

at

the Q output

D31-9.

This will force

D32-6

low

to ensure

that

the

CPU

remains in the

WAIT

state

until

the

CPU

portion of the

MEMSHARE

signal.

D14-9

will

re-

main

low

for

three

clock periods,

until

the da-

16

ta

loaded in to the D input

D14-14

appears

at

D14-9.

At

this

point

D14-9

and

D31-12

are high,

but the signal are

D32-6

will not

go

high

until

the next

rising

edge

of the

MEMSHARE

signal

clocks the data through

F/F

D31

to

D32-4.

This

synchronizes the

end

of the

WAIT

pulse with the

rising

edge

of

MEMSHARE,

which

is

the beginning

of the next

CPU

portion of the

character

time

cycle.

7.2.2

WRITING

TO

THE

ASCII

(Character)

DISPLAY

MEMORY

The

inputs to

D25

(RD

at

D25-15,

WR

at

D25-1,

the

AND

of

A15

and

MRQ

at

D25-13

and

D25-3,

and

A14

at

D25-14

and

D25-2)

are

used

to

deco-

de

reads

and

writes to

either

the

ASCII

(cha-

racter)

or

ATTR

(attribute)

display

memory.

Note

that

the write

ASCII

signal

from

D25-6

is

the only signal

from

D25

to

go

through

some

extra

gating before proceeding to the

memory

section.

This

was

done

to ensure

that

write

pulse

is

present only during a

specific

por-

tion

of the

CPU

part

of a

character

time.

As

the

WR

ASCII

signal

at

D25-6

goes

low,

which

is

coincident with the

WR

pulse

from

the

CPU

at

enable input

D25-1,

it

is

allowed through

D34

only

when

the

WAIT

signal

from

D32-6

is

present

at

D34-10.

This gate ensures

that

the

actual write to the display

memory

takes place

while the processor

is

in the

WAIT

state,

and

terminates synchronously with

end

of the

WAIT

state.

Remember

that

on

the

rising

edge of the

MEM-

SHARE

signal

(which

indicates

the

start

of the

CPU

portion of the character time) the address

multiplexers

to

the display

RAM

are switched

over to the

CPU

address

bus

from

the

refresh

circuit

column

counters.

Also

remember

that

the

OK

to Write signal (See section

7.4.3)

starts

low

about a

third

of the

way

into the

CPU

portion of

MEMSHARE,

and

terminates

as

the

MEMSHARE

signal

goes

low

at

start

of the

re-

fresh portion of the

character

time cycle.

Thus

the output

at

D34-6,

which

is

the

OR

of

OK

to Write

and

WR

ASCII,

ensures

that

the ad-

dress

from

the multiplexers will

have

had

a

chance to properly

settle

before the

write

pul

se

comes

along.

The

signal

from

D24-2

to

D54-

11

latches the data into

D54,

and

the output

at

D34-6

enables the output of the

latch.

The

signal

from

D34-6

also

goes

to the

write

enab-

le

inputs of the

ASCII

display

RAM

at

D51-21

and

D52-21

to

actually

write the data

into

the

RAM.

7.2.3

READING

THE

ASCII

(Character)

DISPLAY

MEMORY

When

the

CPU

attempts to read the display

me-

mory

it

will

be

placed in the

WAIT

state,

as

explained in section

7.2.2,

and

the address

and

read

lines

from

the processor will

be

held

in the

active

state.

At

the

start

of the pro-

cessor portion of the

character

time cycle the

rising

edge of the

MEMSHARE

signal will switch

the

display

RAM

address multiplexers

D27,

D10

and

D13

over to the

CPU

address bus,

and

at

the

end

of the

CPU

portion of the

character

time cycle the

rising

edge

of

MEH

SH

at

D55-11

will

latch

the data into

D55.

Since the

multi-

plexers

had

the

entire

CPU

portion of the cha-

racter

time cycle in

which

to

settle,

it

is

guaranteed

that

correct

data

was

latched

into

D55.

The

processor,

however,

will not

actually

read the data

from

the

latch

until

after

WAIT

state

ends,

which

occurs

on

the

rising

edge

of

MEMSHARE

at the

start

of the next

CPU

portion

of the character time cycle.

7.2.4

WRITING/READING

THE

ATTR

(Attribute)

DISPLAY

RAM

Once

again,

when

the processor attempts to ac-

cess the Display

Memory

it

will

be

placed in

the

WAIT

state

as

described in Section

7.2.1,

but the

attribute

data will

be

immediatly

latched into

D53

by

the

WR

ATTR

signal

from

D25-7

to

D53-11.

The

upper four

bits

of the

attribute

latch

D53

are

used

to

control

full

screen

attributes

and

are discussed in Section

7.3.3.

3.

The

lower four

bits

of the

CPU

data

bus,

DO-D3,

are latched

into

D53

to

set

the

video

attribute

of individual

characters.

As

it

is

ineffecient

to write

an

attribute

every

time a character

is

written,

the

write

enable

inputs

on

10

of

D68,

D69

and

D66

and

the

enable

line

of

tristate

octal buffer

D71

are

tied

to the

WR

ASCII

line

so

that

whenever

an

ASCII

character

is

written

into

D51

or

D52

the

attri

butes are automatically

written

into the

corresponding location in the

attribute

memo-

ry.

Thus

the

attribute

latch

D53

need

be

writ-

ten to only

when

an

attribute

change

is

desi-

red.

Reading the

attributes

is

done

through

D70

in

1a

manner

similar

to

that

for

reading

an

ASCII

character

from

the display

memory,

as

descri-

bed

in Section

7.2.3.

The

attribute

data

is

placed

on

the lower four

bits

of the

CPU

data

bus

when

RD

ATTR

signal

from

D25-9

to

D71-19

goes

low.

7.3

SYNCHRONIZATION

GENERATOR

7.3.1

CRT

CONTROLLER

(CRTC)

The

CRTC

D49,

allows

programming

of terminal

sync

characteristics

by

loading the

control-

ler's

internal

registers.

The

registers

which

controls

these parameters are addressed via

the address

lines

AO

through

A3

and

are loaded

via the

8-bit

wide

CPU

data bus.

The

CRTC

is

selected

for

loading

By

D36,

the

WRITE

decoder

in the Processor section using the addresses

3000-300F

Hex.

Data

in the

internal

registers

of the

CRTC

determines the

number

of display

rows

(24

data

rows

and

1

status

row), the

number

of

columns

(80

or 132), the

number

of scan

lines

per

dis-

play

row

(10).

The

number

of scan

lines

per

frame

is

altered

for

50

or

60

Hz.

After

initialization

of the

CRTC

on

power

up,

positive

horizontal

sync

pulses, with duration

of about 8 microseconds, will

be

visable

at

D49-15

every

64

microseconds.

Positive

verti-

cal

sync

pulses, with a duration of about

200

microseconds. appear

at

D49-11.

The

data

row

counter outputs

(DRO-DR4),

the character coun-

ter

outputs

(HO-H7),

and

the scan counter out-

puts

(RO-R3)

are generally not

used

for

dis-

playing the characters

on

the screen.

However,

some

of these signals are

used

in generating

the non-maskable

interrupt

at

the appropriate

time as described in Section

7.3.4.

7.3.2

DOT

OSCILLATOR

The

Dot

oscillator

D8,

provides timing

infor-

mation

for

the video portion of the Facit

4431

a

9.828MHz

oscillator

is

used

in

80

column

mode

and

a

14.976MHz

oscillator

in

132

column

mode.

The

appropriate

oscillator

is

enabled

by

D5-6,

whose

input

is

determined

by

the

MSB

of

data

word

written into the octal latch

74LS273

D64,(see Section 7.2.4 for

details

about wri-

ting

to

this

latch).

The

buffered output

at

D23-6,

is

the basic dot

clock

for

the video

section,

and

is

passed

as

the input to the

modulo

12

counter

D4.

Since

each character

is

six dots

wide

a

jam

pulse

is

caused

to

occur every

sixth

dot

by

ANDing

the

A (pin12)

and

C (pin9) outputs of the counter

in D33-9,10,

this

pulse

is

then

chopped

to

one

half

its

width

by

the dot clock in

D7

and

the

output

is

used

in the video generator section

for

single

and

double width character display.

Since in the double

wide

character

mode

this

pulse

is

required only every other character

position,

D7-11

is

inverted

by

D45

and

gated

with the

LSB

of the

column

counter

D28-14,

in

D7-9,10.

Thus,

at

D7-8,

we

have

a negative

going pulse

one

dot

wide

for

every

chararcter

position.

In

addition to the

selection

of the proper os-

cillator,

a change

between

132

and

80

chararc-

ters

per

row

requires a

different

set

of para-

meters

to

be

loaded into the

CRT

controller,

which

is

handled

by

the terminal firmware.

17

7.3.3

MEMORY

SHARE

SIGNAL

The

screen refresh

memory

is

accessed in a

transparent manner. This requires

that

one

half

of the character time

be

devoted to

CPU

access,

and

the other

half

to the

refresh

me-

mory

circuitry.

To

synchronize the various

events, a signal

called

"MEMSHARE",

(MEMSH

&

MEMSH(L)

on

schematic),is generated

which

acts

as

the basic character clock

for

the

CRTC.

One

cycle of

MEMSHARE

has

a duration of

six

dot

clock cycles

and

is

generated

as

the output of

D5-12,

which

is

the inverted

(A

and

B)

or C

signal of the

A,

B

and

C outputs of the

7492

counter

D4.

The

inverted

MEMSHARE

(MEMSH(L)

signal

at

D20-3

is

used

in reading the

ASCII

data

and

attributes

from

the display

memory.

The

rising

edge

of the

MEMESHARE

signal se-

lects

the address multiplexors

D27, D10,

and

D13

to enable the

CPU

to access

memory.

At

the

same

time

it

increments the

column

counters

D28,

D11

and

D12

in preparation

for

displaying

one

scan

line

of the next character

on

the

screen.

Since the

CPU

and

the

MEMSHARE

circuitry

are

operationg with

two

entirely

different

clocks,

any

attempt

by

the

CPU

to write

to

the display

memory

while the multiplexors are switching

over should

be

prevented.

For

this

reason a

signal

called

OK

TO

WRITE

(OK

WR)

is

generated

which

will

restrict

CPU

access

to

the

memory

to the proper time

intervals.

The

divide

by

2 output of the

modulo

12

coun-

ter

D4-12,

is

used

as

the clock signal

for

double

wide

characters

and

in generating the

OK

WR

signal.

The

OK

WR

signal

is

generated

as

the Q

NOT

output of the

F/F

D3.

When

this

signal

goes

low

it

allows the processor

to

write to the

RAM

memory.

The

MEMSHARE

signal keeps the

OK

WR

signal high during the refresh portion

by

keeping the

F/F

in

reset

state.

This

signifies

that

the display

RAM

is

inaccessible

by

the

CPU

during the refresh portion of the

MEMSHARE

signal.

When

the

MEMSHARE

goes

high indicating

CPU

access, the

OK

WR

goes

low

only

after

one

dot clock delay

(one

third

into the

CPU

por-

tion of

MEMSHARE).

This delay ensures

that

the

multiplexers will

have

enough

time to switch

over.

Note, Section 7.2.4 describes

how

this

signal

is

used

with the

CPU

for

writing into the

display

memory.

Fig 7.2

illustrate

the timing

signals

derived

in the

sync

generator

circuitry.

18

.---.--

---

·-.---.--.---.--.-----.---

l

I

C·

· · f f

~

a

~

-~

f "b -h·

90~

1 1

I

~-

v

~

µ

~

[JI

"'

~

P'

[A

_L

I

ar._.i

.. .

..

.

··~

.

..

-·

~A·

. .

...

..

·I/

\IV\

:..!:'...!.

J

~

r·

I~

..

I

f""i'wl

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-

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.

.,_

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..

---J..l.-+--.~.~--J~J.~-~---~~----+~----~r~.-A.~-~+~-~-~~~-~-~~

WQ·.

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.A,~-

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10-+--+--+-----+--+-----i--t--r---r-----i

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10

-+---+--+------i--t--t-----t---r---;---t

o~i'_·__._-_-

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_,__-·_·~~--~--·-·~--·~·---·~---~·

'·~

80

column

mode

132

column

mode

VERT:

2V/cm

HORIZ:

100ns/cm

FIG

7.2

DOT

OSCILLATOR,

MEM

SHARE,AND

7.3.4

NON-MASKABLE

INTERRUPT

To

make

the display

as

versatile

as

possible,

the processor updates the

row

start

address for

every character

row,

each

character

row

has

10

scan

lines,

and

consequently a

NON-MASKABLE

INTERRUPT

(NMI)

is

generated every

10

scan

lines.

If

smooth

scroll

is

selected,

and

a

scrolling

window

is

defined,

extra

NMis

may

be

required.

7.3.4.1

Non-smooth

scroll

or

full

screen win-

dow

The

vertical

sync

pulse

is

used

as

real time

reference in updating the display. Therefore,

upon

power-up, the processor looks

for

the ver-

tical

sync pulse,

which

is

read in through the

latch

D43.

Once

the Vertical sync pulse posi-

tion

is

established the processor will

be

ready

to process the

NMis.

To

avoid the

possibility

of the processor having to process the

NMI

before the

vertical

sync

is

established,

the

NMI

is

disabled

by

the signal

KILL

INT

at

D20-5

which

is

set

high

by

writing

to

the

EAROM

latch

D64.

When

the

vertical

sync

is

determined

this

signal

is

removed,

enabling the

NMI.

The

negative going

vertical

sync

pulse appears

at

D5-8.

It

is

ANDed

with the carry pulse

from

the scan

line

counter

D21-12

in

D7.

This ensu-

res

that

whenever

the

refresh

memory

is

scan-

ning the 10th scan

line

of

any

character

row,

the processor will

be

ready to update the

row

address,

and

also loads

D30

with information

about wheter the

row

needs to

be

blanked,

if

it

is

a double

wide

or high

row,

and

if

it

is

the

TOP

or

BOTTOM

half

of the

row.

Incidentally,

this

also loads information about the

extra

interrupt

used

in case of

smooth

scroll

which

is

described in Section

7.3.4.2.

The

column

counters are loaded with the

row

ad-

dress values

whenever

the

Blank

signal

from

the

CRTC

is

active,

which

indicates

the screen

is

in the

retrace

period. This

resets

the

column

counters to address of the

first

character

po-

sition

on

the

row

for

every scan

line

and

the

column

counters count

up

to the

last

column

on

the

line.

When

the

register

D30

is

loaded with

four

bits

of information

from

the data bus, the

other four

bits

are

used

to

load the scan

line

count into the

74LS192

(D21)

in the

Video

Gene-

rator

section.

In

the case of

non-smooth

scroll

this

will always

be

zero.

The

new

row

start

address

is

written

during the

horizontal blanking period

which

guarantees

that

the screen will not

be

disturbed.

When

the

processor, under software

control,

has

set

up

the address

and

data information

for

D29,

D30

and

D21,

a

WRITE

operation

is

attempted.

At

this

point the

74LS138

(D2), enables the output

pin 9 thus

resetting

the

F/F

D31

which

in turn

causes

D32-6

to

go

low

and

place the processor

in a

WAIT

state.

The

WAIT

state

ensures

that

the address

and

data

lines

will

have

had

time

to

settle,

and

that

the

new

row

start

address

is

not written before the horizontal blanking

interval

at

the

end

of scan

line

10.

19

The

WRITE

pulse appears

at

D36-9,

and

after

buffering in

D24

is

gated with the

BLANK

signal

delayed

by

two

character times in D23-9,10.

It

then

emerges

at

D23-8

as

the

write

pulse

that

strobes the scan

line

counter

D21-11,

and

the

registers

D30-11

and

D29-11

latching the

new

scan

line

count

and

the

row

start

address.

The

horizontal blanking pulse

is

generated

at

D49-

17

as

a

positive

going

BLANK

SIGNAL

and

is

latched into the octal latch

D46-17,

by

the

character

rate

clock

MEMSHARE

signal.

The

out-

put of the latch

D46-16

is

the

BLANK

signal

delayed

by

one

character time

and

is

gated with

the

BLANK

signal

at

D22-1,2

to load the

column

counters

D12,

D11,

and

D28

in the sync. genera-

tor

circuitry

with the

new

row

start

address.

The

BLANK

pulse delayed

by

one

character time,

is

also

used

as

an

input

to

the octal latch

D46

-17 to generate a

BLANK

signal

that

is

delayed

by

two

character times

at

D46-19.

This signal

is

used

to

gate the write pulse

at

D23-9

and

also to disable the

line

decoder

D16.

Thus

the

output

D16-9

will

go

high

and

remove

the

reset

from

F/F

D31,

and

the

rising

edge

of the next

MEMSHARE

pulse will terminate the

WAIT

state.

Figure 7.3

shows

the various

BLANK

signals,

the write

row

start

register

signal

and

the

load

column

counter

signal.

D49-17

BLANK

DELAYED

BY

ONE

CHAR.

POSITION

D23-3

PARALLEL

LOAD

COL.

COUNTERS.

D46-19

BLANK

DELAYED

BY

TWO

CHAR.

POSITIONS.

D23-8

WRITE

TO

ROW

START

LATCHES

&

SCAN

LINE

COUNTER

L

.____

__

J

CLK

TO

D21-5

~

u:,

I I

..

u

D23-8

t

RELEASE

TIME

DEPENDS

ON

WHEN

THE

PROCESSOR

RESPONDS

TO

WAIT

STATE

BEING

TAKEN

AWAY

WHICH

IS

SYNCHRONIZED

WITH

MEMSHARE

SIGNAL.

FIG

7.3

SIGNALS

GENERATED

DURING

BLANKING

20

7.3.4.2

Smooth

scroll

or

scrolling

window

The

Facit

4431

has

two

smooth

scrolling

speeds,

fast

and

slow.

In

a

slow

smooth

scrolling

ope-

ration

the character

rows

within the

scrolling

window

are

shifted

upwards

or

downwards

by

one

scan

line

once

during every

refresh

cycle.

(A

refresh

cycle

is

the period

from

one

vertical

sync

pulse to the next.)

In

fast

smooth

scroll

the

character

rows

are

shifted

by

two

scan

lines

during each refresh cycle.

If

the opera-

tor

has

not

explicitly

defined a

scrolling

win-

dow,

then the

entire

screen

is,

in

effect,

a

scrolling

window.

In

the

first

screen

refresh

cycle of

as

smooth

scroll

operation the

first

scan

line

of the

scrolling

window

will display the data

from

the

second

line

of the

chararcter

row

(slow speed).

Recall

that

the scan

line

counter

D21

generats

an

NMI

during the 10th scan

line

of each cha-

racter

row,

and

that

this

interrupt

allows the

CPU

to

set

the scan

line

count

and

row

start

address of the next character

row.

Thus,

at

the

start

of the

scrolling

window,

the processor

sets

the scan

line

counter

D21

to

display

the

second scan

line

of the character

row.

Since the scan

line

counter

D21

only generates

a

carry

on

the 10th scan

line

of each charac-

ter,

and

the

last

scan

line

of the

scrolling

window

is

now

the

first

scan

line

of a

new

cha-

racter

row,

it

is

necessary to generate

an

extra

nonmaskable

interrupt.

This

extra

inter-

rupt

is

needed

so

that

the

CPU

can

set

the

row

start

address

and

scan

line

count of the

first

character

row

below

the

scrolling

window.

Since

the scan

line

counter outputs of the

CRT

Con-

troller

are referenced to the

start

of the

screen

and

not the

start

of the

scrolling

win-

dow,

they are

used

to decode the

end

of the

window.

Thus, the

CRTC

scan

line

outputs

at

D49

-4,8

are

ANDed

in

D6-12,13

to decode scan

line

10,

and

the output

at

D6-11

is

ANDed

with the

extra

interrupt

enable signal

at

D6-1,2

so

that

the output

at

D6-3

will generate the

extra

NMI.

(The

extra

interrupt

enable signal

comes

from

D30-19,

and

is

set

by

the processor

when

smooth

scroll

is

enabled.)

The

Q outputs of the

F/F

D3

controls

whether or

not

interrupts

are

let

through to the proces-

sor.

Since the

vertical

sync

pulse

must

always

be

allowed to generate

NMI,

the

vertical

sync

pulse

presets

F/F

D3.

As

interrupts

from

the

scan

line

counter

would

normally occur

at

the

very beginning of a scan

line,

the processor

would

be

forced to waste a

relatively

long time

in the

WAIT

state.

To

improve

efficiency,

the-

refore,

F/F

D3

is

used

to delay the

interrupt

towards the

end

of the scan

line.

The

F/F

is

set

to enable the

interrupts

when

the

column

count reaches

64

if

80

column

mode

and

96

if

in

132

column

mode.

When

in

80

column

mode

D17-13

is

high

and

the

column

count of

64

from

D49-32

passes through

D34-2

to clock the F/F.

When

in

132

column

mode

D17-13

is

low,

disabling the

D17-11

from

cloc-

king the F/F.

When

the

column

count reaches 96,

D17-8,9 gate a high

at

D17-10

which

clocks the

F/F

D3.

Note

the the

F/F

is

reset

by

the twice

delayed blank

signal.

7.4

VIDEO

GENERATOR

The

Video

Generator

(VG)

circuit

receives

paral-

lel

data

from

the

memory

(M)

and

the

Sync

gene-

rator

(SG)

circuits

and

generates both a

compo-

site

video output signal to drive

an

external

monitor (optional

features)

and

a

direct

drive

signal to drive the

internal

12"

(diagonal) data

display monitor.

7.4 1

CHARACTER

FONT

The

display

may

be

sectioned into

24

rows

of

either

80

or

132

columns

of basic

character

cells

and

a 25th

status

row

of

either

80

or

132

character

cells.

The

basic

cell

is

illustrated

below

in Fig 7.4.

•

1r

•

]~

•

l (

_[

FIG

7.4

BASIC

CHARACTER

CELL

AND

EIGHT

INDEPEN-

DENT

DOT

LOCATIONS

The

basic

cell

is

six dots

wide

by

ten dots

high. There are

eight

horizontal

positions

where

dots

may

be

placed.

Note

that

three of these

eight

positions

lie

on

half-dot

boundaries

and

the rightmost position extends for

two

dot

widths into

column

0 of the next

cell

to the

right.

Columns

4

and

5 are normally blank to

allow horizontal spacing

between

characters,

but

as

will

be

seen

later,

these

columns

may

be

fil-

led

if

continuous horizontal

lines

are to

be

drawn.

Rows

8

and

9 are

used

to display decen-

ding lower case or underlined characters

and

the

line

cursor.

Eleven

bits

are required to address the charac-

ter

(seven

ASCII

data

bits

and

four

bits

for

the

character

scan

line

0-9) to

be

displayed.

The

octal latches

D41

and

D46

provide the seven

ASC-

II

code

bits

and

multiplexer

D18

provides the

four scan

line

number

bits.

These

address

lines

to the character generator

ROM

are

summarized

in

table

below.

Facit 4431 Original operating manual

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