FALCOM JP14-R-LP User manual

THIS DOCUMENT IS AVAILABLE AT HTTP://WWW.FALCOM.DE/
JP14-R-LP & JP14-Q-LP
GPS-Receivers
Lead-free products
Hardware description
Version 1.0.0; Cre ted: Mond y 25 Febru ry 2008

JP14-R-LP & JP14-Q-LP FALCOM GPS RECEIVERS VERSION 1.0.0
T ble of contents
1 INTRODUCTION ........................................................................6
1.1 General ................................................................................................................6
1.2 Used abbreviations ..............................................................................................7
1. Related documents ..............................................................................................8
2 SECURITY .................................................................................9
2.1 General information ..............................................................................................9
2.2 Restricted use ......................................................................................................9
2. Children ................................................................................................................9
2.4 Operation/antenna ...............................................................................................9
2.5 Electrostatic Discharge (ESD) ..............................................................................9
3 SAFETY STANDARDS ............................................................10
4 TECHNICAL DATA ..................................................................11
4.1 FEATURES ........................................................................................................11
5 TECHNICAL DESCRIPTION ...................................................12
5.1 Receiver Architecture .........................................................................................12
5.2 Product applications ...........................................................................................1
5. Technical specifications .....................................................................................1
5. .1 Electrical Characteristics ...............................................................................................1
5. .1.1 General .........................................................................................................................................1
5. .1.2 Accuracy .......................................................................................................................................1
5. .1. DGPS Accuracy ............................................................................................................................1
5. .1.4 Datum ...........................................................................................................................................1
5. .1.5 Time to First Position ....................................................................................................................1
5. .1.6 Sensitivity * ...................................................................................................................................14
5. .1.7 Dynamic Conditions .....................................................................................................................14
5. .1.8 DC Power .....................................................................................................................................14
5. .1.9 Serial Port .....................................................................................................................................14
5. .1.10 Time – 1PPS Pulse ....................................................................................................................14
5.4 Power management modes overview ...............................................................15
5.4.1 Normal Operation mode ...............................................................................................15
5.4.2 Adaptive TricklePower mode (ATP) ...............................................................................15
5.4. Push-to-Fix Mode .........................................................................................................16
5.4.4 NMEA input message for ATP & PTF Mode ..................................................................17
6 HARDWARE INTERFACE AND CONFI URATION SI NALS
.................................................................................................19
6.1 Interfaces (balls assignment) of the JP14-R-LP .................................................19
6.2 Interfaces (balls assignment) of the JP14-Q-LP .................................................20
6. Configuration and timing signals ........................................................................21
6.4 Serial communication signals .............................................................................21
6.5 DC input signals .................................................................................................22
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JP14-R-LP & JP14-Q-LP FALCOM GPS RECEIVERS VERSION 1.0.0
7 SOFTWARE INTERFACE .......................................................23
7.1 SiRF binary data message .................................................................................2
7.2 NMEA data message .........................................................................................24
7.2.1 NMEA output messages ................................................................................................24
7.2.2 NMEA input messages ..................................................................................................24
7.2. Transport Message ........................................................................................................25
8 MECHANICAL DRAW .............................................................26
9 LAYOUT RECOMMENDATION ...............................................29
9.1 Ground planes ....................................................................................................29
9.2 RF connection ....................................................................................................29
9. Soldering profile ................................................................................................. 0
10 FIRST STEPS TO MAKE IT WORK ......................................31
11 APPENDIX .............................................................................33
11.1 How to set the target GPS receiver into power saving modes? ........................
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JP14-R-LP & JP14-Q-LP FALCOM GPS RECEIVERS VERSION 1.0.0
Version history:
This table provides a summary of the document revisions.
Version Author Changes Release date
1.0.0 F. Beqiri Initial version 25/02/2008
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JP14-R-LP & JP14-Q-LP FALCOM GPS RECEIVERS VERSION 1.0.0
C utions
Information furnished herein by FALCOM is believed to be accurate and reliable.
However no responsibility is assumed for its use. Please read carefully the safety
precautions.
If you have any technical questions regarding this document or the product
described in it please contact your vendor.
General information about FALCOM and its range of products are available at the
following Internet address: http://www.falcom.de/
Tr dem rks
Some mentioned products are registered trademarks of their respective companies.
Copyright
This document is copyrighted by FALCOM WIRELESS COMMUNICATIONS mbH with all
rights reserved. No part of this documentation may be produced in any form without
the prior written permission of FALCOM WIRELESS COMMUNICATIONS mbH.
FALCOM WIRELESS COMMUNICATIONS GmbH.
No patent liability is assumed with respect to the use of the information contained
herein.
Note
Specifications and information given in this document are subject to change by
FALCOM without notice.
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JP14-R-LP & JP14-Q-LP FALCOM GPS RECEIVERS VERSION 1.0.0
1 INTRODUCTION
This documentation is relating to the following FALCOM products: JP14-R-LP and
JP14-Q-LP.
1.1 General
Both products are new of highly integrated low-power GPS products – based on a
0.13 micron CMOS process of the SiRFstarIII (GSC3fLP – architecture) - coming with
single-board solutions and increased to 20 parallel channel receiver. Both units for
the first time combine a complete A-GPS digital baseband processor RF front end
and 4 megabits of flash memory in a single 10 mm x 24 mm package providing
manufacturers of cell phones PDAs and other portable and wireless devices with a
drop-in AGPS solution they can use to deliver real-time location and navigation
capabilities in a simpler smaller design with extended battery life.
Both units will deliver exceptional sensitivity low power consumption and extremely
fast time to first fix (TTFF) in a compact 40-pin BGA packages. The digital section of
both GPS receivers includes a powerful SiRFstarIII-LP core GPS signal processor that
handles all the time critical and low latency acquisition tracking and reacquisition
tasks autonomously and a 50-MHz ARM7TDMI processor. All units with the equivalent
of more than 200 000 correlators used for processing signals enable extremely fast
and deep GPS signal search capabilities; achieving time-to-first-fix in only seconds;
resulting a significant improvement on the GPS performance. They come with an
integrated 4-megabit flash memory and 1-megabit SRAM memory eliminating the
need for an external flash component and significantly simplifying the routing
associated with integrating a GPS receiver into a board design.
Units delivers major advancements in GPS performance accuracy integration
computing power and flexibility. Each unit has an integrated temperature
compensated crystal oscillator (TCXO). Due to the higher stability of frequency they
offer a high-improved GPS performance. In addition higher sensitivity allows them
more flexibility on their design the placement of the antenna and the selection of
the kind of antenna. Both modules continuously track all in view satellites thus
providing accurate satellite position data. The physical interface to both units
application is made through the provided balls. It is required for controlling the unit
receiving GPS location data transferring data and providing power supply line. All
units incorporate 4 megabits of flash memory required for storing the GPS software
and user application programs and 1 megabit of static RAM.
Compared to the JP14-Q-LP the JP14-R-LP is more optimized for location
applications requiring high performance in a very smaller form factor – just 10 x 24
mm package ideal for devices with limited on-board processing power. While the
JP14-Q-LP comes more smaller than JP14-R-LP just 15 x 17 mm package.
The concept architecture for both units builds perfect basis for the design of high-
sensitive low-power compact and cost efficient state-of-the-art GPS enabled
system solutions for target platforms such as mobile phones automotive systems
portable computing devices and embedded consumer devices. Both units are also
designed to be entire products such as AVL tracking unit handheld GPS.
The core of the units is comprised of the GSC3fLP that comes with Digital and RF in a
single chip and the GSW3 software stored into the on-chip 4-megabit FLASH that is
API compatible with previous GSW2 software.
The internal GSW3 software completes the package providing flexible system
architecture for standalone GPS based products.
Please consult SiRF (www.sirf.com) for special information about the GSC3f SiRFstarIII
chipset.
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JP14-R-LP & JP14-Q-LP FALCOM GPS RECEIVERS VERSION 1.0.0
Figure 1: The FALCOM JP14-R GPS receiver (top and bottom view)
Figure 2: The FALCOMJP14-Q GPS receiver (top and bottom view)
Users are advised to proceed quickly to the chapter "Security" and read the hints
carefully to secure its optimal use.
1.2 Used abbreviations
Abbreviation Description
A-GPS Assisted - Global Positioning System
BGA Ball Grid Array
DGPS Differential GPS
DOP Dilution of Precision
GPS Global Positioning System
GGA GPS Fixed Data
LNA Low Noise Amplifier
NMEA National Maritime Electronics Association
PRN Pseudo - Random Noise Number – The Identity of GPS satellites
RF Radio Frequency
RP Receive Protocol
RTC Real Time Clock
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JP14-R-LP & JP14-Q-LP FALCOM GPS RECEIVERS VERSION 1.0.0
Abbreviation Description
RTCM Radio Technical Commission for Maritime Services
SDI Data input
SDO Data output
SA Selective Availability
WAAS Wide Area Augmentation System
MSK Minimum Shift Keying
PCB Printed Circuit Board
PRN Pseudo-random noise
IF Intermediate Frequency
A/D Analog/Digital
1.3 Related documents
[1.] SiRF binary and NMEA protocol specification;
www.falcom.de│Support│Documentation│Sirf│ SiRFmessages_SSIII.zip
[2.] SiRF-demo software and manual;
www.falcom.de│Support│Documentation│Sirf│ SiRFdemo.pdf
www.falcom.de│Support│Software & Tools│Sirf│ SiRFdemo.zip
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JP14-R-LP & JP14-Q-LP FALCOM GPS RECEIVERS VERSION 1.0.0
2 SECURIT
This chapter contains important information for the safe and reliable use of the GPS
receiver. Please read this chapter carefully before starting to use the GPS receiver.
2.1 General information
The Global Positioning System uses satellite navigation an entirely new concept in
navigation. GPS has become established in many areas for example in civil aviation
or deep-sea shipping. It is making deep inroads in vehicle manufacturing and before
long everyone of us will use it this way or another.
The GPS system is operated by the government of the United States of America
which also has sole responsibility for the accuracy and maintenance of the system.
The system is constantly being improved and may entail modifications effecting the
accuracy and performance of the GPS equipment.
2.2 Restricted use
Certain restrictions on the use of the GPS receiver may have to be observed on
board a plane in hospitals public places or government institutions laboratories etc.
Follow these instructions.
2.3 Children
Do not allow children to play with the GPS receiver. It is not a toy and children could
hurt themselves or others. The GPS receiver consists of many small parts which can
come loose and could be swallowed by small children. Thoughtless handling can
damage the GPS receiver.
2.4 Operation/antenna
Operate the GPS receiver with an antenna connected to it and with no obstruction
between the receiver and the satellite.
Make absolutely sure that the antenna socket or antenna cable is not shorted as this
would render the GPS receiver disfunctional.
Do not use the receiver with a damaged antenna. Replace a damaged antenna
without delay. Use only a manufacturer-approved antenna. Use only the supplied or
an approved antenna with your GPS receiver. Antennas from other manufacturers
which are not authorized by the supplier can damage the GPS receiver.
Technical modifications and additions may contravene local radio-frequency
emission regulations or invalidate the type approval.
Authorized GPS antennas: FAL-ANT-3 (active antenna)
2.5 Electrostatic Discharge (ESD)
These GPS receivers contain class 1 devices. The following Electrostatic Discharge
(ESD) precautions are recommended:
-Protective outer garments.
-Handle device in ESD safeguarded work area.
-Transport device in ESD shielded containers.
-Monitor and test all ESD protection equipment.
-Treat the GPS receivers as extremely sensitive to ESD.
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JP14-R-LP & JP14-Q-LP FALCOM GPS RECEIVERS VERSION 1.0.0
3 SAFET STANDARDS
The GPS receiver meets the safety standards for RF receivers and the standards and
recommendations for the protection of public exposure to RF electromagnetic
energy established by government bodies and professional organizations such as
directives of the European Community Directorate General V in matters of radio
frequency electromagnetic energy.
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JP14-R-LP & JP14-Q-LP FALCOM GPS RECEIVERS VERSION 1.0.0
4 TECHNICAL DATA
4.1 FEATURES
-OEM single board 20 channel GPS receiver
-Size: JP14-R-LP: 10.2 x 24.5 x mm (B x L x H)
JP14-Q-LP: 15.7 x 17. x mm (B x L x H)
-Weight: JP14-R-LP: 1.5 g (without shielding)
JP14-Q-LP: 1.2 g (without shielding)
-Casing: Fully shielded
-TCXO: ± 0.5 ppm
-FLASH Memory: on-chip 4 Mbit FLASH and 1 Mbit SRAM.
-Operating voltage: +3.3 V DC ±5 %
-Power consumption: 140 mW (continuous mode)
-Power management: Adaptive TricklePower™ (ATP)*
Push-to-Fix (PTF)*
* For more details see chapter 5.4.
-Temperature range: -40 to +85 °C (operation transportation and
storage).
-Protocol: SDI1/ SDO1 ** :
NMEA 38400 baud Msg.: GLL GGA RMC GSV
GSA VTG
8 data bits no parity 1 stop bit
** All options related to this serial port are available
upon request.
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JP14-R-LP & JP14-Q-LP FALCOM GPS RECEIVERS VERSION 1.0.0
5 TECHNICAL DESCRIPTION
5.1 Receiver Architecture
The JP14-R-LP/Q-LP OEM GPS receivers from FALCOM are new OEM GPS receiver
products that feature the SiRFstarIII single chipset. The core of these units is
comprised of the GSC3LP that includes the Digital and RF in a single chip. All units
are built around re-configurable high-output segmented matched filter in
conjunction with a FFT processor which can search all 1023 chips of the GPS code
simultaneously over a wide frequency range for fast initial acquisition with large
uncertainties. The flexibility of the core allows the core processing engine and
memory to be reconfigured to track more than 20 satellites using the same
hardware. This flexibility make the JP14-R-LP/Q-LP highly efficient engines for wide
variety of location applications. The core of JP14-R-LP/Q-LP contains a built in
sequencer which handles all the high-rate interrupts for GPS and SBAS (WAAS
EGNOS) tracking and acquisitions. After initialization the receiver handles all the time
critical and low latency acquisition tracking and reacquisition tasks of GPS and SBAS
autonomously. The on-chip SRAM size is 1-Mbit (32Kx32) memory that can be used
for either instructions or data. The SRAM is designed for a combination of low power
and high speed and can support single cycle reads for all bus speeds. In many
applications the 4 Mbit FLASH completely eliminates the need for external data
memory.
Figure 3: Architecture of the JP14-R-LP/Q-LP GPS receivers.
Figure 3 above shows the block diagram of the JP14-R-LP/Q-LP architecture.
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JP14-R-LP & JP14-Q-LP FALCOM GPS RECEIVERS VERSION 1.0.0
5.2 Product applications
-Handheld GPS receiver applications
-Automotive applications
-Marine navigation applications
-Aviation applications
-Timing applications
5.3 Technical specifications
5.3.1 Electrical Characteristics
5.3.1.1 General
Frequency L1 1575.42 MHz
C/A code 1.023 MHz chip rate
Channels 20
Max. update rate 1 Hz
Processor speed 6 12.5 25 and 49 MHz
Data bus 16 bit
5.3.1.2 Accuracy
Position Autonomous: 10 meters CEP without SA
SBAS: < 5 meter
Velocity 0.1 meters/second without SA
Time 1 microsecond synchronized to GPS time
5.3.1.3 DGPS Accuracy
Position 1 to 5 meters typical
Velocity 0.05 meters/second typical
5.3.1.4 Datum
WGS-84
5.3.1.5 Time to First Position
GSM < 20 sec. average
3G < 20 sec. average
CDMA < 16 sec. average
Hot start < 18 sec. average
Hot start (open sky) < 1 sec. average
Cold start < 42 sec. average
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JP14-R-LP & JP14-Q-LP FALCOM GPS RECEIVERS VERSION 1.0.0
5.3.1.6 Sensitivity *
GSM 15 dBHz**
3G 15 dBHz**
CDMA 15 dBHz**
Tracking 13 dBHz
Hot Start 15 dBHz
Cold Start 30 dBHz
* The sensitivity value is specified at the correlator. On a JP14 Receivers using GSW3 fir ware
with the supplied antenna, 17 dBHz is equivalent to -155 dB . Other board and antenna
characteristics will vary.
** With SiRFLock fir ware.
5.3.1.7 Dynamic Con itions
Altitude 18 000 meters (60 000 feet) max.
Velocity <515 meters/second (1000 knots) max.
Acceleration 4 g max.
Jerk 20 meters/second³ max.
5.3.1.8 DC Power
Main power + 3.3 V DC ±5 %
Core power +1.5 V DC
Continuous mode approx. 45 mA at 3.3 V DC (with an active
antenna “FAL-ANT-3“)
Backup battery power +3 V DC ±5%
5.3.1.9 Serial Port
Electrical interface full duplex serial communication CMOS level.
Protocol messages SiRF binary and NMEA-0183 with a baud
rate selection.
SiRF binary – position velocity altitude status
and control NMEA – GGA GLL GSA GSV
RMC VTG
5.3.1.10 Time – 1PPS Pulse
Level CMOS
Pulse duration 1.5 µs
Time reference At the pulse positive edge
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JP14-R-LP & JP14-Q-LP FALCOM GPS RECEIVERS VERSION 1.0.0
5.4 Power management modes overview
There are three basic operating modes in which the JP14 family operates during use.
Each mode is used to accomplish a different task during the process of acquiring
and maintaining the GPS information. The JP14 family include all the functionality
necessary to implement the three different modes of operation. By default the JP14
family runs in normal mode (continuous mode). All three different operating modes
are described below. Additionally two of them such as Adaptive TricklePower™
(ATP) and Push-to-Fix (PTF) are designed as power saving modes.
5.4.1 Normal Operation mode
In this default implementation of normal mode the JP14 family is fully powered and
performs the function of signal search acquisition measurement and satellite
tracking. The amount of time spent in the initial full power is dependent on the start
conditions such as the number of satellites for which the ephemeris data must be
collected and the time to calibrate the RTC. When the JP3 family has been locked-
on to at least four satellites the receiver is able to calculate its current positions. In
this mode the JP14 family is fully powered and satellite searching initial acquisition
initial position calculation and tracking measurement functions are always
performed. In order to reduce the start up time of the receiver it is preferable to
connect externally a backup battery so that the RTC is running during the power
interrupt. The backup power is required for retention of SRAM memory and
maintaining the Real-Time-Clock. The validity of data stored in SRAM is kept due to
RTC keeps running and these data will be needed on the next power up scenario.
5.4.2 Adaptive TricklePower mode (ATP)
Adaptive TricklePower (ATP) is a variant of TricklePower ™. But only ATP and Push-To-
Fix (PTF is described in next chapter) modes are supported on JP14 family. ATP is best
suited for applications where regular updates are required and where stronger
signal levels are expected. The transition of receiver into the ATP mode can be done
and configured by using either the Action│Set Low Power (Trickle Power) …
command available in SiRFDemo evaluation software or the input command
described in chapter 5.4.4 on page 17.
When ATP is enabled the receiver will maximize the navigation performance.
Depending on different states of the power management circuits the receiver
belongs to one of three system states:
Full Power State (Acquisition/Tracking modes)
After initial turn on or system reset the JP14 will remain in the full power state until
a series of Kalman filter navigation solution is obtained all ephemeris data is
collected and the RTC is calibrated before transitioning to CPU-state. The receiver
stays in full power state until a position solution is made and estimated to be
reliable. In this state all RF circuitry and the baseband are fully powered. Even in
this state there is a difference in power consumption during acquisition mode
and tracking mode. During the acquisition mode processing is more intense thus
consuming more power (Diagram is shown below that is simplified for ease of
understanding. Timing values are only examples).
CP -State
In this state the LNA in the RF section is shut off. The TCXO and fractional
synthesizer from the RF section are still powered in order to provide a clock to the
CPU. This state is entered when the satellite measurements have been collected
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JP14-R-LP & JP14-Q-LP FALCOM GPS RECEIVERS VERSION 1.0.0
but the navigation solution still needs to be computed thus consuming power is
less than in the full power state.
Standby state
In the standby state power remains applied to the JP14 family but the RF section
is completely powered off and the clock to the baseband is stopped. About 600
µA of current is drawn in this state for the internal core regulator RTC and battery-
backed RAM. The receiver enters this state when a position fix has been
computed and reported. Typically before shutting down the RTC wakeup register
is programmed to wake up the system sometime in the future.
Remark: The environment temperature may also affect the power consumption in the Standby state.
Figure 4: Three system states into the ATP mode.
The transition from Standby state back to the full power is generated through the
internal RTC which transmits a wake up signal to the GPS engine to switch it on. The
JP14 is woken up and begins to acquire the on view satellites and to collect their
data. Under normal tracking conditions the receiver is set for a specific update
period (range from 1 to 10 seconds) and a specific sampling time during each
period (range from 200 to 900 ms). The receiver turns to full power state for the
sampling time to collect data and then operates in Standby state for the remainder
of the update period. The next full-power state is initiated by an RTC wakeup. But in
harsh tracking environments the receiver automatically switches to full power state
to improve navigation performance. When the satellites are sorted according their
signal strength the fourth satellite determines if the transition will occur or not. The
threshold is 26 dB-Hz. When tracking conditions return to normal (four or more
satellites with C/No of 30 dB-Hz or higher) the receiver switches back to the power
saving mode.
5.4.3 Push-to-Fix Mode
The Push-to-Fix mode puts the FALCOM JP14 family into a background duty cycle
which provides a periodic refresh of position receiver time ephemeris data and RTC
calibration every 10 seconds to 2 hours. The transition of receiver into the Push-to-Fix
mode can be implemented and configured by using either the Action│Set Low
Power (Trickle Power) … command available in SiRFDemo evaluation software or
the input command described in chapter 5.4.4 on page 17.
The PTF period is 30 minutes by default but can be anywhere between 10 seconds
and 2 hours. When the PTF mode is enabled due to a new PTF cycle the receiver
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JP14-R-LP & JP14-Q-LP FALCOM GPS RECEIVERS VERSION 1.0.0
will stay on full power until the good navigation solution is computed. The so-called
hibernate state will follow for the remainder of the period. For example if the
receiver took 15 seconds to fix position and refresh ephemeris on the default period
of 30 minutes the receiver will sleep for the 29 minutes and 45 seconds. Whenever
the receiver wakes up it collects almanac and ephemeris data and then goes back
to the previous sleep phase again.
Remark: The environment temperature may also affect the power consumption in the Hibernate state.
Figure 5: Three system states in the PTF mode.
5.4.4 NMEA input message for ATP & PTF Mode
Power saving mode is disabled by default. In order to enable it input the NMEA
message in table below. The description of each parameter used for Adaptive
TricklePower or Push-to-Fix ™ is listed below. How to send these messages to the
target unit refer to chapter Appendix section 11.1 page .
Syntax $PSRF107,<Mode>,<OnTimeMs*>,<LPInterval*>,<MaxAcqTimeMs>,<MaxOffTimeMs>,<TPAdaptive><*CS><CR><LF>
Examples
$PSRF107,1,400,2000,60000,60000,1*17<CR><LF>
$PSRF107,2,400,60000,60000,60000,0*21<CR><LF>
$PSRF107,0,0,0,0,0,0*21<CR><LF>
Parameter Description
<Mode>
It defines the mode to be performed. It can be set to:
0Sets the target receiver back to the Continuous mode
(full power).
1Sets the target receiver into the daptive TricklePower
(TP) mode.
2Sets the target receiver into the Push-To-Fix (PTF) mode.
<OnTimeMs*>
It defines the OnTime period in milliseconds the receiver will stay in full
power state until a position solution is made and estimated to be
reliable. Please note that in harsh tracking environments the receiver
automatically switches to full power state to improve navigation
performance even if the defined OnTime has been expired. When the
satellites are sorted according their signal strength the fourth satellite
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JP14-R-LP & JP14-Q-LP FALCOM GPS RECEIVERS VERSION 1.0.0
determines if the transition to Standby mode/hibernate state will occur
or not. It can be set to a value between:
200 ... 900 OnTime period in milliseconds
<LPInterval*>
It defines the complete interval of time in milliseconds the receiver will
stay in full power and Standby mode/hibernate state.
It can be set to a value between:
1000 ... 10000 The interval of time in milliseconds for daptive
TricklePower ( TP) mode.
10000 ... 7200000 The interval of time in milliseconds for Push-To-Fix
(PTF) mode.
<MaxAcqTimeMs>
It specifies the Maximum Acquire Time in milliseconds how long the
target receiver should attempt to acquire satellites and navigate. If this
time elapses and no GPS-fix is obtained the target receiver is set into
the sleep mode for up to MaxOffTime in ms. It means the target receiver
searches for MaxAcqTime in ms sleeps for MaxOffTime in ms searches
again for MaxAcqTime in ms etc. It can be set to a value between:
1000 ... No Limit
<MaxOffTimeMs>
It specifies the Maximum Off Time in milliseconds how long the target
receiver should remain off (sleep mode) before making another
attempt to navigate. This mode is enabled if the target receiver is
turned on and acquires satellites but does not navigate. This mode is
disabled if the target receiver is turned on acquires and navigates. It
can be set to a value between:
1000 .. 1800000
<TPAdaptive>
It enables/disables the Adaptive TricklePower (ATP) mode if the value of
the <Mode> parameter is set to 1 otherwise it does not have any effect.
It can be set to:
0It disables the daptive TricklePower ( TP) mode.
1It enables the daptive TricklePower ( TP) mode.
<*CS>
CHECKSUM is a two-hex character as defined in the NMEA specification.
Use of checksums is required on all input messages. For more detailed
information refer to the chapter 7.2. page 25.
<CR><LF>
Each message is terminated using Carriage Return (CR) Line Feed (LF)
which is hex 0D 0A. Because 0D 0A are not printable ASCII characters
they are omitted from the example strings but must be sent to terminate
the message and cause the receiver to process that input message.
* Note:
•SiRF recommends the use of 300 ms, 1-second or 400 ms, 2-second for
optimum performance.
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JP14-R-LP & JP14-Q-LP FALCOM GPS RECEIVERS VERSION 1.0.0
6 HARDWARE INTERFACE AND CONFIGURATION
SIGNALS
6.1 Interfaces (balls assignment) of the JP14-R-LP
Ball Name I/O Description Level
1 VCC I Main power supply + . V DC ±5 %
2 VCC
VBAT I Power for RTC and SRAM + V DC ±5%
4 VDDK O Core power at 1.5 V. Do not use, leave it open.
5 SDI1 I Serial Data Input A CMOS
6 SDO1 O Serial Data Output A CMOS
7 SDO2 O Serial Data Output B (It is not supported by default GSW .1.0) CMOS
8 SDI2 I Serial Data Input B (It is not supported by default GSW .1.0) CMOS
9 NADC_D I Do not use, leave it open.
10 SPI_EN I Control-line for production test. Do not use, leave it open. CMOS
11 SPI_CLK I Control-lines for production test. Do not use, leave it open.
12 SPI_DATA O Control-line for production test. Do not use, leave it open.
1 NC
- Not connected -14 NC
15 NC
16 GPIO0 I/O General propose input/output CMOS
17 NC - Not connected -
18 GND Digital ground 0 V
19 GND_RF Analogue ground
20 VANT I Power supply for an active antenna Up to +12 V DC / max. 25
mA
21 RF_IN I GPS signal from connected antenna 50 Ohms @ 1.575 GHz
22 GND_RF Analogue grounds
2 GND_RF
24 VCCRF O Supply voltage of RF section + 2.85 V DC / max. 25 mA
25 GND Digital grounds 0 V
26 GND
27 NSRESET I Do not use, leave it open.
28 T-MARK O 1 PPS Time Mark Output CMOS
29 BOOTSEL I Boots the unit into the Update mode, if it is set to HIGH. CMOS (=VCC)
0 NADC_CS O Control outputs. Do not use, leave it open. CMOS
1 TIMERSYNC O Control outputs. Do not use, leave it open. CMOS
2 CS2 O Control outputs. Do not use, leave it open. CMOS
GPIO1 I/O General propose input/output CMOS
4 VCCGSP O Control output for baseband processor. Do not use, leave it
open. CMOS
This confidential document is the property of FALCOM and may not be copied or circulated without permission.
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JP14-R-LP & JP14-Q-LP FALCOM GPS RECEIVERS VERSION 1.0.0
Ball Name I/O Description Level
5 PWRCTL O Control outputs. Do not use, leave it open. CMOS
6 WAKEUP O Control outputs. Do not use, leave it open. CMOS
7 GPIO10 I/O General propose input/output CMOS
8 M-RST I Rest the unit, active low CMOS
9 VDD_RTC I Control-line for production test. Do not use, leave it open. +1.5 V DC
40 ON/OFF I Control-line for production test. Do not use, leave it open. CMOS
Table 1: Pin assignment of the JP14-R
6.2 Interfaces (balls assignment) of the JP14-Q-LP
Ball Name I/O Description Level
1 GND_RF Analogue grounds
2 VANT I Power supply for an active antenna Up to +12 V DC / max. 25
mA
GND Analogue grounds 0 V
4 VCC
5 VCC I Main power supply + . V DC ±5 %
6 VBAT I Power for RTC and SRAM + V DC ±5%
7 VCCRF O Supply voltage of RF section + 2.85 V DC / max. 25 mA
8 M-RST I Rest the unit, active low CMOS
9 VCCGSP O Control output for baseband processor.Do not use, leave
it open. CMOS
10 PWRCTL O Control outputs. Do not use, leave it open. CMOS
11 BOOTSEL I Boots the unit into the Update mode, if it is set to HIGH. CMOS (=VCC)
12 WAKEUP O Control outputs. Do not use, leave it open. CMOS
1 CS2 O Control outputs. Do not use, leave it open. CMOS
14 GPIO1 I/O General propose input/output CMOS
15 GPIO0 I/O General propose input/output CMOS
16 SDI1 I Serial Data Input A CMOS
17 SDO2 O Serial Data Output B (It is not supported by default
GSW .1.0) CMOS
18 SDO1 O Serial Data Output A CMOS
19 VDDK O Core power at 1.5 V. Do not use, leave it open.
20 SDI2 I Serial Data Input B (It is not supported by default
GSW .1.0) CMOS
21 GPIO10 I/O General propose input/output CMOS
22 VDD_RTC I Control-line for production test. Do not use, leave it open. +1.5 V DC
2 T-MARK O 1 PPS Time Mark Output CMOS
24 ON/OFF I Control-line for production test. Do not use, leave it open. CMOS
25 NADC_CS O Control outputs. Do not use, leave it open. CMOS
This confidential document is the property of FALCOM and may not be copied or circulated without permission.
Page 20