Freescale Semiconductor CPU32 User manual

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CPU32
REFERENCE MANUAL
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CPU32 REFERENCE MANUAL MOTOROLA
iii
PREFACE
This reference manual describes programming and operation of the CPU32 in-
struction processing module, found in the M68300 Family of embedded controllers.
It is part of a multivolume set of manuals — each volume corresponds to a major
module in the M68300 Family.
A user's manual for each device incorporating the CPU32 describes processor
function and operation with reference to other modules within the device.
This manual consists of the following sections and appendix:
Section 1 Overview
Section 2 Architecture Summary
Section 3 Data Organization and Addressing Capabilities
Section 4 Instruction Set
Section 5 Processing States
Section 6 Exception Processing
Section 7 Development Support
Section 8 Instruction Execution Timing
Appendix A M68000 Family Summary
Index
NOTE
In this manual, the terms assertion and negation specifya particular
logic state.
Assert and assertion refer to an active or true signal.
Negate and negation refer to an inactive or false signal. These
termsare used independently of the voltage level that theyrepresent.
This manual is written for systems designers, systems programmers, and applica-
tions programmers. Systems designers need general knowledge of the entire vol-
ume, with particular emphasis on Section 1, Section 7, and Appendix A — they will
also need to be familiar with electrical specifications and mechanical data con-
tained in the user’s manual. Systems programmers should become familiar with
Sections 1 through 6, Section 8, and Appendix A. Applications programmers can
find most of the information they need in Sections 1 through 5, Section 8, and Ap-
pendix A.
This manual is also written for users of the M68000 Family that are not familiar with
the CPU32. Although there are comparative references to other Motorola micro-
processors throughout the manual, Section 1, Section 2, and Appendix A specifi-
cally identify the CPU32 within the M68000 Family, and discuss the differences
betweeen it and related devices.
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MOTOROLA CPU32 REFERENCE MANUAL
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REFERENCE MANUAL v
Paragraph Title Page
SECTION 1 OVERVIEW
1.1 Features ....................................................................................................1-1
1.1.1 Virtual Memory ..................................................................................1-2
1.1.2 Loop Mode Instruction Execution ......................................................1-2
1.1.3 Vector Base Register ........................................................................1-3
1.1.4 Exception Handling ...........................................................................1-3
1.1.5 Enhanced Addressing Modes ...........................................................1-4
1.1.6 Instruction Set ...................................................................................1-4
1.1.6.1 Table Lookup and Interpolation Instructions .............................1-4
1.1.6.2 Low-Power Stop Instruction ......................................................1-6
1.1.7 Processing States .............................................................................1-6
1.1.8 Privilege States .................................................................................1-6
1.2 Block Diagram ...........................................................................................1-6
SECTION 2ARCHITECTURE SUMMARY
2.1 Programming Model ..................................................................................2-1
2.2 Registers ...................................................................................................2-2
2.3 Data Types ................................................................................................2-3
2.3.1 Organization in Registers ..................................................................2-4
2.3.1.1 Data Registers ..........................................................................2-4
2.3.1.2 Address Registers .....................................................................2-5
2.3.1.3 Control Registers ......................................................................2-5
2.3.2 Organization in Memory ....................................................................2-6
SECTION 3 DATA ORGANIZATION AND ADDRESSING CAPABILITIES
3.1 Program and Data References ..................................................................3-1
3.2 Notation Conventions ................................................................................3-2
3.3 Implicit Reference ......................................................................................3-2
3.4 Effective Address ......................................................................................3-3
3.4.1 Register Direct Mode .........................................................................3-3
3.4.1.1 Data Register Direct ..................................................................3-3
3.4.1.2 Address Register Direct ............................................................3-3
3.4.2 Memory Addressing Modes ...............................................................3-4
3.4.2.1 Address Register Indirect ..........................................................3-4
3.4.2.2 Address Register Indirect With Postincrement ..........................3-4
3.4.2.3 Address Register Indirect With Predecrement ..........................3-4
3.4.2.4 Address Register Indirect With Displacement ...........................3-5
3.4.2.5 Address Register Indirect With Index (8-Bit Displacement) ......3-5
3.4.2.6 Address Register Indirect With Index (Base Displacement) .....3-6
TABLE OF CONTENTS
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TABLE OF CONTENTS
3.4.3 Special Addressing Modes ................................................................3-7
3.4.3.1 Program Counter Indirect With Displacement ...........................3-7
3.4.3.2 Program Counter Indirect with Index (8-Bit Displacement) .......3-7
3.4.3.3 Program Counter Indirect with Index (Base Displacement) ......3-8
3.4.3.4 Absolute Short Address ............................................................3-8
3.4.3.5 Absolute Long Address .............................................................3-9
3.4.3.6 Immediate Data .........................................................................3-9
3.4.4 Effective Address Encoding Summary ..............................................3-9
3.5 Programming View of Addressing Modes ...............................................3-11
3.5.1 Addressing Capabilities ...................................................................3-11
3.5.2 General Addressing Mode Summary ..............................................3-14
3.6 M68000 Family Addressing Capability ....................................................3-14
3.7 Other Data Structures .............................................................................3-15
3.7.1 System Stack ..................................................................................3-15
3.7.2 User Stacks .....................................................................................3-16
3.7.3 Queues ............................................................................................3-17
SECTION 4 INSTRUCTION SET
4.1 M68000 Family Compatibility ....................................................................4-1
4.1.1 New Instructions ................................................................................4-1
4.1.1.1 Low-Power Stop (LPSTOP) ......................................................4-1
4.1.1.2 Table Lookup and Interpolation (TBL) .......................................4-2
4.1.2 Unimplemented Instructions ..............................................................4-2
4.2 Instruction Format .....................................................................................4-2
4.2.1 Notation .............................................................................................4-3
4.3 Instruction Summary .................................................................................4-5
4.3.1 Condition Code Register ...................................................................4-5
4.3.2 Data Movement Instructions ..............................................................4-6
4.3.3 Integer Arithmetic Operations ............................................................4-7
4.3.4 Logic Instructions ..............................................................................4-8
4.3.5 Shift and Rotate Instructions .............................................................4-9
4.3.6 Bit Manipulation Instructions .............................................................4-9
4.3.7 Binary-Coded Decimal (BCD) Instructions ......................................4-10
4.3.8 Program Control Instructions ...........................................................4-10
4.3.9 System Control Instructions ............................................................4-11
4.3.10 Condition Tests ...............................................................................4-12
4.4 Instruction Details ....................................................................................4-13
4.5 Instruction Format Summary .................................................................4-170
4.6 Table Lookup and Interpolation Instructions .........................................4-188
4.6.1 Table Example 1: Standard Usage ...............................................4-188
4.6.2 Table Example 2: Compressed Table ...........................................4-189
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TABLE OF CONTENTS
4.6.3 Table Example 3: 8-Bit Independent Variable ...............................4-191
4.6.4 Table Example 4: Maintaining Precision .......................................4-192
4.6.5 Table Example 5: Surface Interpolations ......................................4-194
4.7 Nested Subroutine Calls ........................................................................4-194
4.8 Pipeline Synchronization with the NOP Instruction ...............................4-194
SECTION 5PROCESSING STATES
5.1 State Transitions .......................................................................................5-1
5.2 Privilege Levels .........................................................................................5-1
5.2.1 Supervisor Privilege Level .................................................................5-2
5.2.2 User Privilege Level ..........................................................................5-2
5.2.3 Changing Privilege Level ...................................................................5-2
5.3 Types of Address Space ...........................................................................5-3
5.3.1 CPU Space Access ..........................................................................5-3
5.3.1.1 Type 0000 — Breakpoint ..........................................................5-4
5.3.1.2 Type 0001 — MMU Access ......................................................5-4
5.3.1.3 Type 0010 — Coprocessor Access ...........................................5-4
5.3.1.4 Type 0011 — Internal Register Access .....................................5-4
5.3.1.5 Type 1111 — Interrupt Acknowledge ........................................5-5
SECTION 6 EXCEPTION PROCESSING
6.1 Definition of Exception Processing ............................................................6-1
6.1.1 Exception Vectors .............................................................................6-1
6.1.2 Types of Exceptions ..........................................................................6-2
6.1.3 Exception Processing Sequence .......................................................6-3
6.1.4 Exception Stack Frame .....................................................................6-3
6.1.5 Multiple Exceptions ...........................................................................6-4
6.2 Processing of Specific Exceptions ............................................................6-5
6.2.1 Reset .................................................................................................6-5
6.2.2 Bus Error ...........................................................................................6-6
6.2.3 Address Error ....................................................................................6-7
6.2.4 Instruction Traps ................................................................................6-8
6.2.5 Software Breakpoints ........................................................................6-8
6.2.6 Hardware Breakpoints .......................................................................6-8
6.2.7 Format Error ......................................................................................6-9
6.2.8 Illegal or Unimplemented Instructions ...............................................6-9
6.2.9 Privilege Violations ..........................................................................6-10
6.2.10 Tracing ............................................................................................6-11
6.2.11 Interrupts .........................................................................................6-12
6.2.12 Return from Exception .....................................................................6-13
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TABLE OF CONTENTS
6.3 Fault Recovery ........................................................................................6-14
6.3.1 Types of Faults ................................................................................6-16
6.3.1.1 Type I: Released Write Faults .................................................6-16
6.3.1.2 Type II: Prefetch, Operand, RMW, and MOVEP Faults ..........6-17
6.3.1.3 Type III: Faults During MOVEM Operand Transfer .................6-17
6.3.1.4 Type IV: Faults During Exception Processing .........................6-18
6.3.2 Correcting a Fault ............................................................................6-18
6.3.2.1 (Type I) Completing Released Writes via Software ................6-19
6.3.2.2 (Type I) Completing Released Writes via RTE .......................6-19
6.3.2.3 (Type II) Correcting Faults via RTE .........................................6-19
6.3.2.4 (Type III) Correcting Faults via Software .................................6-20
6.3.2.5 (Type III) Correcting Faults By Conversion and Restart .........6-20
6.3.2.6 (Type III) Correcting Faults via RTE ........................................6-21
6.3.2.7 (Type IV) Correcting Faults via Software ................................6-21
6.4 CPU32 Stack Frames ..............................................................................6-21
6.4.1 Normal Four-Word Stack Frame .....................................................6-22
6.4.2 Normal Six-Word Stack Frame ........................................................6-22
6.4.3 BERR Stack Frame .........................................................................6-22
SECTION 7 DEVELOPMENT SUPPORT
7.1 CPU32 Integrated Development Support ..................................................7-1
7.1.1 Background Debug Mode (BDM) Overview ......................................7-1
7.1.2 Deterministic Opcode Tracking Overview .........................................7-2
7.1.3 On-Chip Hardware Breakpoint Overview ..........................................7-3
7.2 Background Debug Mode (BDM) ..............................................................7-3
7.2.1 Enabling BDM ...................................................................................7-4
7.2.2 BDM Sources ....................................................................................7-4
7.2.2.1 External BKPT Signal ................................................................7-4
7.2.2.2 BGND Instruction ......................................................................7-4
7.2.2.3 Double Bus Fault .......................................................................7-5
7.2.2.4 Peripheral Breakpoints ..............................................................7-5
7.2.3 Entering BDM ....................................................................................7-5
7.2.4 Command Execution .........................................................................7-5
7.2.5 Background Mode Registers .............................................................7-6
7.2.5.1 Fault Address Register (FAR) ...................................................7-6
7.2.5.2 Return Program Counter (RPC) ................................................7-6
7.2.5.3 Current Instruction Program Counter (PCC) .............................7-7
7.2.6 Returning from BDM ..........................................................................7-7
7.2.7 Serial Interface ..................................................................................7-7
7.2.7.1 CPU Serial Logic .......................................................................7-8
7.2.7.2 Development System Serial Logic ..........................................7-10
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TABLE OF CONTENTS
7.2.8 Command Set .................................................................................7-11
7.2.8.1 Command Format ...................................................................7-11
7.2.8.2 Command Sequence Diagram ................................................7-12
7.2.8.3 Command Set Summary .........................................................7-14
7.2.8.4 Read A/D Register (RAREG/RDREG) ....................................7-15
7.2.8.5 Write A/D Register (WAREG/WDREG) ...................................7-15
7.2.8.6 Read System Register (RSREG) ............................................7-16
7.2.8.7 Write System Register (WSREG) ...........................................7-16
7.2.8.8 Read Memory Location (READ) ..............................................7-17
7.2.8.9 Write Memory Location (WRITE) ............................................7-18
7.2.8.10 Dump Memory Block (DUMP) .................................................7-19
7.2.8.11 Fill Memory Block (FILL) .........................................................7-21
7.2.8.12 Resume Execution (GO) .........................................................7-22
7.2.8.13 Call User Code (CALL) ...........................................................7-22
7.2.8.14 Reset Peripherals (RST) .........................................................7-24
7.2.8.15 No Operation (NOP) ................................................................7-24
7.2.8.16 Future Commands ..................................................................7-25
7.3 Deterministic Opcode Tracking ...............................................................7-25
7.3.1 Instruction Fetch (IFETCH) .............................................................7-25
7.3.2 Instruction Pipe (IPIPE) ...................................................................7-25
7.3.3 Opcode Tracking during Loop Mode ...............................................7-27
SECTION 8 INSTRUCTION EXECUTION TIMING
8.1 Resource Scheduling ................................................................................8-1
8.1.1 Microsequencer .................................................................................8-1
8.1.2 Instruction Pipeline ............................................................................8-2
8.1.3 Bus Controller Resources .................................................................8-2
8.1.3.1 Prefetch Controller ....................................................................8-3
8.1.3.2 Write-Pending Buffer .................................................................8-3
8.1.3.3 Microbus Controller ...................................................................8-3
8.1.4 Instruction Execution Overlap ...........................................................8-4
8.1.5 Effects of Wait States ........................................................................8-5
8.1.6 Instruction Execution Time Calculation .............................................8-5
8.1.7 Effects of Negative Tails ....................................................................8-6
8.2 Instruction Stream Timing Examples .........................................................8-7
8.2.1 Timing Example 1: Execution Overlap ..............................................8-7
8.2.2 Timing Example 2: Branch Instructions .............................................8-8
8.2.3 Timing Example 3: Negative Tails .....................................................8-9
8.3 Instruction Timing Tables ........................................................................8-10
8.3.1 Fetch Effective Address ..................................................................8-12
8.3.2 Calculate Effective Address ............................................................8-13
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8.3.3 MOVE Instruction ............................................................................8-14
8.3.4 Special-Purpose MOVE Instruction .................................................8-14
8.3.5 Arithmetic/Logic Instructions ...........................................................8-15
8.3.6 Immediate Arithmetic/Logic Instructions ..........................................8-17
8.3.7 Binary-Coded Decimal and Extended Instructions ..........................8-18
8.3.8 Single Operand Instructions ............................................................8-18
8.3.9 Shift/Rotate Instructions ..................................................................8-19
8.3.10 Bit Manipulation Instructions ...........................................................8-20
8.3.11 Conditional Branch Instructions .......................................................8-20
8.3.12 Control Instructions .........................................................................8-21
8.3.13 Exception-Related Instructions and Operations ..............................8-21
8.3.14 Save and Restore Operations .........................................................8-22
APPENDIX AM68000 FAMILY SUMMARY
INDEX
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