Freescale Semiconductor QorIQ T1023 User manual

QorIQ T1023 Reference Design Board
User Guide
Document Number: T1023RDBUG
Rev. 0, 08/2015

QorIQ T1023 Reference Design Board User Guide, Rev. 0, 08/2015
2 Freescale Semiconductor, Inc.

Contents
Section number Title Page
Chapter 1
Overview
1.1 Related documentation....................................................................................................................................................5
1.2 Acronyms and abbreviations...........................................................................................................................................6
1.3 T1023RDB board features.............................................................................................................................................. 7
1.4 Specifications..................................................................................................................................................................9
1.5 T1023RDB-PC board drawings......................................................................................................................................10
Chapter 2
Architecture
2.1 Processor.........................................................................................................................................................................11
2.2 Power.............................................................................................................................................................................. 12
2.3 Reset................................................................................................................................................................................13
2.4 Clocks............................................................................................................................................................................. 14
2.5 Memory interface............................................................................................................................................................14
2.6 Termination.....................................................................................................................................................................15
2.7 SerDes interfaces (PCIe/SGMII/SATA).........................................................................................................................15
2.7.1 PCI Express support...........................................................................................................................................15
2.7.2 SGMII support................................................................................................................................................... 16
2.7.3 SerDes clock...................................................................................................................................................... 16
2.8 EC1 10/100/1000 BaseT interface (ETH1) ....................................................................................................................16
2.9 SerDes lane D 10/100/1000 BaseT interface (ETH2).....................................................................................................17
2.10 SerDes lane B 2.5G BaseT interface (ETH3)................................................................................................................. 17
2.11 Ethernet management......................................................................................................................................................17
2.12 Ethernet ports..................................................................................................................................................................18
2.13 I2C...................................................................................................................................................................................18
2.14 IFC.................................................................................................................................................................................. 20
2.14.1 NOR flash memory............................................................................................................................................ 20
2.14.2 NAND flash memory.........................................................................................................................................21
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Section number Title Page
2.15 eSPI interface..................................................................................................................................................................22
2.16 eSDHC interface............................................................................................................................................................. 22
2.17 GPIO interface................................................................................................................................................................ 23
2.18 Interrupts.........................................................................................................................................................................23
2.19 USB interface..................................................................................................................................................................24
2.20 RS-232............................................................................................................................................................................ 25
2.21 POR configuration.......................................................................................................................................................... 26
2.22 JTAG/COP port.............................................................................................................................................................. 26
2.23 DMA .............................................................................................................................................................................. 28
2.24 Connectors, Headers, Push buttons, and LEDs...............................................................................................................28
2.24.1 Connectors......................................................................................................................................................... 28
2.24.2 Headers...............................................................................................................................................................29
2.24.3 Push buttons....................................................................................................................................................... 30
2.24.4 LEDs.................................................................................................................................................................. 30
2.25 Switch settings................................................................................................................................................................ 31
2.25.1 T1023RDB-PC RCW source configuration (using switches)............................................................................31
2.25.2 Switches configuration options..........................................................................................................................32
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Chapter 1
Overview
The T1023 Reference design board (T1023RDB) is a system featuring QorIQ advanced
multicore processor. It combines two 64-bit ISA Power Architecture processor cores with
high-performance data path acceleration and network and peripheral bus interfaces
required for networking, telecom/datacom, wireless infrastructure, and military/aerospace
application.
This low-cost, high-performance system solution consists of a Printed circuit board
(PCB) assembly and a software Board support package (BSP). This BSP enables the
fastest possible time-to-market for development or integration of applications including
multi-service branch office router, security appliance/UTM and enterprise wireless access
point. This document describes the hardware features of the board including
specifications, block diagram, connectors, interfaces, and hardware straps. It also
describes the board settings and physical connections needed to boot the RDB. Revision
history lists the changes to this document.
When you finish reading this document, you should be familiar with:
• Board layout and its interfaces
• Board configuration options
This document is applicable for PCBA version 700-28530 Rev D and Schematics version
SCH-28530 Rev D.
1.1 Related documentation
The table below lists and explains the additional documents that you can refer to, for
more information about T1023RDB.
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Some of the documents listed below may be available only under a Non-disclosure
agreement (NDA). To request access to these documents, contact your local field
applications engineer or sales representative.
Table 1-1. Useful references
Document Description
QorIQ T1023 Integrated Processor
Reference Manual
Provides a detail description on T1023 QorIQ multicore processor, and on some of its
features like memory map, serial interfaces, power supply, chip features, and clock
information.
QorIQ T1023, T1013 Data Sheet Provides specific data regarding AC, DC electrical specifications, thermal
characteristics, and pin assignments, as well as other design considerations.
1.2 Acronyms and abbreviations
The table below lists and explains the acronyms and abbreviations used in this document.
Table 1-2. Acronyms and abbreviations
Usage Description
COP Common On-chip Processor
CPC CoreNet Platform Cache
CPLD Complex Programmable Logic Device
DIMM Dual In-Line Memory Module
DIP Dual In-Line Package
DIU Display Interface Unit
DMA Direct Memory Access
DPAA Data Path Acceleration Architecture
DRAM Dynamic Random Access Memory
DUT Device Under Test
EC Ethernet Controllers
EDC Error Detection and Correction
EEPROM Electrically Erasable Programmable Read-Only Memory
EMI Ethernet Management Interfaces
eMMC embedded MultiMediaCard
eSDHC enhanced Secure Digital Host Controller
eSPI enhanced Serial Peripheral Interface
FET Field Effect Transistor
HDLC High-level Data Link Control
I2C Inter-Integrated Circuit
IFC Integrated Flash Controller
JTAG Joint Test Action Group
Table continues on the next page...
Acronyms and abbreviations
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Table 1-2. Acronyms and abbreviations (continued)
Usage Description
MPIC Multicore Programmable Interrupt Controller
PCIe/PEX PCI Express
PLD Programmable Logic Device
POR Power On Reset
SATA Serial Advanced Technology Attachment
SD Secure Digital
SDRAM Synchronous Dynamic Random-Access Memory
SDHC Secure Digital High Capacity
SerDes Serializer/Deserializer
SGMII Serial Gigabit Media Independent Interface
SPI Serial Peripheral Interface
SYSCLK System Clock
TDM Time-Division Multiplexing
UART Universal Asynchronous Receiver/Transmitter
VCC Voltage for Circuit
VTT Voltage for Terminal
1.3 T1023RDB board features
The T1023RDB board features are as follows:
• T1023RDB runs at default core frequency 1.2 GHz, platform clock 400 MHz, DDR4
1600 MT/s.
• Memory subsystem:
• 2 GB unbuffered DDR4 SDRAM discrete devices (32-bit bus)
• 128 MB NOR flash single-chip memory
• 512 MB NAND flash memory
• 256 Kbit M24256 I2C EEPROM
• 64 MB SPI memory
• 8 GB eMMC 4.51
• SD/MMC connector to interface with the SD memory card
• Interfaces
• PCIe:
• Lane A: x1 mini-PCIe slot
• Lane C: x1 mini-PCIe slot
• 10/100/1000 BaseT Ethernet ports:
• EC1, RGMII: one 10/100/1000 port with RTL8211FS PHY
Chapter 1 Overview
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• Lane B: 2.5G SGMII port with AQR105 PHY
• Lane D: 1G SGMII port with RTL8211FS PHY
• USB 2.0 port:
• X1 USB2.0 port: connect to a type-A conector
• UART interface:
• UART interface: supports one UART at default 115200 Baud rate for
console display
• RJ-45 connector is used for the UART port
• Board connectors:
• JTAG/COP for T1023 debugging
• Push button for Board Reset
• Remote Reset Header
• Real-time clock on I2C bus
• Boot Source Selection:
• Supports NOR/SD/NAND/SPI boot by the selection of the dip switches
NOTE
Boot from eMMC will be supported in the next SDK
release.
• PoE:
• The power is enabled by default for all the boards. Turn off the power of one
PCIe card, if the external PoE power is not enough.
• PCB
• 6-layer routing (4-layer signals, 2-layer power and ground)
The below figure shows the T1023RDB-PC block diagram.
T1023RDB board features
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PoE Clocking Power POR
Config Reset
64MB SPI FLASH
USB2.0
Type A
RJ-45 RS232
Serial
SD/MMC
eMMC
EEPROM RTC
I2C1 JTAG
COP
RGMII PHY
1G SGMII PHY
2.5GSGMII PHY
Mini PCle Slot2
RJ-45
Mini PCle Slot1
512MB NAND
FLASH
128MB NOR
FLASH
DDR4
2GB
X32
X16
X8
DDR
IFC
SerDes
EC1
SPI
QorlQ
T1023
lane A
laneC
lane B
laneD
X1
X1
X1
X1
RJ-45
RJ-45
Figure 1-1. Block diagram
1.4 Specifications
The table below lists the specifications of the T1023RDB-PC.
Table 1-3. RDB specifications
Characteristics Specifications
Chassis Power requirements Maximum 60 W 12 V AC adapter
Chassis Power requirements 25.5 W If POE is present
Communication processor T1023 cores running at 1400 MHz
Operating temperature 0 °C to 70 °C (room temperature)
Storage temperature –25 °C to 85 °C
Table continues on the next page...
Chapter 1 Overview
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Table 1-3. RDB specifications (continued)
Characteristics Specifications
Relative humidity 5% to 90% (noncondensing)
PCB dimensions:
Length
Width
Thickness
8504 mil (216 mm)
6692 mil (170 mm)
62 mil
1.5 T1023RDB-PC board drawings
The below figure shows the T1023RDB-PC board diagram. The board is 216 mm x 170
mm (8504 mil x 6692 mil).
Figure 1-2. T1023RDB-PC board diagram
T1023RDB-PC board drawings
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Chapter 2
Architecture
This chapter explains the architecture of T1023RDB:
•Processor
•Power
•Reset
•Clocks
•Memory interface
•Termination
•SerDes interfaces (PCIe/SGMII/SATA)
•Ethernet controllers
•EC1 10/100/1000 BaseT interface (ETH1)
•SerDes lane D 10/100/1000 BaseT interface (ETH2)
•SerDes lane B 2.5G BaseT interface (ETH3)
•Ethernet management
•Ethernet ports
•I2C
•IFC
•eSPI interface
•eSDHC interface
•GPIO interface
•Interrupts
•USB interface
•RS-232
•POR configuration
•JTAG/COP port
•DMA
•Connectors, Headers, Push buttons, and LEDs
•Switch settings
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2.1 Processor
The T1023RDB supports many features of the T1023 processor, as detailed in the
following sections. The boards and the supporting hardware are all identical, but the
ability to use various features depends on the device installed.
2.2 Power
The power supply system of the T1023RDB systems uses external power adaptor +12 V
for the RDB board. The rated power is 60 W.
•PoE Power Supply - Linear Technical LTC4269 on board is used for Power over
Ethernet function. It is compliant to the 802.3 at standard and can supply 22.5 W
power for the board. LTC4269 is sourced from the ETH3 ethernet port. Mini-PCIe
slot and SGMII PHY, AQR105 and USB regulators can be turned off by resetting
jumpers, once the PoE power is not enough. DCDC provides power these devices.
For more details, see Connectors, Headers, Push buttons, and LEDs.
•CPU VDD (DCDC_1V0) - The CPU core voltage DCDC_1V0 rail is sourced from a
Linear switching regulator. The device used on the RDB is the LT8612. DCDC_1V0 =
1.0 V.
•AVDD For Core PLL, Platform, SerDes - All these pins are sourced from VR500
SW2 output VR500_1V8, and RC filter is used for each pin. Voltage is 1.8 V.
•DDR - The memory interface power (VPP, VTT, GVDD, and VREF) are sourced
from VR500. VR500_2V5 for VPP = 2.5 V, VR500_VTT for VTT = 0.6 V,
VR500_1V2 for GVDD = 1.2 V, and VR500_VREF for VREF = 0.6 V.
•SerDes - The SerDes Receiver power S1VDD is sourced from a Linear regulator
LT3021. The SerDes Transmitter and PLL power X1VDD is sourced from the
VR500. LDO_1V0 for S1VDD = 1.0 V; VR500_1V35 for X1VDD = 1.35 V.
•eSPI, SDHC_WP, SDHC_CD (CVDD) - Each of these rails are sourced from the
VR500 SW2. VR500_1V8 for CVDD = 1.8 V.
•SD/MMC (EVDD) - EVDD can be selected between 1.8 V (VR500_1V8) and 3.3 V
(DCDC2_3V3), T1023 pin SDHC_VS is used to enable the selected rail. This pin is
pull down to select 3.3 V when it is set high, EVDD will be switched to 1.8 V rail.
•IFC, GPIO, JTAG IO, System Control (OVDD) - This rail is sourced from the
VR500 SW2. VR500_1V8 for OVDD = 1.8 V.
•I2C, UART (DVDD) - I2C and UART interface is operated in 3.3 V level, and are
sourced directly from the always on regulator LT8612 (U29), DCDC2_3V3 rail.
•Ethernet Interface, EMI1 EMI2 (LVDD/TVDD) - The LVDD rail is used for the
TSEC I/O and is configured for 1.8 V operation. The rail is sourced from VR500
SW2, rail is VR500_1V8. TVDD for EMI2 is 1.2 V and sourced from a linear
regulator LT3021, rail is LDO_1V2.
Power
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•Mini-PCIe (1.5 V, 3.3 V and PA for QCA card) - The +1.5 V rail is used by the
mini-PCIe slot and is sourced by VR500, rail name is VR500_1V5. The Mini-PCIe 1
(P2) 3.3 V is sourced from regulator LT8612(U29), DCDC2_3V3. The Mini-PCIe
2(P3) 3.3 V is sourced from another regulator LT8612 (U28). Each PA card is
sourced from a LT8612(U45 and U49) regulator. Each type of card has different PA
voltage. Hence, each DCDC can be adjusted to the four kind of output voltages, that
is 3.3 V,3.5 V, 4.5 V,and 5 V. For more details, see Connectors, Headers, Push
buttons, and LEDs
•AQR105 (0.85 V, 1.2 V, 2.1 V, 2.5 V) - 0.85 V is sourced from part LTC3605A, rail
is DCDC_V85; 1.2 V is sourced from part LT3021, rail is LDO_1V2; 2.1 V is
sourced from another LT3021 part, rail is LDO_2V1; 2.5 V is sourced from the
VR500_2V5 rail.
The following figure shows the board power structure and the current consumption. All
the values marked are the maximum values from the datasheet and are only for reference.
Figure 2-1. Power block
2.3 Reset
All resets on the board are handled by the reset switch SW4. Power-on Reset is initiated
by pressing the switch SW4. Software is also capable of initiating a reset by asserting the
RESET_REQ line from the processor.
Chapter 2 Architecture
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2.4 Clocks
The T1023 board uses single source clocking mode. The clock generator channel
provides 100 MHz to the system differential clock input. The Ethernet controller clock is
sourced from the RTL8211 PHY.
2.5 Memory interface
The memory interface on the RDB is configured as DDR4 and is implemented as a single
bank discrete chips (x8). ECC is not supported on the design. The memory size supported
on the board is shown below.
Figure 2-2. Memory interface
The PCB design is capable of running up to a clock rate of 800 MHz (1600 MT/s data
rate). The DDR4 interface uses the SSTL driver/receiver and 1.2 V power. A VREF,
1.2V/2 is needed for all SSTL receivers in the DDR4 interface. A VPP 2.5 V is need for
DDR4 which is used for activating power supply. For details on DDR4 timing design and
termination, see Application Note AN3940- Hardware and Layout Design Considerations
for DDR3 Memory Interfaces. Signal integrity test results show this design does not
require serialing resistors (Series resistor (SR) and Termination resistor (TR)) for the
discrete DDR4 devices used. DDR4 supports on-die termination; the DDR4 chips and
T1023 are connected directly. The 1.2 V, VREF, VTT, and VPP are powered from a
PMIC VR500 output.
Clocks
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T1023
DDR4
Controller
MCS[0]_B
MCK, MCK_B, MCKE[0]
MRAS_B, MCAS_B, MWE_B
A[0:14], BA[0:1],BG[0:1]
MDQ[0:31]
MDQS[0:3], MDQS[0:3]_B
MDM[0:3]
ODT
PAR, ALERT, ACT
DDR4 Device
39 Ohm VREF
VTT
Figure 2-3. DDR4 SDRAM connection
NOTE
DQ swap across nibbles is not allowed.
2.6 Termination
The DDR4 address, control, and command signals are terminated to the VTT rail through
39 Ohm resistor.
2.7 SerDes interfaces (PCIe/SGMII/SATA)
T1023 processor supports the SGMII, 2.5G SGMII and PCI Express high-speed I/O
interface standards. The table below details the SerDes connections.
Table 2-1. SerDes1 connectivity
SerDes Lane Mode Connected to Comment
Lane A PCI Express 1 Mini-PCIe slot Used for WLAN type cards
Lane C PCI Express 2 Mini-PCIe slot Used for WLAN type cards
Lane B 2.5G SGMII AQR105 PHY
Lane D 1G SGMII Realtek SGMII PHY
Chapter 2 Architecture
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2.7.1 PCI Express support
On the RDB, lanes A and C are configured as two independent x1 PCI Express
interfaces. These interfaces are compliant with the PCI Express Base Specification
Revision 2.0. The physical layer of the PCI Express interface operates at a transmission
rate of 3.125 Gbaud (data rate of 2.5 Gbit/s) per lane. The theoretical unidirectional peak
bandwidth is 2.5 Gbit/s per lane. Receive and transmit ports operate independently,
resulting in an aggregate theoretical bandwidth of 5 Gbit/s per lane. It supports Root
complex (RC) and End point (EP) configurations.
2.7.2 SGMII support
On the T1023RDB-PC, lane B of SerDes are used in 2.5G SGMII mode and lane D are in
1G SGMII mode. The Serial gigabit media independent interface (SGMII) is a high-
speed interface linking the Ethernet controller with an Ethernet PHY. SGMII uses
differential signalling for electrical robustness. Only four signals are required: receive
data and its inverse, and send data and its inverse.
2.7.3 SerDes clock
The clocking for the SerDes interface is 100 MHz for SerDes PLL1 and 125 MHz for
SerDes PLL2, both are provided by the 5P49V5901A616NLGI clock chip.
2.8 EC1 10/100/1000 BaseT interface (ETH1)
EC1 is set to operate in RGMII mode. It connects to a Realtek RGMII PHY
(RTL8211FS), as shown in the below figure.
EC1
EMI1
T1023
RGMII
MDC, MDIO
RTL8211FS
GBE PHY
MDIO PHY
Address = 1
RJ-45 Port
ETH1
Figure 2-4. RGMII interface connection
EC1 10/100/1000 BaseT interface (ETH1)
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2.9 SerDes lane D 10/100/1000 BaseT interface (ETH2)
SerDes lane D is set to operate in SGMII and is directly connected to the RealTek SGMII
PHY(RTL8211FS), as shown in the below figure.
lane D
EMI1
T1023
SGMII
MDC, MDIO
RTL8211FS
GBE PHY
MDIO PHY
Address = 3
RJ-45 Port
ETH2
Figure 2-5. SGMII interface connection
2.10 SerDes lane B 2.5G BaseT interface (ETH3)
SerDes lane B is set to operate in 2.5G SGMII and is directly connected to the AQR105
PHY, as shown in the below figure.
Figure 2-6. SGMII interface connection
Chapter 2 Architecture
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2.11 Ethernet management
The table below details how the MDC and MDIO connections are made on the RDB.
Table 2-2. MDC/MDIO connectivity
Device PHY address
EC1/RGMII PHY 00001
AQR105 PHY 00010
SGMII PHY 00011
2.12 Ethernet ports
The figure below shows how the Ethernet ports are connected on the backside of the
RDB chassis. ETH3 (PoE) port is same as the PoE power port.
ETH1 ETH2 ETH3 (PoE)
Figure 2-7. Ethernet port connection
2.13 I2C
The T1023 device has two I2C controllers. On the RDB, the I2C buses are connected as
shown below. The M24256 serial EEPROM can be used to store configuration registers’
values.
Ethernet ports
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T1023
I2C1-SCL
3.3 V
3.3 V
Vcore Current Sense
INA220A
SCL
SDA
I2C Address = 0x41
12V Current Sense
INA220A
Mini PCle 1
PCle x1
Connector
I2C Address is dependent
by PCle card
MC34VR500
PMIC
DS1339U-33+
I2C RTC
I2C1-SDA
I2C EEROM
SCL
SDA
SCL
SDA
SCL
SDA
SCL
SDA
SCL
SDA
SCL
SDA
M24256
I2C2-SCL
I2C2-SDA
I2C Address = 0x40
I2C Address is dependent
by PCle card
Mini PCle 2
PCle x1
Connector
I2C Address = 0x08
I2C Address = 0x68
I2C Address = 0x50
GPIO Expander for
selecting NOR BANK
I2C Address = 0x20
Figure 2-8. I2C subsystem
The table below shows all the I2C device and address information on T1023RDB-PC.
Table 2-3. I2C Bus connections
I2C Bus I2C Address Manufactur
er
Device Comment
I2C1 0x50 ST
Microelectron
ics
M24256 Stores configuration register's value
I2C1 0x68 Dallas DS1339U-33+ Real time clock
I2C1 0x08 Freescale MC34VR500 PMIC
I2C1 Mini PCIe 2 PCIe x1
Connector
I2C address is dependent on PCIe
card
I2C2 0x41 Linear INA220A core current measurement
Table continues on the next page...
Chapter 2 Architecture
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Table 2-3. I2C Bus connections (continued)
I2C Bus I2C Address Manufactur
er
Device Comment
I2C2 0x40 Linear INA220A 12 V current measurement
I2C2 Linear Mini PCIe 1 PCIe x1
Connector
I2C address is dependent on PCIe
card
I2C2 0x20 NXP PCA6408APW GPIO expander for selecting NOR
bank
2.14 IFC
The Integrated flash controller (IFC) is used to access the external NAND flash and NOR
flash. To interface with the standard memory device, an address latch is needed on the
upper address bits since they are multiplexed with the data bus. The IFC_AVD is used as the
latching signal. The following modules are connected to the IFC:
• 128 MB NOR flash memory
• 512 MB NAND flash memory
NOTE
Silicon IFC_NOR 28 bit addressing mode is not functional with
Asynchronous non-ADM NOR. For more details, see
A-009138: IFC_NOR 28/25 addressing mode is not functional
for T1023 with Asynchronous, Non-ADM NOR errata
document.
2.14.1 NOR flash memory
T1023RDB-PC provides 128 MB of NOR flash memory. The flash memory used is
configured in a 16-bit port size. The NOR flash memory is divided in to 8 banks. By
default, only bank0 and bank4 are supported to swap in U-Boot by using the following
commands:
switch bank0
switch bank4
The below figure shows the hardware connections for the flash memory.
IFC
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