FRONTGRADE GR740-MINI User manual

Frontgrade Gaisler AB
Kungsgatan 12 | SE-411 19 Goteborg | Sweden
[phone] | frontgrade.com/gaisler
GR740-MINI
Development Board
GR740-MINI-UM
Dec 2023, Version 1.1
GR740-MINI Board User’s Manual
Dec 2023, Version 1.1
USER'S MANUAL

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GR740-MINI
GR740-MINI-UM
Dec 2023, Version 1.1
TABLE OF CONTENTS
1Introduction..............................................................................................................................................................4
1.1 Purpose and Scope of the Document .........................................................................................................4
1.2 Reference Documents ...................................................................................................................................4
2Abbreviations ..........................................................................................................................................................5
3GR740-Mini-board Design .................................................................................................................................... 6
3.1 Overview .......................................................................................................................................................... 6
3.2 Handling...........................................................................................................................................................7
4Board design ...........................................................................................................................................................8
4.1 Board block diagram ......................................................................................................................................9
4.2 Power the board ...........................................................................................................................................10
4.3 Interacting with the board ............................................................................................................................ 11
4.4 Power supplies..............................................................................................................................................12
4.5 FTDI chip ....................................................................................................................................................... 13
4.6 Reset ..............................................................................................................................................................14
4.7 GR740 Processor .........................................................................................................................................15
4.7.1 Bootstrap signals .................................................................................................................................16
4.7.2 Debugging.............................................................................................................................................17
4.7.3 LED ........................................................................................................................................................18
4.7.4 JTAG ......................................................................................................................................................18
4.7.5 WDOGN ................................................................................................................................................19
4.7.6 Oscillators and clock input..................................................................................................................20
4.7.7 SDRAM.................................................................................................................................................. 21
4.7.8 PROM....................................................................................................................................................22
4.7.9 Ethernet................................................................................................................................................. 23
4.7.10 SpaceWire ............................................................................................................................................ 24
4.7.11 GPIO...................................................................................................................................................... 24
4.8 CertusPro-NX FPGA....................................................................................................................................25
4.8.1 Configurate and programming ...........................................................................................................26
4.8.2 LED ........................................................................................................................................................27
4.8.3 JTAG ......................................................................................................................................................28
4.8.4 SPI FLASH............................................................................................................................................28
4.8.5 Oscillators and clocks input................................................................................................................29
4.8.6 DDR3 Memory...................................................................................................................................... 30
4.8.7 Ethernet................................................................................................................................................. 31
4.8.8 SerDes...................................................................................................................................................32
4.9 Intercommunication between GR740 and CertusPro-NX.......................................................................33
4.9.1 PCI .........................................................................................................................................................33
4.9.2 GMII/MII................................................................................................................................................. 34
4.9.3 SpaceWire ............................................................................................................................................ 36
4.10 FMC+ connector ...........................................................................................................................................37
Revision information ......................................................................................................................................................42
Disclaimer........................................................................................................................................................................43
Appendix A......................................................................................................................................................................44
Appendix B......................................................................................................................................................................45
Appendix C......................................................................................................................................................................46

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GR740-MINI
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List of Figures
Figure 3-1 GR740-MINI Development board.............................................................................................. 6
Figure 4-1 Top view of GR740-MINI board ................................................................................................. 8
Figure 4-2 GR740-MINI Board block Diagram............................................................................................. 9
Figure 4-3 USB-C connector for power supply soluon............................................................................ 10
Figure 4-4 Jumper Conguraon .............................................................................................................. 11
Figure 4-5 LED(1-3) board placement....................................................................................................... 11
Figure 4-6 Power Regulaon Scheme....................................................................................................... 12
Figure 4-7 Implementaon of voltage sequencer.................................................................................... 14
Figure 4-8 GR740 SOC Block Diagram....................................................................................................... 15
Figure 4-9 GR740 Package ........................................................................................................................ 15
Figure 4-10 Bootstrap signals ..................................................................................................................... 16
Figure 4-11 LED(4 -10) board placement.................................................................................................... 18
Figure 4-12 GR740 Clock Distribuon scheme ........................................................................................... 20
Figure 4-13 Implementaon for SDRAM..................................................................................................... 21
Figure 4-14 Implementaon of PROM memory ......................................................................................... 22
Figure 4-15 ETH0 implementaon.............................................................................................................. 23
Figure 4-16 GPIO for GR740........................................................................................................................ 24
Figure 4-17 CertusPro-NX implementaon ................................................................................................ 25
Figure 4-18 Programming the FPGA ........................................................................................................... 26
Figure 4-19 LED(11-15) and D8 board placement ...................................................................................... 27
Figure 4-20 SPI Flash implementaon ........................................................................................................ 28
Figure 4-21 CertusPro-NX Clock Distribuon scheme ................................................................................ 29
Figure 4-22 CertusPro-NX DDR3 memory implementaon........................................................................ 30
Figure 4-23 Ethernet implementaon ........................................................................................................ 31
Figure 4-24 SerDes implementaon........................................................................................................... 32
Figure 4-25 PCI interface............................................................................................................................. 33
Figure 4-26 GMII/MII Intercommunicaon ................................................................................................ 34
Figure 4-27 SpaceWire Implementaon on the FPGA................................................................................ 36
Figure 4-28 SpaceWire Implementaon on the GR740.............................................................................. 36
Figure 4-29 FMC+ connector scheme......................................................................................................... 37
List of Tables
Table 4-1 Power and status LED .................................................................................................................. 11
Table 4-2 Voltages ....................................................................................................................................... 13
Table 4-3 FTDI Port assignment................................................................................................................... 13
Table 4-4 Default bootstrap values ............................................................................................................. 17
Table 4-5 LED correspond the GR740.......................................................................................................... 18
Table 4-6 LED correspond the CertusPro-NX............................................................................................... 27
Table 4-7 Shared pins on GR740 for PCI and Ethernet interface................................................................. 34
Table 4-8 Pinout for FMC+ connector ......................................................................................................... 38

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GR740-MINI
GR740-MINI-UM
Dec 2023, Version 1.1
1 INTRODUCTION
1.1 Purpose and Scope of the Document
This document provides a User’s Manual and interface document for the GR740-MINI development board.
The work has been performed at Frontgrade Gaisler AB, Gothenburg, Sweden.
1.2 Reference Documents
The following documents are referred as they contain relevant informaon:
[RD1] GR740MINI-QSG.pdf, Quick Start Guide, available from
https://www.gaisler.com/gr740-mini
[RD2] “GR740 user manual and data sheet”, available from
https://www.gaisler.com/GR740
[RD3] GRMON3 User Manual, available from https://www.gaisler.com/GRMON3
[RD4] “CertusPro-NX Family, Data Sheet”, Document number: FPGA-DS-02086
available from https://www.latticesemi.com
[RD5] “sysCONFIG User Guide for Nexus Platform, Technical Note”, Document
number: FPGA-TN-02099-2.5, available from https://www.latticesemi.com/
[RD6] “CertusPro-NX High-Speed I/O Interface, Technical Note”, Document number:
FPGA-TN-02244-1.1, available from https://www.latticesemi.com/

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GR740-MINI
GR740-MINI-UM
Dec 2023, Version 1.1
2 ABBREVIATIONS
AHB
Advanced High-performance bus, part of [AMBA]
AMBA
Advanced Microcontroller Bus Architecture
APB
Advanced Peripheral Bus, part of [AMBA]
DDR3
Double Data Rate
DSU
Debug Support Unit
EDAC
Error Detection and Correction
ESD
Electro-Static Discharge
FMC
FPGA Mezzanine Card
FPGA
Field Programmable Logic Array
FTDI
Future Technology Devices International
GMII
Gigibit Media Independent Interface
GPIO
General Purpose Input / Output
HCSL
High speed Current Steering Logic
HPC
High Pin Count
I2C
Inter-Integrated Circuit
IP
Intellectual Property
JTAG
Joint Test Action Group
LPC
Low Pin Count
LVDS
Low-Voltage Differential Signaling
MII
Media Independent Interface
SDRAM
Random Access Memory
SPI
Serial Peripheral Interface
PCB
Printed Circuit Board
PCI
Peripheral Component Interconnect
PHY
Physical Layer Device
PLL
Phase Locked Loop
PROM
Programmable Read Only Memory
UART
Universal Asynchronous Receiver Transmitter
USB
Universal Serial Bus

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GR740-MINI
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3 GR740-MINI-BOARD DESIGN
3.1 Overview
This document describes the design and implementaon of the GR740-MINI board. There is also a Quick
Start Guide [RD1] available, describing used commands and syntax etc. for debugging and development.
The GR740-MINI board is a compact evaluaon plaorm built around the Frontgrade GR740 quad-core
LEON4FT SPARC V8 processor and Lace Semiconductor FPGA CertusPro-NX. The board is designed with
mulple electrical funcons and interfaces with gives the user a exibility to interact with the board.
Figure 3-1 GR740-MINI Development board

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GR740-MINI
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The board contains the following main items.
•2 x USB-C connectors for debug and power
•GR470 Processor
o1 x USB interface via FTDI FT4232 providing JTAG and UART
o1 x Ethernet for communicaon and debug
o4 x SpaceWire channels to FMC+ connector
o256MB SDRAM
o128MB FLASH
•CertusPro-NX FPGA
o1 x USB interface via FTDI FT4232 providing JTAG and UART
o1 x Ethernet for communicaon and debug
o4 x SerDes to FMC+ connector
oLVDS to FMC+ connector
o3V3 IO to FMC+ connector
oI2C link to FMC+ connector
o1GB DDR3 memory
o512Mb SPI FLASH
•Intercommunicaon between GR740 and CertusPro-NX
oPCI link (32bit, 33MHz)
oGMII/MII
o4 x SpaceWire channels
3.2 Handling
This unit contains sensive electronic components which can be damaged by Electrostac Discharges (ESD).
When handling or installing the unit observe appropriate precauons and ESD safe pracces.
When not in use, store the unit in an electrostac protecve container or bag.
When conguring the jumpers on the board, or connecng/disconnecng cables, ensure that the unit is in
an un-powered state.
When operang the board in a 'stand-alone' conguraon, the power supply should be current limited to
prevent damage to the board or power supply in the event of an overcurrent situaon.
This equipment has SpaceWire ports that use Low Voltage Dierenal Signalling (LVDS) which has limited
common mode voltage protecon. To avoid damage to the SpaceWire interfaces due to common mode
voltage see secon 4.10 FMC+ connector

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4 BOARD DESIGN
This secon describes the board design in detail. The electrical funcons and interfaces that are common
for both the devices (the processor and the FPGA) are described in the rst secons: 4.1 to 4.6. In secon
4.7 and 4.8 each device and corresponding funcons/interfaces are described. The intercommunicaon be-
tween the devices is described in secon 4.9 and the FMC+ connector in secon 4.10.
Note: This design is not aimed for ight and should not be used as a reference design.
Figure 4-1 Top view of GR740-MINI board
Figure 4-1 shows the top view for the GR740-MINI board and is marked with interacons and indicaons.
For a more detailed assembly drawing referring to Appendix A & B.

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4.1 Board block diagram
The GR740-MINI Development Board provides the electrical funcons and interfaces as represented in the
block diagram in Figure 4-2.
Figure 4-2 GR740-MINI Board block Diagram
There are mulple ways to communicate with the board, in Figure 4-2 the interfaces are represented as
grey boxes and described shortly below.
1. USB 2.0: The USB 2.0 link is connected to a FTDI chip that converts the USB-data into four serial out-
puts (2 x JTAG and 2 x UART) connected to both the FPGA and Processor. USB 2.0 interface is con-
nected to connector J2.
2. Ethernet: Both MII and GMII interface are supported by the FPGA and processor through J3.Where
J3A is to CertusPro-NX and J3B to the GR740.
3. FMC+ connector: the usage of the FMC+ connector is dependent on an external mezzanine board.
In this design the FMC+ connector provides the GR740 with four SpaceWire channels and the Cer-
tusPro-NX with SerDes LVDS, I2C and GPIO 3V3.

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4.2 Power the board
The GR740-MINI board is powered using either of the USB-C connectors (J1 or J2). Therefor there are two
ways to power supply the board and which is accomplished by aaching a 2-pin jumper to the 3-pin head
(JP5), see Figure 4-3
The overall power requirement for the board is 15W. J2 is considered as the main power supply, and the
conguraon jumper is set to this as default (JP5: 1-2). This can be used when communicang with USB-C
(data and power through the same cable), Ethernet or FMC+ connector. The USB-C source must handle at
least 3A, 5V (15W). J2 must be inserted to start up the board since the D_N/P signals are needed to the FTDI
chip see Figure 4-3.
There is only one excepon when there is need to use J1 as power source. This is when the user is com-
municang with USB and the USB-source (for example a computer or a docking staon) cannot handle the
power requirements. Then, the users need to have an external power source connected to J1 and the data
to J2, this conguraon is chosen when seng jumper in JP5: 2-3 mode.
Figure 4-3 USB-C connector for power supply solution
Note: that the source (for example a computer, charger or docking staon) used in this case must have
a USB-C connector that can deliver at least 3A, 5V (15W). Observe that not all sources with USB-C
sockets support that. Check the sources manual before connecng to the GR740-MINI board.

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4.3 Interacting with the board
As menoned in secon 4.2 there are two ways to power supply the board, by seng a conguraon
jumper. This conguraon jumper is shown in Figure 4-4.
Figure 4-4 Jumper Configuration
On the board there are three LED for indicang power availability and communicaon status, see Table 4-1
for more informaon and Figure 4-5 for the board placement.
Table 4-1 Power and status LED
LED
Colour
Comment
LED1
Green
Indicates that 3V3 is available
LED2
Red
Light when USB is in suspended mode
LED3
Green
Indicate normal operaonal mode.
Figure 4-5 LED(1-3) board placement

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4.4 Power supplies
A block diagram showing the power supply design for the GR740-MINI board is shown in Figure 4-6. Since
this board is power supplied through USB the FTDI chip that handles the communicaon via USB is powered
up rst via a dedicated voltage. A GPIO from the FTDI chip goes HIGH aer the handshake is performed with
OK result. This signal enables the rest of the power supplies through a voltage sequencer. The voltage se-
quencer (MAX16027TP+) will enable the dierent voltages in specic order with a xed me delay set by an
external capacitor. The enable signals are depending on the previous voltage supplies power-good (output)
signal. The voltage sequence is designed to full the power-up requirements for the GR740. The FPGA do
not have any power up requirements and is enabled aerwards. Figure 4-7 shows the implementaon for
the voltage sequencer.
For most voltages switched point of load DC/DC converters are used. The type of DC/DC converters
(LMZ21701, MPM3630 & MPM3620) are chosen because they are small, can supply the required currents
and have integrated inductors. For the GR740 PLL voltage an ultra-low noise low drop out regulator (LDO)
(TPS79601) is used
To achieve the right power setup to the DDR3 memory interface a dedicated DDR3 terminaon circuit
(TPS51200) is used.
Figure 4-6 Power Regulation Scheme

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Table 4-2 below list the different voltages for the GR740-MINI board with their main users.
Table 4-2 Voltages
Voltage
Main users
FTDI_3V46
FTDI chip, EPROM
FTDI_3V3
FTDI chip
3V3
Oscillator, Clock buffer, Processor (GR740), FLASH memory,
SDRAM, Ethernet PHY, SPI FLASH, FPGA (CertusPro-NX)
3PV3
FMC+ Connector
3PV3AUX
FMC+ Connector
2V5
FPGA (CertusPro-NX), Processor (GR740)
1V8
FPGA (CertusPro-NX)
1V5
FPGA (CertusPro-NX), DDR3 Termination, DDR3 Memory
1V2
Ethernet PHY, Processor (GR740)
1V2_PLL
Processor (GR740)
1V0
FPGA (CertusPro-NX)
VADJ (1.8V)
FMC+ Connector , FPGA (CertusPro-NX)
4.5 FTDI chip
The GR740-MINI board provides Serial to USB interface chip, FT4232HPQ from FTDI, which provides up to 4
serial ports connect to a single USB-C connector (J2). The FTDI chip is connected to both the GR740 and the
CertusPro-NX with JTAG and/or UART, see Table 4-3 for the port assignments. There is an EEPROM con-
nected to the FTDI chip aimed for conguraon. A separate 12 MHz crystal is dedicated for the FTDI chip.
See the Quick Start Guide [RD1] for more informaon about usage.
Table 4-3 FTDI Port assignment
Port
Funcon
Target
A
JTAG
GR740
B
JTAG
CertusPro-NX
C
UART
GR740
D
UART
CertusPro-NX

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4.6 Reset
The reset signal is acve low and is connected to the processor GR740, FPGA CertusPro-NX, PROM memory,
Ethernet PHY (GR740), Ethernet PHY (CertusPro-NX) and it is derived from the voltage sequencer. Figure 4-7
shows the implementaon for the voltage sequencer. The reset signal is held low by the sequencer unl all
the enable (output) signals are high. The reset signal is controlled by a master-reset (input) signal. This sig-
nal is also acve low and have a pull-up resistor connected to it. The watchdog signal from the GR740 is
connected to the master-reset signal through a jumper, by default this is disabled, refer to secon 4.7.5 for
more informaon. There is also a switch (SW1) to the master-reset signal for manually reset the board, see
Figure 4-1 for placement.
Figure 4-7 Implementation of voltage sequencer

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4.7 GR740 Processor
The Frontgrade Gaisler GR740 processor is a radiaon-hard system-on- chip featuring a quad-core fault-tol-
erant LEON4 SPARC V8 processor, and a set of IP cores connected through AMBA AHB/APB buses as repre-
sented in the Figure 4-8.
Figure 4-8 GR740 SOC Block Diagram
The details for the interfaces, operaon, and programming of the GR740 processor are given in [RD2].
This GR740 processor is packaged in a 625-pin, 1mm pitch plasc Ball Grid Array package (27 x 27 mm).
Figure 4-9 GR740 Package

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4.7.1 Bootstrap signals
The power-up and inialisaon state for the GR740 is aected by several external signals. A number of
GPIO:s and funcon pins are predened for this purpose. To set the desired seng a pull-up or pull-down
resistors are used to set the signal to HIGH or LOW. For more detailed informaon about the bootstrap sig-
nals see secon 3.1 in GR740 User Manual [RD2].
As shown in Figure 4-10 there are opons to change most of the bootstrap values since there are addional
not mounted resistors in the schemac.
Figure 4-10 Bootstrap signals
The default conguraon for those signals in the GR740-MINI design is shown in Table 4 3.

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Table 4-4 Default bootstrap values
Bootstrap signal
Pin
Default
Descripon
DSU_EN
D18
HIGH
Enables the Debug Support Unit (DSU)
BREAK
D17
LOW
Puts all processors in debug mode when asserted
PCIMODE_ENABLE
B21
HIGH
Enables PCI mode.
MEM_IFWIDTH
C20
HIGH
Selects the half width SDRAM interface
MEM_CLKSEL
E16
HIGH
Set external source to the memory clock.
GPIO[0]
A21
LOW
Sets the IP and MAC address for Ethernet Debug Com-
municaon Link.
GPIO[1]
C18
LOW
GPIO[2]
B20
LOW
GPIO[3]
C17
LOW
GPIO[4]
A20
LOW
GPIO[5]
D16
LOW
GPIO[6]
B19
LOW
Selects SpaceWire router Distributed Interrupt cong-
uraon: Interrupts with acknowledgment mode (32 in-
terrupts with acknowledgments)
GPIO[7]
B17
LOW
GPIO[8]
A19
HIGH
Ethernet Debug Communicaon Link routed over the
Debug AHB bus
GPIO[9]
C16
HIGH
GPIO[10]
B18
LOW
Selects the PROM width to 8-bit.
GPIO[11]
D15
LOW
The SpaceWire router is not disabled aer reset
GPIO[12]
A18
LOW
Sets the two least signicant bits of the SpaceWire
router’s instance ID.
GPIO[13]
C15
LOW
GPIO[14]
A17
LOW
Disable EDAC of the PROM area
GPIO[15]
D14
LOW
Enables PROM/IO aer reset
PLL_BYPASS[0]
A22
LOW
Bypass PLL and use clock input directly. 2: SpW clock,
1: SDRAM clock, 0: System clock PLL bypass.
PLL_BYPASS[1]
B22
LOW
PLL_BYPASS[2]
E17
LOW
PLL_IGNLOCK
B23
LOW
The PLL outputs of the device are gated unl the PLL
lock outputs have been asserted.
4.7.2 Debugging
In this design the debugging interfaces that are provided are JTAG and Ethernet (EDCL). Program download
and debugging to the processor is performed using the GRMON3 Debug Monitor tool from Frontgrade
Gaisler [RD3]. For more informaon about the debugging referring to the GRMON3 documentaon [RD3]
and the Quick Start Guide [RD1]
There are three debug control signals.
1. DSU_EN (input): This signal is a bootstrap signal which is pulled high on the board to enable debug-
ging.
2. BREAK (input): This signal puts all processors in debug mode when asserted while DSU_EN is HIGH.
On this board the signal is pull-down and connected to pin ADBUS7 on the FTDI chip, this feature
allows GRMON to break the reset-loop by the ag -digpio

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GR740-MINI
GR740-MINI-UM
Dec 2023, Version 1.1
3. DSU_ACTIVE (output): When the processor is halted.
4.7.3 LED
On the board there are LEDs corresponds to the GR740, see Table 4-5 for more informaon and Figure 4-11
for the board placement.
Table 4-5 LED correspond the GR740
LED
Colour
Comment
LED4
Green
Connected to DSU_ACTIVE, indicates when debug support unit is acve.
LED5
Red
Connected to PROC_ERRORN signal, will indicate when processor 0 en-
ters error mode.
LED6
Red
Connected to WDOGN, for more informaon see secon 4.7.5
LED7
Green
Connected to GPIO2[5]
LED8
Green
Connected to GPIO2[6]
LED9
Green
Connected to GPIO2[7]
LED10
Green
Connected to GPIO2[8]
Figure 4-11 LED(4 -10) board placement
4.7.4 JTAG
GR740 supports JTAG interface for debugging. This link is accessible via J2 (USB-C) through the FTDI chip.

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GR740-MINI
GR740-MINI-UM
Dec 2023, Version 1.1
4.7.5 WDOGN
The GR740 processor includes a Watchdog mer funcon which can be used for the purpose of generang
a system reset in the event of a soware malfuncon or crash. To ulise the Watchdog feature, it is neces-
sary to appropriately set-up and enable the Watchdog mer. Please consult the GR740 processor User Man-
ual [RD2] for the correct register locaons and details. On this development board the WDOGN signal is
connected to the master-resetn on the voltage sequencer via a jumper, see Figure 4-7. More informaon
about the reset funconality refer to secon 4.6. By default, the jumper (JP2) is not installed so the watch-
dog mer funcon is disabled, to enable this funcon the jumper needs to be installed.
For soware development it is oen convenient or necessary to disable the Watchdog triggering to be able
to easily debug without interference from the Watchdog operaon. In this case, the jumper should not be
installed. If the watchdog triggers when the jumper is not installed, no system reset will occur, but the
Watchdog LED, LED6 will sll illuminate.

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GR740-MINI
GR740-MINI-UM
Dec 2023, Version 1.1
4.7.6 Oscillators and clock input
Figure 4-12 shows the oscillator and clocks scheme for the GR740. For more details of the internal PLL struc-
ture, clock gang and mulplexing features of the GR740, see secon 4 in the GR740 User Manual [RD2].
Figure 4-12 GR740 Clock Distribution scheme
The system clock (SYS_CLK), memory interface clock (MEM_EXTCLK) and the SpaceWire clock (SPW_CLK)
are all separate inputs on the GR740 with a frequency of 50MHz. The signals originate from the same clock
but are buered through a high-performance, low-skew clock buer (LMK1C1104) with separate outputs.
The GR740_PCI_CLK originates from a 33MHz oscillator and is also buered.
When Ethernet is in GMII mode the 125MHz clock is buered (LMK1C1104) into the GR740 (ETH0_GTXCLK)
and to the Ethernet PHY (transmit reference clock). Due to the output delay in the GR740 on transmier
clock the signals need to be a skewed from each other. Therefor the clock signal to the Ethernet PHY is de-
layed with 1ns in the layout. The Ethernet PHY also has a feature to skew the signal, and this can be used to
tune the skewing. The ETH0_RXCLK frequency is 125MHz and is derived from the Ethernet PHY.
In MII mode the ETH0_GTXCLK is not used. The ETH0_RXCLK and ETH0_TXCLK frequency are 25MHz and
derived from the Ethernet PHY.
The PHY uses an external crystal of 25MHz.
Due to limitaons in the driving strength of the output clock signal MEM_CLK_OUT, this signal is needed to
be externally buered (LMK1C1104) to signal MEM_CLK_IN_0 and MEM_CLK_IN_1 back to itself as an input
and to the SDRAM.
The JTAG_CLK is derived from the FTDI chip, which has an external crystal of 12MHz.