Fujitsu MB90390 Series User manual

FUJITSU MICROELECTRONICS
CONTROLLER MANUAL
F
2
MC-16LX
16-BIT MICROCONTROLLER
MB90390 Series
HARDWARE MANUAL
CM44-10122-4E

FUJITSU MICROELECTRONICS LIMITED
F
2
MC-16LX
16-BIT MICROCONTROLLER
MB90390 Series
HARDWARE MANUAL
The information for microcontroller supports is shown in the following homepage.
Be sure to refer to the "Check Sheet" for the latest cautions on development.
"Check Sheet" is seen at the following support page
"Check Sheet" lists the minimal requirement items to be checked to prevent problems beforehand in system development.
http://edevice.fujitsu.com/micom/en-support/

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PREFACE
■Objectives and intended reader
Thank you very much for your continued patronage of Fujitsu semiconductor products.
The MB90390 series has been developed as a general-purpose version of the F2MC-16LX series,
which is an original 16-bit single-chip microcontroller compatible with the Application Specific IC
(ASIC).
This manual explains the functions and operation of the MB90390 series for designers who actually
use the MB90390 series to design products. Please read this manual first.
Note: F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
■Trademark
The company names and brand names herein are the trademarks or registered trademarks of their
respective owners.
■License
Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use,
these components in an I2C system provided that the system conforms to the I2C Standard
Specification as defined by Philips.
■Structure of this preliminary manual
CHAPTER 1 OVERVIEW
The MB90390 Series is a family member of the F2MC-16LX microcontrollers.
CHAPTER 2 CPU
This chapter explains the CPU.
CHAPTER 3 INTERRUPTS
This chapter explains the functions and operations of the interrupt and extended intelligent I/O
service (EI2OS) for MB90390 series.
CHAPTER 4 DELAYED INTERRUPT
This chapter explains the functions and operations of the delayed interrupt.
CHAPTER 5 CLOCKS
This chapter describes the clocks used by MB90390 series microcontrollers.
CHAPTER 6 CLOCK MODULATOR
This chapter provides an overview of the Clock Modulator and its features. It describes the
register structure and operation of the Clock Modulator.
CHAPTER 7 RESETS
This chapter describes resets for the MB90390 series microcontrollers.

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CHAPTER 8 LOW-POWER CONTROL CIRCUIT
This chapter explains the functions and operations of the low-power control circuits.
CHAPTER 9 MEMORY ACCESS MODES
This chapter explains the functions and operations of the memory access modes.
CHAPTER 10 I/O PORTS
This chapter explains the functions and operations of the I/O ports.
CHAPTER 11 TIME-BASE TIMER
This chapter explains the functions and operations of the time-base timer.
CHAPTER 12 WATCHDOG TIMER
This chapter explains the functions and operations of the watchdog timer.
CHAPTER 13 16-BIT I/O TIMER
This chapter explains the functions and operations of the 16-bit I/O timer.
CHAPTER 14 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
This chapter explains the functions and operations of the 16-bit reload timer (with the event
count function).
CHAPTER 15 WATCH TIMER
This chapter explains the functions and operations of the Watch Timer.
CHAPTER 16 8/16-BIT PPG
This chapter explains the 8/16-bit PPG and explains its functions.
CHAPTER 17 DTP/EXTERNAL INTERRUPTS
This chapter explains the functions and operations of the DTP/external interrupts.
CHAPTER 18 8/10-BIT A/D CONVERTER
This chapter describes the functions and operation of the 8/10-bit A/D converter.
CHAPTER 19 UART0, UART1
This chapter explains the UART0, UART1 functions and operations.
CHAPTER 20 UART2, UART3
This chapter explains the functions and operation of UART2, UART3.
CHAPTER 21 400 kHz I2C INTERFACE
This section describes the functions and operation of the fast I2C interface.
CHAPTER 22 SERIAL I/O
This chapter explains the functions and operations of the serial I/O.
CHAPTER 23 CAN CONTROLLER
This chapter explains the functions and operations of the CAN controller.
CHAPTER 24 STEPPING MOTOR CONTROLLER
This chapter explains the functions and operations of the stepping motor controller.
CHAPTER 25 SOUND GENERATOR
This chapter explains the functions and operations of the sound generator.

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CHAPTER 26 ADDRESS MATCH DETECTION FUNCTION
This chapter explains the address match detection function and operation.
CHAPTER 27 ROM MIRRORING MODULE
This chapter explains the ROM mirroring module.
CHAPTER 28 3M-BIT FLASH MEMORY
This chapter explains the functions and operation of the 3M-bit flash memory.
CHAPTER 29 EXAMPLES OF SERIAL PROGRAMMING CONNECTION
This chapter provides examples of F2MC-16LX MB90F394H(A) serial programming connection.
APPENDIX
The appendixes provide I/O maps, instructions, and other information.

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Copyright ©2007-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved.
• The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
• The information, such as descriptions of function and application circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU
MICROELECTRONICS does not warrant proper operation of the device with respect to use based on such information. When
you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of
such use of the information. FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of
the use of the information.
• Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU
MICROELECTRONICS or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-
party's intellectual property right or other right by using such information. FUJITSU MICROELECTRONICS assumes no
liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of
information contained herein.
• The products described in this document are designed, developed and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured,
could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss
(i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life
support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible
repeater and artificial satellite).
Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or
damages arising in connection with above-mentioned uses of the products.
• Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
• Exportation/release of any products described in this document may require necessary procedures in accordance with the
regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
• The company names and brand names herein are the trademarks or registered trademarks of their respective owners.

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CONTENTS
CHAPTER 1 OVERVIEW ................................................................................................... 1
1.1 Product Overview ............................................................................................................................... 2
1.2 Features .............................................................................................................................................. 3
1.3 Block Diagram of MB90V390H ........................................................................................................... 6
1.4 Block Diagram of MB90V390HA/MB90V390HB ................................................................................. 7
1.5 Block Diagram of MB90394HA/MB90F394H(A) ................................................................................. 8
1.6 Pin Assignment ................................................................................................................................... 9
1.7 Package Dimensions ........................................................................................................................ 12
1.8 Pin Functions .................................................................................................................................... 13
1.9 Input-Output Circuits ......................................................................................................................... 19
1.10 Handling Device ................................................................................................................................ 22
CHAPTER 2 CPU ............................................................................................................ 25
2.1 Outline of the CPU ............................................................................................................................ 26
2.2 Memory Space .................................................................................................................................. 27
2.3 Memory Space Map .......................................................................................................................... 30
2.4 Linear Addressing ............................................................................................................................. 32
2.5 Bank Addressing Types .................................................................................................................... 33
2.6 Multi-byte Data in Memory Space ..................................................................................................... 35
2.7 Registers ........................................................................................................................................... 36
2.7.1 Accumulator (A) ........................................................................................................................... 39
2.7.2 User Stack Pointer (USP) and System Stack Pointer (SSP) ....................................................... 40
2.7.3 Processor Status (PS) ................................................................................................................. 41
2.7.4 Program Counter (PC) ................................................................................................................. 44
2.8 Register Bank ................................................................................................................................... 45
2.9 Prefix Codes ..................................................................................................................................... 47
2.10 Interrupt Disable Instructions ............................................................................................................ 49
2.11 Precautions for Use of "DIV A, Ri" and "DIVW A, RWi" Instructions ................................................ 51
CHAPTER 3 INTERRUPTS ............................................................................................. 53
3.1 Outline of Interrupts .......................................................................................................................... 54
3.2 Interrupt Vector ................................................................................................................................. 57
3.3 Interrupt Control Registers (ICR) ...................................................................................................... 59
3.4 Interrupt Flow .................................................................................................................................... 62
3.5 Hardware Interrupts .......................................................................................................................... 64
3.5.1 Hardware Interrupt Operation ...................................................................................................... 65
3.5.2 Occurrence and Release of Hardware Interrupt .......................................................................... 66
3.5.3 Multiple interrupts ........................................................................................................................ 68
3.6 Software Interrupts ........................................................................................................................... 69
3.7 Extended Intelligent I/O Service (EI2OS) .......................................................................................... 71
3.7.1 Extended Intelligent I/O Service Descriptor (ISD) ....................................................................... 73
3.7.2 EI2OS Status Register (ISCS) ..................................................................................................... 75
3.8 Operation Flow of and Procedure for Using the Extended Intelligent I/O Service (EI2OS) .............. 77

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3.9 Exceptions ........................................................................................................................................ 80
CHAPTER 4 DELAYED INTERRUPT ............................................................................. 81
4.1 Outline of Delayed Interrupt Module ................................................................................................. 82
4.2 Delayed Interrupt Register ................................................................................................................ 83
4.3 Delayed Interrupt Operation ............................................................................................................. 84
CHAPTER 5 CLOCKS ..................................................................................................... 85
5.1 Clocks ............................................................................................................................................... 86
5.2 Block Diagram of the Clock Generation Block .................................................................................. 89
5.3 Clock Selection Registers ................................................................................................................. 91
5.3.1 Clock Selection Register (CKSCR) ............................................................................................. 92
5.3.2 PLL and Special Configuration Control Register (PSCCR) ......................................................... 95
5.4 Clock Mode ....................................................................................................................................... 97
5.5 Oscillation Stabilization Wait Time .................................................................................................. 100
5.6 Connection of an Oscillator or an External Clock to the Microcontroller ......................................... 101
5.7 Output of the main clock HCLK and HCLKX .................................................................................. 103
CHAPTER 6 CLOCK MODULATOR ............................................................................. 105
6.1 Overview of Clock Modulator .......................................................................................................... 106
6.2 Register Description of Clock Modulator ........................................................................................ 107
6.3 Registers of Clock Modulator .......................................................................................................... 108
6.3.1 Clock Modulator Control Register (CMCR) ............................................................................... 109
6.3.2 Clock Modulation Parameter Register (CMPR) ......................................................................... 114
6.4 Application Note of the Clock Modulator ......................................................................................... 121
CHAPTER 7 RESETS .................................................................................................... 125
7.1 Resets ............................................................................................................................................. 126
7.2 Reset Cause and Oscillation Stabilization Wait Times ................................................................... 128
7.3 External Reset Pin .......................................................................................................................... 130
7.4 Reset Operation .............................................................................................................................. 131
7.5 Reset Cause Bits ............................................................................................................................ 133
7.6 Status of Pins in a Reset ................................................................................................................ 136
CHAPTER 8 LOW-POWER CONTROL CIRCUIT ........................................................ 137
8.1 Overview of Low-Power Consumption Mode .................................................................................. 138
8.2 Block Diagram of the Low-Power Consumption Control Circuit ..................................................... 141
8.3 Low-Power Consumption Mode Control Register (LPMCR) ........................................................... 143
8.4 CPU Intermittent Operation Mode .................................................................................................. 147
8.5 Standby Mode ................................................................................................................................. 148
8.5.1 Sleep Mode ............................................................................................................................... 149
8.5.2 Time-base Timer Mode ............................................................................................................. 151
8.5.3 Stop Mode ................................................................................................................................. 153
8.6 Status Change Diagram ................................................................................................................. 156
8.7 Status of Pins in Standby Mode and during Reset ......................................................................... 158
8.8 Usage Notes on Low-Power Consumption Mode ........................................................................... 159