Fujitsu MB90390 Series User manual

FUJITSU MICROELECTRONICS
CONTROLLER MANUAL
F
2
MC-16LX
16-BIT MICROCONTROLLER
MB90390 Series
HARDWARE MANUAL
CM44-10122-4E

FUJITSU MICROELECTRONICS LIMITED
F
2
MC-16LX
16-BIT MICROCONTROLLER
MB90390 Series
HARDWARE MANUAL
The information for microcontroller supports is shown in the following homepage.
Be sure to refer to the "Check Sheet" for the latest cautions on development.
"Check Sheet" is seen at the following support page
"Check Sheet" lists the minimal requirement items to be checked to prevent problems beforehand in system development.
http://edevice.fujitsu.com/micom/en-support/

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PREFACE
■Objectives and intended reader
Thank you very much for your continued patronage of Fujitsu semiconductor products.
The MB90390 series has been developed as a general-purpose version of the F2MC-16LX series,
which is an original 16-bit single-chip microcontroller compatible with the Application Specific IC
(ASIC).
This manual explains the functions and operation of the MB90390 series for designers who actually
use the MB90390 series to design products. Please read this manual first.
Note: F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
■Trademark
The company names and brand names herein are the trademarks or registered trademarks of their
respective owners.
■License
Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use,
these components in an I2C system provided that the system conforms to the I2C Standard
Specification as defined by Philips.
■Structure of this preliminary manual
CHAPTER 1 OVERVIEW
The MB90390 Series is a family member of the F2MC-16LX microcontrollers.
CHAPTER 2 CPU
This chapter explains the CPU.
CHAPTER 3 INTERRUPTS
This chapter explains the functions and operations of the interrupt and extended intelligent I/O
service (EI2OS) for MB90390 series.
CHAPTER 4 DELAYED INTERRUPT
This chapter explains the functions and operations of the delayed interrupt.
CHAPTER 5 CLOCKS
This chapter describes the clocks used by MB90390 series microcontrollers.
CHAPTER 6 CLOCK MODULATOR
This chapter provides an overview of the Clock Modulator and its features. It describes the
register structure and operation of the Clock Modulator.
CHAPTER 7 RESETS
This chapter describes resets for the MB90390 series microcontrollers.

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CHAPTER 8 LOW-POWER CONTROL CIRCUIT
This chapter explains the functions and operations of the low-power control circuits.
CHAPTER 9 MEMORY ACCESS MODES
This chapter explains the functions and operations of the memory access modes.
CHAPTER 10 I/O PORTS
This chapter explains the functions and operations of the I/O ports.
CHAPTER 11 TIME-BASE TIMER
This chapter explains the functions and operations of the time-base timer.
CHAPTER 12 WATCHDOG TIMER
This chapter explains the functions and operations of the watchdog timer.
CHAPTER 13 16-BIT I/O TIMER
This chapter explains the functions and operations of the 16-bit I/O timer.
CHAPTER 14 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
This chapter explains the functions and operations of the 16-bit reload timer (with the event
count function).
CHAPTER 15 WATCH TIMER
This chapter explains the functions and operations of the Watch Timer.
CHAPTER 16 8/16-BIT PPG
This chapter explains the 8/16-bit PPG and explains its functions.
CHAPTER 17 DTP/EXTERNAL INTERRUPTS
This chapter explains the functions and operations of the DTP/external interrupts.
CHAPTER 18 8/10-BIT A/D CONVERTER
This chapter describes the functions and operation of the 8/10-bit A/D converter.
CHAPTER 19 UART0, UART1
This chapter explains the UART0, UART1 functions and operations.
CHAPTER 20 UART2, UART3
This chapter explains the functions and operation of UART2, UART3.
CHAPTER 21 400 kHz I2C INTERFACE
This section describes the functions and operation of the fast I2C interface.
CHAPTER 22 SERIAL I/O
This chapter explains the functions and operations of the serial I/O.
CHAPTER 23 CAN CONTROLLER
This chapter explains the functions and operations of the CAN controller.
CHAPTER 24 STEPPING MOTOR CONTROLLER
This chapter explains the functions and operations of the stepping motor controller.
CHAPTER 25 SOUND GENERATOR
This chapter explains the functions and operations of the sound generator.

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CHAPTER 26 ADDRESS MATCH DETECTION FUNCTION
This chapter explains the address match detection function and operation.
CHAPTER 27 ROM MIRRORING MODULE
This chapter explains the ROM mirroring module.
CHAPTER 28 3M-BIT FLASH MEMORY
This chapter explains the functions and operation of the 3M-bit flash memory.
CHAPTER 29 EXAMPLES OF SERIAL PROGRAMMING CONNECTION
This chapter provides examples of F2MC-16LX MB90F394H(A) serial programming connection.
APPENDIX
The appendixes provide I/O maps, instructions, and other information.

iv
Copyright ©2007-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved.
• The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
• The information, such as descriptions of function and application circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU
MICROELECTRONICS does not warrant proper operation of the device with respect to use based on such information. When
you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of
such use of the information. FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of
the use of the information.
• Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU
MICROELECTRONICS or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-
party's intellectual property right or other right by using such information. FUJITSU MICROELECTRONICS assumes no
liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of
information contained herein.
• The products described in this document are designed, developed and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured,
could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss
(i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life
support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible
repeater and artificial satellite).
Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or
damages arising in connection with above-mentioned uses of the products.
• Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
• Exportation/release of any products described in this document may require necessary procedures in accordance with the
regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
• The company names and brand names herein are the trademarks or registered trademarks of their respective owners.

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CONTENTS
CHAPTER 1 OVERVIEW ................................................................................................... 1
1.1 Product Overview ............................................................................................................................... 2
1.2 Features .............................................................................................................................................. 3
1.3 Block Diagram of MB90V390H ........................................................................................................... 6
1.4 Block Diagram of MB90V390HA/MB90V390HB ................................................................................. 7
1.5 Block Diagram of MB90394HA/MB90F394H(A) ................................................................................. 8
1.6 Pin Assignment ................................................................................................................................... 9
1.7 Package Dimensions ........................................................................................................................ 12
1.8 Pin Functions .................................................................................................................................... 13
1.9 Input-Output Circuits ......................................................................................................................... 19
1.10 Handling Device ................................................................................................................................ 22
CHAPTER 2 CPU ............................................................................................................ 25
2.1 Outline of the CPU ............................................................................................................................ 26
2.2 Memory Space .................................................................................................................................. 27
2.3 Memory Space Map .......................................................................................................................... 30
2.4 Linear Addressing ............................................................................................................................. 32
2.5 Bank Addressing Types .................................................................................................................... 33
2.6 Multi-byte Data in Memory Space ..................................................................................................... 35
2.7 Registers ........................................................................................................................................... 36
2.7.1 Accumulator (A) ........................................................................................................................... 39
2.7.2 User Stack Pointer (USP) and System Stack Pointer (SSP) ....................................................... 40
2.7.3 Processor Status (PS) ................................................................................................................. 41
2.7.4 Program Counter (PC) ................................................................................................................. 44
2.8 Register Bank ................................................................................................................................... 45
2.9 Prefix Codes ..................................................................................................................................... 47
2.10 Interrupt Disable Instructions ............................................................................................................ 49
2.11 Precautions for Use of "DIV A, Ri" and "DIVW A, RWi" Instructions ................................................ 51
CHAPTER 3 INTERRUPTS ............................................................................................. 53
3.1 Outline of Interrupts .......................................................................................................................... 54
3.2 Interrupt Vector ................................................................................................................................. 57
3.3 Interrupt Control Registers (ICR) ...................................................................................................... 59
3.4 Interrupt Flow .................................................................................................................................... 62
3.5 Hardware Interrupts .......................................................................................................................... 64
3.5.1 Hardware Interrupt Operation ...................................................................................................... 65
3.5.2 Occurrence and Release of Hardware Interrupt .......................................................................... 66
3.5.3 Multiple interrupts ........................................................................................................................ 68
3.6 Software Interrupts ........................................................................................................................... 69
3.7 Extended Intelligent I/O Service (EI2OS) .......................................................................................... 71
3.7.1 Extended Intelligent I/O Service Descriptor (ISD) ....................................................................... 73
3.7.2 EI2OS Status Register (ISCS) ..................................................................................................... 75
3.8 Operation Flow of and Procedure for Using the Extended Intelligent I/O Service (EI2OS) .............. 77

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3.9 Exceptions ........................................................................................................................................ 80
CHAPTER 4 DELAYED INTERRUPT ............................................................................. 81
4.1 Outline of Delayed Interrupt Module ................................................................................................. 82
4.2 Delayed Interrupt Register ................................................................................................................ 83
4.3 Delayed Interrupt Operation ............................................................................................................. 84
CHAPTER 5 CLOCKS ..................................................................................................... 85
5.1 Clocks ............................................................................................................................................... 86
5.2 Block Diagram of the Clock Generation Block .................................................................................. 89
5.3 Clock Selection Registers ................................................................................................................. 91
5.3.1 Clock Selection Register (CKSCR) ............................................................................................. 92
5.3.2 PLL and Special Configuration Control Register (PSCCR) ......................................................... 95
5.4 Clock Mode ....................................................................................................................................... 97
5.5 Oscillation Stabilization Wait Time .................................................................................................. 100
5.6 Connection of an Oscillator or an External Clock to the Microcontroller ......................................... 101
5.7 Output of the main clock HCLK and HCLKX .................................................................................. 103
CHAPTER 6 CLOCK MODULATOR ............................................................................. 105
6.1 Overview of Clock Modulator .......................................................................................................... 106
6.2 Register Description of Clock Modulator ........................................................................................ 107
6.3 Registers of Clock Modulator .......................................................................................................... 108
6.3.1 Clock Modulator Control Register (CMCR) ............................................................................... 109
6.3.2 Clock Modulation Parameter Register (CMPR) ......................................................................... 114
6.4 Application Note of the Clock Modulator ......................................................................................... 121
CHAPTER 7 RESETS .................................................................................................... 125
7.1 Resets ............................................................................................................................................. 126
7.2 Reset Cause and Oscillation Stabilization Wait Times ................................................................... 128
7.3 External Reset Pin .......................................................................................................................... 130
7.4 Reset Operation .............................................................................................................................. 131
7.5 Reset Cause Bits ............................................................................................................................ 133
7.6 Status of Pins in a Reset ................................................................................................................ 136
CHAPTER 8 LOW-POWER CONTROL CIRCUIT ........................................................ 137
8.1 Overview of Low-Power Consumption Mode .................................................................................. 138
8.2 Block Diagram of the Low-Power Consumption Control Circuit ..................................................... 141
8.3 Low-Power Consumption Mode Control Register (LPMCR) ........................................................... 143
8.4 CPU Intermittent Operation Mode .................................................................................................. 147
8.5 Standby Mode ................................................................................................................................. 148
8.5.1 Sleep Mode ............................................................................................................................... 149
8.5.2 Time-base Timer Mode ............................................................................................................. 151
8.5.3 Stop Mode ................................................................................................................................. 153
8.6 Status Change Diagram ................................................................................................................. 156
8.7 Status of Pins in Standby Mode and during Reset ......................................................................... 158
8.8 Usage Notes on Low-Power Consumption Mode ........................................................................... 159

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CHAPTER 9 MEMORY ACCESS MODES .................................................................... 163
9.1 Outline of Memory Access Modes .................................................................................................. 164
9.2 Mode Pins of Memory Access Mode .............................................................................................. 165
9.3 Mode Data of Memory Access Mode .............................................................................................. 166
CHAPTER 10 I/O PORTS ................................................................................................ 169
10.1 I/O Ports .......................................................................................................................................... 170
10.2 I/O Port Registers ........................................................................................................................... 171
10.2.1 Port Data Register ..................................................................................................................... 172
10.2.2 Data Direction Register ............................................................................................................. 174
10.2.3 Analog Input Enable Register .................................................................................................... 175
10.2.4 Input Level Select Register ........................................................................................................ 176
CHAPTER 11 TIME-BASE TIMER .................................................................................. 177
11.1 Outline of Time-base Timer ............................................................................................................ 178
11.2 Time-base Timer Control Register .................................................................................................. 179
11.3 Operations of Time-base Timer ...................................................................................................... 181
CHAPTER 12 WATCHDOG TIMER ................................................................................ 183
12.1 Outline of Watchdog Timer ............................................................................................................. 184
12.2 Watchdog Timer Operation ............................................................................................................. 187
CHAPTER 13 16-BIT I/O TIMER ..................................................................................... 191
13.1 Outline of 16-Bit I/O Timer .............................................................................................................. 192
13.2 16-Bit I/O Timer Registers .............................................................................................................. 194
13.3 16-bit Free-run Timer ...................................................................................................................... 196
13.3.1 Data Register ............................................................................................................................. 197
13.3.2 Control Status Register ............................................................................................................. 198
13.3.3 16-bit Free-run Timer Operation ................................................................................................ 201
13.4 Output Compare ............................................................................................................................. 203
13.4.1 Output Compare Register .......................................................................................................... 204
13.4.2 Control Status Register of Output Compare .............................................................................. 205
13.4.3 16-bit Output Compare Operation ............................................................................................. 210
13.5 Input Capture .................................................................................................................................. 215
13.5.1 Input Capture Register Details .................................................................................................. 216
13.5.2 16-bit Input Capture Operation .................................................................................................. 221
CHAPTER 14 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) ................ 223
14.1 Outline of 16-Bit Reload Timer (with Event Count Function) .......................................................... 224
14.2 16-Bit Reload Timer (with Event Count Function) .......................................................................... 226
14.2.1 Timer Control Status Register (TMCSR) ................................................................................... 227
14.2.2 Register Layout of 16-bit Timer Register (TMR)/16-bit Reload Register (TMRLR) ................... 230
14.3 Internal Clock and External Clock Operations of 16-bit Reload Timer ........................................... 231
14.4 Underflow Operation of 16-bit Reload Timer .................................................................................. 233
14.5 Output Pin Functions of 16-bit Reload Timer .................................................................................. 234
14.6 Counter Operation State ................................................................................................................. 235

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CHAPTER 15 WATCH TIMER ........................................................................................ 237
15.1 Outline of Watch Timer ................................................................................................................... 238
15.2 Watch Timer Registers ................................................................................................................... 239
15.2.1 Timer Control Register .............................................................................................................. 240
15.2.2 Sub-second Registers ............................................................................................................... 244
15.2.3 Second/Minute/Hour Registers .................................................................................................. 245
CHAPTER 16 8/16-BIT PPG ........................................................................................... 247
16.1 Outline of 8/16-bit PPG ................................................................................................................... 248
16.2 Block Diagram of 8/16-bit PPG ....................................................................................................... 250
16.3 8/16-bit PPG Registers ................................................................................................................... 254
16.3.1 PPG0 Operation Mode Control Register (PPGC0) .................................................................... 255
16.3.2 PPG1 Operation Mode Control Register (PPGC1) .................................................................... 257
16.3.3 PPG0/1 Clock Select Register (PPG01) .................................................................................... 259
16.3.4 Reload Register (PRLL/PRLH) .................................................................................................. 261
16.4 Operations of 8/16-bit PPG ............................................................................................................. 262
16.5 Selecting a Count Clock for 8/16-bit PPG ....................................................................................... 264
16.6 Controlling Pin Output of 8/16-bit PPG Pulses ............................................................................... 265
16.7 8/16-bit PPG Interrupts ................................................................................................................... 266
16.8 Initial Values of 8/16-bit PPG Hardware ......................................................................................... 267
CHAPTER 17 DTP/EXTERNAL INTERRUPTS .............................................................. 269
17.1 Outline of DTP/External Interrupts .................................................................................................. 270
17.2 DTP/External Interrupt Registers .................................................................................................... 271
17.3 Operations of DTP/External Interrupts ............................................................................................ 273
17.4 Switching between External Interrupt and DTP Requests .............................................................. 275
17.5 Notes on Using DTP/External Interrupts ......................................................................................... 276
CHAPTER 18 8/10-BIT A/D CONVERTER ..................................................................... 279
18.1 Outline of the 8/10-Bit A/D Converter ............................................................................................. 280
18.2 Configuration of the 8/10-Bit A/D Converter ................................................................................... 282
18.3 8/10-Bit A/D Converter Pins ............................................................................................................ 284
18.4 8/10-Bit A/D Converter Registers ................................................................................................... 286
18.4.1 Analog Input Enable / A/D Converter Select Register ............................................................... 287
18.4.2 A/D Control Status Register 1 (ADCS1) .................................................................................... 288
18.4.3 A/D control status register 0 (ADCS0) ....................................................................................... 290
18.4.4 A/D Data Register (ADCR0, ADCR1) ........................................................................................ 292
18.5 8/10-Bit A/D Converter Interrupts ................................................................................................... 294
18.6 Operation of the 8/10-Bit A/D Converter ......................................................................................... 295
18.6.1 Conversion using EI2OS ............................................................................................................ 297
18.6.2 A/D conversion data protection function .................................................................................... 298
18.7 Notes on the 8/10-Bit A/D Converter .............................................................................................. 300
18.8 Sample Program 1 for the 8/10-Bit A/D Converter (Single Conversion Mode Using EI2OS) ......... 301
18.9 Sample Program 2 for the 8/10-Bit A/D Converter (Continuous Conversion Mode Using EI2OS)
.......................................................................................................................................................... 304
18.10 Sample Program 3 for the 8/10-Bit A/D Converter (Stop Conversion Mode Using EI2OS) ............ 307

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CHAPTER 19 UART0, UART1 ........................................................................................ 311
19.1 Features of UART0, UART1 ........................................................................................................... 312
19.2 UART0, UART1 Block Diagram ...................................................................................................... 313
19.3 UART0, UART1 Registers .............................................................................................................. 314
19.3.1 Serial Mode Control Register (UMC) ......................................................................................... 315
19.3.2 Status Register (USR) ............................................................................................................... 317
19.3.3 Input Data Register (UIDR) and Output Data Register (UODR) ................................................ 319
19.3.4 Rate and Data Register (URD) .................................................................................................. 320
19.4 UART0, UART1 Operation ............................................................................................................. 322
19.5 Baud Rate ....................................................................................................................................... 323
19.6 Internal and External Clock ............................................................................................................. 326
19.7 Transfer Data Format ..................................................................................................................... 327
19.8 Parity Bit ......................................................................................................................................... 328
19.9 Interrupt Generation and Flag Set Timings ..................................................................................... 329
19.9.1 Flag Set Timings for a Receive Operation (Mode0, Mode1, Mode3) ........................................ 330
19.9.2 Flag Set Timings for a Receive Operation (in Mode 2) ............................................................. 331
19.9.3 Flag Set Timings for a Transmit Operation ................................................................................ 332
19.9.4 Status Flag During Transmit and Receive Operation ................................................................ 333
19.10 UART0, UART1 Application Example ............................................................................................. 334
CHAPTER 20 UART2, UART3 ........................................................................................ 337
20.1 Overview of UART2, UART3 .......................................................................................................... 338
20.2 Configuration of UART2, UART3 .................................................................................................... 342
20.3 UART2, UART3 Pins ...................................................................................................................... 347
20.4 UART2, UART3 Registers .............................................................................................................. 349
20.4.1 Serial Control Register (SCR2/SCR3) ....................................................................................... 350
20.4.2 Serial Mode Register (SMR2/SMR3) ......................................................................................... 352
20.4.3 Serial Status Register (SSR2/SSR3) ......................................................................................... 354
20.4.4 Reception and Transmission Data Register (RDR2/RDR3 and TDR2/TDR3) .......................... 357
20.4.5 Extended Status/Control Register (ESCR2/ESCR3) ................................................................. 359
20.4.6 Extended Communication Control Register (ECCR2/ECCR3) .................................................. 362
20.4.7 Baud Rate Generator Register 0 and 1 (BGR02/03 and BGR12/13) ........................................ 364
20.5 UART2, UART3 Interrupts .............................................................................................................. 365
20.5.1 Reception Interrupt Generation and Flag Set Timing ................................................................ 369
20.5.2 Transmission Interrupt Generation and Flag Set Timing ........................................................... 371
20.6 UART2, UART3 Baud Rates .......................................................................................................... 373
20.6.1 Setting the Baud Rate ............................................................................................................... 375
20.6.2 Reload Counter ......................................................................................................................... 378
20.7 Operation of UART2, UART3 ......................................................................................................... 380
20.7.1 Operation in Asynchronous Mode (Op. Modes 0 and 1) ........................................................... 382
20.7.2 Operation in Synchronous Mode (Operation Mode 2) ............................................................... 385
20.7.3 Operation with LIN Function (Operation Mode 3) ...................................................................... 388
20.7.4 Direct Access to Serial Pins ...................................................................................................... 392
20.7.5 Bidirectional Communication Function (Normal Mode) ............................................................. 393
20.7.6 Master/Slave Communication Function (Multiprocessor Mode) ................................................ 395
20.7.7 LIN Communication Function .................................................................................................... 398
20.7.8 Sample Flowcharts for UART2, UART3 in LIN Communication (Operation Mode 3) ................ 399

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20.8 Notes on Using UART2, UART3 ..................................................................................................... 401
CHAPTER 21 400 kHz I2C INTERFACE ......................................................................... 405
21.1 I2C Interface Overview .................................................................................................................... 406
21.2 I2C Interface Registers ................................................................................................................... 408
21.2.1 Bus Status Register (IBSR) ....................................................................................................... 410
21.2.2 Bus Control Register (IBCR) ..................................................................................................... 413
21.2.3 Ten Bit Slave Address Register (ITBA) ..................................................................................... 422
21.2.4 Ten Bit Address Mask Register (ITMK) ..................................................................................... 423
21.2.5 I2C Seven Bit Slave Address Register (ISBA) ........................................................................... 425
21.2.6 I2C Data Register (IDAR) .......................................................................................................... 427
21.2.7 I2C Clock Control Register (ICCR) ............................................................................................ 428
21.2.8 Noise Filter Configuration Register (INFCR) ............................................................................. 431
21.3 I2C Interface Operation ................................................................................................................... 432
21.4 Programming Flow Charts .............................................................................................................. 435
CHAPTER 22 SERIAL I/O ............................................................................................... 437
22.1 Outline of Serial I/O ........................................................................................................................ 438
22.2 Serial I/O Registers ......................................................................................................................... 439
22.2.1 Serial Mode Control Status Register (SMCS) ........................................................................... 440
22.2.2 Serial Shift Data Register (SDR) ............................................................................................... 444
22.3 Serial I/O Prescaler (CDCR) ........................................................................................................... 445
22.4 Serial I/O Operation ........................................................................................................................ 446
22.4.1 Shift Clock ................................................................................................................................. 447
22.4.2 Serial I/O Operation ................................................................................................................... 448
22.4.3 Shift Operation Start/Stop Timing .............................................................................................. 450
22.4.4 Interrupt Function of the Extended Serial I/O Interface ............................................................. 453
CHAPTER 23 CAN CONTROLLER ................................................................................ 455
23.1 Features of CAN Controller ............................................................................................................ 456
23.2 Block Diagram of CAN Controller ................................................................................................... 457
23.3 List of Overall Control Registers ..................................................................................................... 458
23.4 List of Message Buffers (ID Registers) ........................................................................................... 460
23.5 List of Message Buffers (DLC Registers and Data Registers) ........................................................ 463
23.6 Classifying the CAN Controller Registers ....................................................................................... 466
23.6.1 Control Status Register (CSR) .................................................................................................. 467
23.6.2 Bus Operation Stop Bit (HALT = 1) ........................................................................................... 472
23.6.3 Last Event Indicator Register (LEIR) ......................................................................................... 474
23.6.4 Receive and Transmit Error Counters (RTEC) .......................................................................... 476
23.6.5 Bit Timing Register (BTR) .......................................................................................................... 477
23.6.6 Message Buffer Valid Register (BVALR) ................................................................................... 479
23.6.7 IDE register (IDER) .................................................................................................................... 480
23.6.8 Transmission Request Register (TREQR) ................................................................................ 481
23.6.9 Transmission RTR Register (TRTRR) ....................................................................................... 482
23.6.10 Remote Frame Receiving Wait Register (RFWTR) ................................................................... 483
23.6.11 Transmission Cancel Register (TCANR) ................................................................................... 484
23.6.12 Transmission Complete Register (TCR) .................................................................................... 485

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23.6.13 Transmission Interrupt Enable Register (TIER) ......................................................................... 486
23.6.14 Reception Complete Register (RCR) ........................................................................................ 487
23.6.15 Remote Request Receiving Register (RRTRR) ........................................................................ 488
23.6.16 Receive Overrun Register (ROVRR) ......................................................................................... 489
23.6.17 Reception Interrupt Enable Register (RIER) ............................................................................. 490
23.6.18 Acceptance Mask Select Register (AMSR) ............................................................................... 491
23.6.19 Acceptance Mask Registers 0 and 1 (AMR0 and AMR1) .......................................................... 493
23.6.20 Message Buffers ........................................................................................................................ 495
23.6.21 ID Register x (x = 0 to 15) (IDRx) .............................................................................................. 496
23.6.22 DLC Register x (x = 0 to 15) (DLCRx) ....................................................................................... 498
23.6.23 Data Register x (x = 0 to 15) (DTRx) ......................................................................................... 499
23.7 Transmission of CAN Controller ..................................................................................................... 501
23.8 Reception of CAN Controller .......................................................................................................... 504
23.9 Reception Flowchart of CAN Controller .......................................................................................... 507
23.10 How to Use the CAN Controller ...................................................................................................... 508
23.11 Procedure for Transmission by Message Buffer (x) ....................................................................... 510
23.12 Procedure for Reception by Message Buffer (x) ............................................................................. 512
23.13 Setting Configuration of Multi-level Message Buffer ....................................................................... 514
23.14 Setting the redirection of CAN1 and CAN3 RX/TX pin ................................................................... 516
23.15 Setting the CAN Direct Mode Register ........................................................................................... 518
23.16 Precautions when Using CAN Controller ........................................................................................ 519
CHAPTER 24 STEPPING MOTOR CONTROLLER ....................................................... 521
24.1 Outline of Stepping Motor Controller .............................................................................................. 522
24.2 Stepping Motor Controller Registers ............................................................................................... 523
24.2.1 PWM Control 0 register ............................................................................................................. 524
24.2.2 PWM1 and PWM2 Compare Registers ..................................................................................... 526
24.2.3 PWM1 and PWM2 Select Registers .......................................................................................... 527
24.3 Notes on Using the Stepping Motor Controller ............................................................................... 531
CHAPTER 25 SOUND GENERATOR ............................................................................. 533
25.1 Outline of Sound Generator ............................................................................................................ 534
25.2 Sound Generator Registers ............................................................................................................ 535
25.2.1 Sound Generator Control Register ............................................................................................ 536
25.2.2 Frequency Data register ............................................................................................................ 539
25.2.3 Amplitude Data Register ............................................................................................................ 540
25.2.4 Decrement Grade Register ........................................................................................................ 541
25.2.5 Tone Count Register ................................................................................................................. 542
CHAPTER 26 ADDRESS MATCH DETECTION FUNCTION ......................................... 543
26.1 Outline of the Address Match Detection Function .......................................................................... 544
26.2 Registers of the Address Match Detection Function ....................................................................... 545
26.3 Operation of the Address Match Detection Function ...................................................................... 547
26.4 Example of the Address Match Detection Function ........................................................................ 548
CHAPTER 27 ROM MIRRORING MODULE ................................................................... 551
27.1 Outline of ROM Mirroring Module ................................................................................................... 552

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27.2 ROM Mirroring Register (ROMM) ................................................................................................... 553
CHAPTER 28 3M-BIT FLASH MEMORY ........................................................................ 555
28.1 Overview of 3M-bit Flash Memory .................................................................................................. 556
28.2 Block Diagram of the Entire Flash Memory and Sector Configuration of the Flash Memory .......... 557
28.3 Write/Erase Modes ......................................................................................................................... 559
28.4 Flash Memory Control Status Register (FMCS) ............................................................................. 561
28.5 Starting the Flash Memory Automatic Algorithm ............................................................................ 563
28.6 Confirming the Automatic Algorithm Execution State ..................................................................... 565
28.6.1 Data Polling Flag (DQ7) ............................................................................................................ 567
28.6.2 Toggle Bit Flag (DQ6) ................................................................................................................ 569
28.6.3 Timing Limit Exceeded Flag (DQ5) ........................................................................................... 570
28.6.4 Sector Erase Timer Flag (DQ3) ................................................................................................. 571
28.6.5 Toggle Bit-2 Flag (DQ2) ............................................................................................................ 573
28.7 Detailed Explanation of Writing to and Erasing Flash Memory ....................................................... 575
28.7.1 Setting The Read/Reset State ................................................................................................... 576
28.7.2 Writing Data ............................................................................................................................... 577
28.7.3 Erasing All Data (Erasing Chips) ............................................................................................... 579
28.7.4 Erasing Optional Data (Erasing Sectors) ................................................................................... 580
28.7.5 Suspending Sector Erase .......................................................................................................... 582
28.7.6 Restarting Sector Erase ............................................................................................................ 583
28.8 Notes on using 3M-bit Flash Memory ............................................................................................. 584
28.9 Reset Vector Address in Flash Memory ......................................................................................... 586
28.10 Example of Programming 3M-bit Flash Memory ............................................................................ 587
CHAPTER 29 EXAMPLES OF SERIAL PROGRAMMING CONNECTION .................... 591
29.1 Basic Configuration of MB90F394H(A) Serial Programming Connection ....................................... 592
29.2 Example of Serial Programming Connection .................................................................................. 596
29.3 Example of Serial Programming Connection (Power Supplied From the Programmer) ................. 598
29.4 Example of Minimum Connection to the Flash Microcontroller Programmer
(User Power Supply Used) ............................................................................................................. 600
29.5 Example of Minimum Connection to the Flash Microcontroller Programmer
(Power Supplied From the Programmer) ........................................................................................ 602
APPENDIX ......................................................................................................................... 605
APPENDIX A I/O Maps .............................................................................................................................. 606
APPENDIX B Instructions ........................................................................................................................... 621
B.1 Instruction Types ............................................................................................................................ 622
B.2 Addressing ..................................................................................................................................... 623
B.3 Direct Addressing ........................................................................................................................... 625
B.4 Indirect Addressing ........................................................................................................................ 631
B.5 Execution Cycle Count ................................................................................................................... 639
B.6 Effective address field .................................................................................................................... 642
B.7 How to Read the Instruction List .................................................................................................... 643
B.8 F2MC-16LX Instruction List ............................................................................................................ 646
B.9 Instruction Map ............................................................................................................................... 660
APPENDIX C Timing Diagrams in Flash Memory Mode ............................................................................ 682

xiii
APPENDIX D List of Interrupt Vectors ........................................................................................................ 690
INDEX................................................................................................................................... 695

xiv

xv
Main changes in this edition
The vertical lines marked in the left side of the page show the changes.
Page Changes (For details, refer to main body.)
621 to 681 Changed the entire part of "APPENDIX B Instructions"
Reference: Main changes (Rev.2 →Rev.3)
Page Changes (For details, refer to main body.)
-
Added the following part number.
(MB90V390HA, MB90V390HB, MB90394HA, MB90F394HA)
Register name and pin name are changed.
(Program bank register (PCB) →Program counter bank register (PCB))
(Additional bank register (ADB) →Additional data bank register (ADB))
(ESCR3 →ESCR2/ESCR3)
(SIN3 →SIN2/SIN3)
(SOT3 →SOT2/SOT3)
(SMR3 →SMR2,SMR3)
(ECCR3 →ECCR2/ECCR3)
(BGR03/13 →BGR02/BGR03,BGR12/BGR13)
(SSR3 →SSR2/SSR3)
(RDR3 →RDR2/RDR3)
(SCR3 →SCR2/SCR3)
(TDR3 →TDR2/TDR3)
(SCK3 →SCK2/SCK3)
(UODR0, 1, 2 →UODR0, UODR1)
(UIDR0, 1, 2 →UIDR0, UIDR1)
Function name is changed.
(UART0, 1, 2 →UART0, UART1)
(UART3 →UART2, UART3)
(UART3 synchronous clock mode →UART2, UART3 synchronous clock mode)
(3M/4M-BIT FLASH MEMORY →3M-BIT FLASH MEMORY)
3Table 1.2-1 Features of the MB90390 Series (1/3) is changed.
(UART of MB90V390H : 3 channels →2 channels)
4Table 1.2-1 Features of the MB90390 Series (2/3) is changed.
(Clock Modulator is added.)
5Table 1.2-1 Features of the MB90390 Series (3/3) is changed. (15 years →20 years*)
(* is added.)
13 Table 1.8-1 Pin Description (1/6) Pin name of pin number 98 is changed.
(P00 to P05 →P05)
22
●Preventing latch-up is changed.
(Therefore, the maximum voltage ratings must not be exceeded. By the same token, make sure that the
analog supply voltage (AVCC and AVRH) should not exceed the digital supply voltage. is added.)
23 ●Power supply input pins (VCC/VSS) is changed.

xvi
24
●Crystal Oscillator Circuit is changed.
(Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device. is
added.)
●Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs is changed.
((turning on/off the analog and digital power supplies simultaneously is acceptable) is deleted.)
●Note on operation during PLL clock mode is changed.
55 Figure 3.1-2 Overview of Software Interrupts is changed.
(ILM : Interrupt level mask register →S :Stack flag)
59 Notes is changed. (•ICS1 and ICS0 are valid for write only. S1 and S0 are valid for read only. is added.)
(<Additional information> is added.)
63 Figure 3.4-2 Register Saving During Interrupt Processing is changed.
(DPB →DTB)
68 Figure 3.5-2 Registers Saved in Stack is changed.
(DPB →DTB)
70 Figure 3.6-1 Occurrence and Release of Software Interrupt is changed.
(ILM : Interrupt level mask register →S :Stack flag)
78
●When data transfer continues (when the stop condition is not satisfied) is changed.
((Table 3.8-1 "Execution time when the extended EI2OS continues" + Table 3.8-2 "Data transfer compensa-
tion values for extended EI2OS execution time") machine cycles →((Table 3.8-1 + Table 3.8-2) machine
cycles)
103 Summary of 5.7 Output of the main clock HCLK and HCLKX is changed.
105 CHAPTER 6 CLOCK MODULATOR
Notes is changed.
112 Table 6.3-1 Function of Each Bit of the Clock Modulator Control Register (3/3) Function of bit1 is changed.
(6 ms →6 µs)
113 Table 6.3-2 States of the Modulator is changed. (modulator power on, waiting modulator startup time (> 6 ms) →
modulator power on, waiting modulator startup time (> 6 µs))
114 Figure 6.3-3 Modulation Parameter Register is changed.
(CMPRL (upper) →CMPRH (upper))
(XX0000010 B→XX000010B)
141 Figure 8.2-1 Block Diagram of the Low-power Consumption Control Circuit is changed.
(Osc. stab. wait clear →Oscillation stabilization wait time clear)
158 8.7 Status of Pins in Standby Mode and during Reset is added.
175
■Analog Input Enable Registers
Note is changed.
(ANIN 0 to 7 →AN0 to AN7)
(ANIN 8 to 14 →AN8 to AN14)
184 Figure 12.1-1 Watchdog Timer Block Diagram is changed.
187 ■State Transition Diagram of the Watchdog Timer is added.
188
■Watchdog Counter is changed.
■Watchdog Stop is changed.
■Watchdog Deactivation is added.
■Watchdog Timer Behavior in Stop Mode, Time-base Timer Mode, and Sleep Mode is added.
189 ■Watchdog Timer Behavior at Reset is added.
Reference: Main changes (Rev.2 →Rev.3)
Page Changes (For details, refer to main body.)