GE CPCI3UX606 Quick user guide

Hardware Reference Manual
CPCI3UX606
First Edition
Publication No. CPCI3UX606-HRM/1
GE
Intelligent Platforms

Publication No. CPCI3UX606-HRM/1 2
Document History
Waste Electrical and Electronic Equipment (WEEE) Returns
GEIntelligentPlatformsLimitedisregisteredwithanapprovedProducerComplianceScheme
(PCS)and,subjecttosuitablecontractualarrangementsbeinginplace,willensureWEEEis
processedinaccordancewiththerequirementsoftheWEEEDirective.
GEIntelligentPlatformsLimited.willevaluaterequeststotakebackproductspurchasedbyour
customersbeforeAugust13,2005onacasebycasebasis.AWEEEmanagementfeemayapply.
Edition Date Board Artwork Revision
First May 2010 Rev 1

Publication No. CPCI3UX606-HRM/1 Table of Contents 3
Table of Contents
1 • CPCI3UX606 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.1 Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2 Connector and Header Designations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3 Breakout Panel Connectivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.4 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.4.1 P1 (Ethernet Gigabit Signals) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.4.2 P2 (COM1/COM2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.4.3 P3 (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.4.4 P4 (PMC 1 to 32 I/O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.4.5 P5 (PMC 33 to 64 I/O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
1.4.6 P6 (SATA0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
1.4.7 P7 (SATA1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
1.4.8 P8 (COM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
1.4.9 P9 and P10 (ETH1/GPIO/COM1 Options) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
1.4.10 J3 (10/100/1000BaseT Ethernet Channel 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
1.4.11 J4 (10/100/1000BaseT Ethernet Channel 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
1.4.12 J5 (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

4CPCI3UX606 Publication No. CPCI3UX606-HRM/1
1 • CPCI3UX606
Theinformationcontainedinthismanualmustbeusedinconjunctionwiththe
I/OModulesManual.
LINK
I/O Modules Manual, publication number RT5154.
1.1 Description
TheCPCI3UX606moduleisacustomizedinterfaceadapter,compatiblewith3U
CompactPCIbackplanes.ItfitsdirectlyontotherearP2positionofthebackplane
andisonlysuitableforinterconnectionwiththeIMP3Ahostcard.Seethe
I/OModulesManual‐CompatibilityTablesformoreinformation.
TheCPCI3UX606issuitableforfittinginrearguide‐rails,accordingto
IEEE1101.11.
Figure 1-1 CPCI3UX606

Publication No. CPCI3UX606-HRM/1 CPCI3UX606 5
1.2 Connector and Header Designations
CAUTION
Do not fit a jumper across the E1 pins. If a build option that provides USB has been selected, linking
these pins will short USB_PWR to ground, which may cause damage to the IMP3A.
Figure 1-2 RS422/485 Signal Definition
Table 1-1 Headers
PCB Male Header ID Function Pin Signal
E1 BIT_FAIL open-drain output/
USB powera
a. Function depends on the build option selected.
1USB_PWR
2GND
E2 RTC_STDBY input 1RTC_STDBY
2GND
E3 Push-button resetb
b.A push-button reset switch can be connected across these pins.
1PRST#
2GND
E4 Flash protection unlock linkc
c. Not available on Rev 1 boards.
1FLASH_WE#
2GND
E5 COM1 RS422 input terminationd
d.120 Ω termination selected when pins linked.
1COM1_RXD_A
2COM1_RXD_B
E6 COM2 RS422 input terminationb1COM2_RXD_A
2COM2_TERM

6CPCI3UX606 Publication No. CPCI3UX606-HRM/1
ChassisGNDisconnectedviathefrontpanel.
NOTE
Availability of signals at the various connectors depends on the I/O option selected on the IMP3A.
See the hardware reference manual for more details.
LINK
IMP3A Hardware Reference Manual, publication number IMP3A-HRM.
1.3 Breakout Panel Connectivity
Table 1-2 Connectors
Connector Function Type
P1 Ethernet Gigabit Signals Male header
P2 COM1/COM2 Male header
P3 GPIO Male header
P4 PMC 1 to 32 I/O Male header
P5 PMC 33 to 64 I/O Male header
P6 SATA0 Molex header
P7 SATA1 Molex header
P8 COM1 9-way D-type
P9 ETH1/GPIO/COM1 options Male header
P10 ETH1/GPIO/COM1 options Male header
J3 10/100/1000BaseT Ethernet Channel 0 RJ-45
J4 10/100/1000BaseT Ethernet Channel 1 RJ-45
J5 USB female type A USB
Table 1-3 Breakout Panel Connectivity
Breakout Panels
RS232 (2 x 9-way D-type) RS232 (2 x 25-way D-Type)
SIOX600 SIO2X601
CPCI3UX606 header P2 P2

Publication No. CPCI3UX606-HRM/1 CPCI3UX606 7
1.4 Pin Assignments
1.4.1 P1 (Ethernet Gigabit Signals)
CAUTION
If a build option that does not provide Gigabit Ethernet on either channel 0 or 1 is selected, then
these pins carry the GPIO signals shown. In this case, no links should be fitted across P1 to prevent
damage to or unexpected operation on any Gigabit Ethernet interface connected to J3 or J4.
AssumingthebuildoptionprovidesGigabitEthernet,forGigabitEthernet
operationonchannel0(atJ3),fitlinksacrossthepinsshownbelow:
ForGigabitEthernetoperationonchannel1(atJ4),fitlinksacrossthepinsshown
below:
ETH1_3‐andETH1_3+areselectedusingP9andP10.
1.4.2 P2 (COM1/COM2)
COM1is2‐wireRS232DTEasaminimum(noRTS/CTS);4‐wireoperation
dependsonavailabilityoftherequiredsignals,whichisanIMP3Abuildoption
(alsoseeP9andP10).RS232/RS422configurationofCOM1issoftwarecontrolled;
RS422optionsignalsaregiveninparentheses.
COM2is4‐wirepermanently.RS232/RS422configurationofCOM2issoftware
controlled;RS422optionsignalsaregiveninparentheses.
Table 1-4 P1 Pin Assignments for Gigabit Ethernet on Channel 0
Pins Linked Signal GPIO Signal
12 and 11 ETH0_2+ GPIO4
10 and 9 ETH0_2- GPIO5
8 and 7 ETH0_3+ GPIO7
6 and 5 ETH0_3- GPIO8
Table 1-5 P1 Pin Assignments for Gigabit Ethernet on Channel 1
Pins Linked Signal GPIO Signal
4 and 3 ETH1_2+ GPIO6
2 and 1 ETH1_2- GPIO9
Table 1-6 P2 Pin Assignments
Pin Signal Pin Signal
1COM1_LBa
a.Connected between pins 1, 2 and 3.
2COM1_LBa
3COM1_LBa4 No connection
5 COM1_TXD (TXD_A) 6 COM1_RXD (RXD_A)
7 COM1_CTS (RXD_B) 8 COM1_RTS (TXD_B)
9 No connection 10 No connection
11 No connection 12 COM2_LBb
13 COM2_TXD (TXD_A) 14 COM2_LBb
15 COM2_LBb
b.Connected between pins 12, 14 and 15.
16 COM2_RXD (RXD_A)
17 COM2_RTS (TXD_B) 18 COM2_CTS (RXD_B)
19 GND 20 GND

8CPCI3UX606 Publication No. CPCI3UX606-HRM/1
1.4.3 P3 (GPIO)
NOTE
Availability of signals at this connector depends on the build option selected on the IMP3A.
Table 1-7 P3 Pin Assignments
Pin Signal Pin Signal
1GPIO0 2GND
3GPIO1 4GND
5GPIO2 6GND
7GPIO3 8GND
9GPIO4 10GND
11 GPIO5 12 GND
13 GPIO6 14 GND
15 GPIO7 16 GND
17 GPIO8 18 GND
19 GPIO9 20 GND
21 GPIO10 22 GND
23 GPIO11 24 GND
25 GPIO12 26 GND
27 GPIO13 28 GND
29 GPIO14 30 GND
31 GPIO15 32 GND

Publication No. CPCI3UX606-HRM/1 CPCI3UX606 9
1.4.4 P4 (PMC 1 to 32 I/O)
Table 1-8 P4 Pin Assignments
Pin Signal Pin Signal
1 J14-1 2 J14-2
3 J14-3 4 J14-4
5 J14-5 6 J14-6
7 J14-7 8 J14-8
9 J14-9 10 J14-10
11 J14-11 12 J14-12
13 J14-13 14 J14-14
15 J14-15 16 J14-16
17 J14-17 18 J14-18
19 J14-19 20 J14-20
21 J14-21 22 J14-22
23 J14-23 24 J14-24
25 J14-25 26 J14-26
27 J14-27 28 J14-28
29 J14-29 30 J14-30
31 J14-31 32 J14-32
33 GND 34 GND
35 GND 36 GND

10 CPCI3UX606 Publication No. CPCI3UX606-HRM/1
1.4.5 P5 (PMC 33 to 64 I/O)
NOTE
Availability of signals at this connector depends on the build option selected on the IMP3A.
PMC I/Os 47 to 64 are also not available if the IMP3A is System Controller.
1.4.6 P6 (SATA0)
NOTE
Availability of signals at this connector depends on the build option selected on the IMP3A.
Usearight‐angledSATAcabletoremainwithintheallowableheightlimit.
Table 1-9 P5 Pin Assignments
Pin Signal Pin Signal
1 J14-33 2 J14-34
3 J14-35 4 J14-36
5 J14-37 6 J14-38
7 J14-39 8 J14-40
9 J14-41 10 J14-42
11 J14-43 12 J14-44
13 J14-45 14 J14-46
15 J14-47 16 J14-48
17 J14-49 18 J14-50
19 J14-51 20 J14-52
21 J14-53 22 J14-54
23 J14-55 24 J14-56
25 J14-57 26 J14-58
27 J14-59 28 J14-60
29 J14-61 30 J14-62
31 J14-63 32 J14-64
33 GND 34 GND
35 GND 36 GND
Table 1-10 P6 Pin Assignments
Pin Signal
1GND
2SATA0_TX+
3SATA0_TX-
4GND
5SATA0_RX-
6SATA0_RX+
7GND

Publication No. CPCI3UX606-HRM/1 CPCI3UX606 11
1.4.7 P7 (SATA1)
NOTE
Availability of signals at this connector depends on the build option selected on the IMP3A.
Usearight‐angledSATAcabletoremainwithintheallowableheightlimit.
1.4.8 P8 (COM1)
SeetheP2descriptionformoredetailsonCOM1.
Table 1-11 P6 Pin Assignments
Pin Signal
1GND
2SATA1_TX+
3SATA1_TX-
4GND
5SATA1_RX-
6SATA1_RX+
7GND
Table 1-12 P8 Pin Assignments
Pin Signal Pin Signal
1 No connection 6 No connection
2 COM1_RXD (RXD_A) 7 COM1_CTS (RXD_B)
3 COM1_TXD (TXD_A) 8 COM1_RTS (TXD_B)
4 No connection 9 No connection
5GND

12 CPCI3UX606 Publication No. CPCI3UX606-HRM/1
1.4.9 P9 and P10 (ETH1/GPIO/COM1 Options)
P9andP10mustbothbelinkedasappropriatefortheIMP3Abuildoption,as
showninFigure1‐3.
Figure 1-3 Connection Options
1.4.10 J3 (10/100/1000BaseT Ethernet Channel 0)
Gigabitoperationdependsonavailabilityoftherequiredsignals,whichisan
IMP3Abuildoption(seealsoP1).10/100signalsaregiveninparentheses.
Table 1-13 P9 Pin Assignments
Pin Signal Pin Signal
1ETH1_3+
3 ETH1_3+_GPIO10_COM1_CTS 4 COM1_CTS
5GPIO10
Table 1-14 P10 Pin Assignments
Pin Signal Pin Signal
2ETH1_3-
3 COM1_RTS 4 ETH1_3-_GPIO11_COM1_RTS
6GPIO11
Table 1-15 J3 Pin Assignments
Pin Signal
1ETH0_0+(TX+)
2ETH0_0-(TX-)
3ETH0_1+(RX+)
4ETH0_2+
5ETH0_2-
6ETH0_1-(RX-)
7ETH0_3+
8ETH0_3-

Publication No. CPCI3UX606-HRM/1 CPCI3UX606 13
1.4.11 J4 (10/100/1000BaseT Ethernet Channel 1)
Gigabitoperationdependsonavailabilityoftherequiredsignals,whichisan
IMP3Abuildoption(seealsoP1,P9andP10).10/100signalsaregivenin
parentheses.
1.4.12 J5 (USB)
NOTE
Availability of signals at this connector depends on the build option selected on the IMP3A.
TheIMP3AprovidesUSB_PWRwhenaUSBbuildoptionisselected.
Table 1-16 J4 Pin Assignments
Pin Signal
1ETH1_0+(TX+)
2ETH1_0-(TX-)
3ETH1_1+(RX+)
4ETH1_2+
5ETH1_2-
6ETH1_1-(RX-)
7ETH1_3+
8ETH1_3-
Table 1-17 J5 Pin Assignments
Pin Signal
1USB_PWR
2USB_D-
3USB_D+
4GND

14 CPCI3UX606 Publication No. CPCI3UX606-HRM/1
Figure 1-4 CPCI3UX606 with Front Panel
Figure 1-5 CPCI3UX606 in Rear Guide Rails (per IEEE1101.11)

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Publication No. CPCI3UX606-HRM/1