GE IMP2B Quick user guide

GE
Intelligent Platforms
Hardware Reference Manual
IMP2B 3U cPCI Single Board Computer
Edition 5
Publication No. IMP2B-0HH/5

2IMP2B 3U cPCI Single Board Computer Publication No. IMP2B-0HH/5
Document History
Edition Date Board Artwork Revision
1 September 2007 Rev 1
2 June 2008 Rev 2
3 July 2009 Rev 4
4 August 2010 Rev 4
4 + Errata April 2011 Rev 4
5 October 2011 Rev 4
Waste Electrical and Electronic Equipment (WEEE) Returns
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subject to suitable contractual arrangements being in place, will ensure WEEE is processed in
accordance with the requirements of the WEEE Directive.
GE Intelligent Platforms Limited will evaluate requests to take back products purchased by our
customers before August 13, 2005 on a case by case basis. A WEEE management fee may apply.

Publication No. IMP2B-0HH/5 Preface 3
Preface
This manual contains hardware information for the IMP2B boards with PCB artwork
revisions 4 and onwards. The information contained in this manual must be used in
conjunction with the PowerPact3 Family Product Manual.
LINK
PowerPact3 Family Product Manual, publication number PP3-0HH.

4IMP2B 3U cPCI Single Board Computer Publication No. IMP2B-0HH/5
Contents
1 • Overview........................................................................................................................................................8
1.1 Features .....................................................................................................................................................................................................8
2 • Configuration ........................................................................................................................................... 10
2.1 Link Functions.......................................................................................................................................................................................10
2.2 Suggested Link Settings ..................................................................................................................................................................11
2.3 Factory Test Link (P1).........................................................................................................................................................................11
2.4 Flash Boot Image Select Links (P2 1-2 and 3-4)................................................................................................................... 11
2.5 Backplane Flash Programming Link (P2 5-6)......................................................................................................................... 12
2.6 Flash Protection Password Unlock Link (P3 1-2)..................................................................................................................12
2.7 Boot Flash Write Enable Link (P3 3-4) and User Flash Write Enable Link (P3 5-6) ............................................... 13
2.8 JTAG Scanbridge Enable Link (P4 1-2) ......................................................................................................................................13
2.9 Backplane JTAG Buffer Enable Link (P4 3-4)..........................................................................................................................14
2.10 Backplane JTAG Auto-Write Enable Link (P4 5-6).............................................................................................................14
2.11 Force 33 MHz Operation Link (P5 1-2)....................................................................................................................................14
2.12 NVRAM/Serial EEPROM Write Enable Link (P5 3-4)...........................................................................................................15
2.13 Spare Link (P5 5-6) ...........................................................................................................................................................................15
2.14 Special Linking Requirements....................................................................................................................................................15
3 • Functional Description......................................................................................................................... 16
3.1 PowerPC Processor............................................................................................................................................................................16
3.2 Host Bridge ............................................................................................................................................................................................17
3.3 RAM............................................................................................................................................................................................................18
3.4 Non-Volatile RAM (NVRAM).............................................................................................................................................................18
3.5 Flash Memory .......................................................................................................................................................................................19
3.5.1 Boot Flash...........................................................................................................................................................................................................19
3.5.2 User Flash...........................................................................................................................................................................................................20
3.5.3 Flash Sector Protection................................................................................................................................................................................20
3.6 Memory Map set up by VxWorks (as seen by CPU) ............................................................................................................ 21
3.7 PMC Site...................................................................................................................................................................................................21
3.7.1 PMC Rear I/O Tracking..................................................................................................................................................................................22
3.7.2 ‘Peripheral Only’ Mode..................................................................................................................................................................................22
3.7.3 ‘Limited Host, Full PMC User I/O’ Mode.................................................................................................................................................22
3.7.4 ‘Alternative PMC I/O’ Mode.........................................................................................................................................................................23
3.8 Serial Ports .............................................................................................................................................................................................24
3.9 Ethernet...................................................................................................................................................................................................25
3.10 USB 2.0 ..................................................................................................................................................................................................25
3.11 Timers ....................................................................................................................................................................................................25
3.12 Watchdog Timer...............................................................................................................................................................................25
3.13 DMA Engines.......................................................................................................................................................................................26
3.14 I2C Interface ........................................................................................................................................................................................26
3.14.1 Serial EEPROM................................................................................................................................................................................................26
3.14.2 Real-Time Clock ............................................................................................................................................................................................26
3.14.3 Elapsed Time Indicator..............................................................................................................................................................................27
3.14.4 Temperature Sensing.................................................................................................................................................................................27
(continued overleaf)

Publication No. IMP2B-0HH/5 Contents 5
3 • Functional Description (continued)
3.15 EPLD........................................................................................................................................................................................................28
3.15.1 Internal EPLD Registers .............................................................................................................................................................................28
3.15.2 Board ID Register 1 – Offset 0x00000000 ........................................................................................................................................29
3.15.3 Board ID Register 2 – Offset 0x00000002 ........................................................................................................................................29
3.15.4 Device/Bus Information Register 1 – Offset 0x00000004.........................................................................................................29
3.15.5 Device/Bus Information Register 2 – Offset 0x00000006.........................................................................................................30
3.15.6 Configuration Register 1 – Offset 0x00000008..............................................................................................................................30
3.15.7 Configuration Register 2 – Offset 0x0000000A..............................................................................................................................31
3.15.8 Control Register 1 – Offset 0x0000000C...........................................................................................................................................31
3.15.9 Control Register 2 – Offset 0x0000000E ...........................................................................................................................................32
3.15.10 Test Registers..............................................................................................................................................................................................32
3.15.11 Scratchpad Registers ..............................................................................................................................................................................32
3.15.12 EPLD Interrupt Register – Offset 0x00000020 .............................................................................................................................33
3.15.13 Software Reset Register – Offset 0x00000040............................................................................................................................33
3.15.14 Semaphore Register – Offset 0x00000060 ...................................................................................................................................34
3.16 General Purpose I/O Controller .................................................................................................................................................34
3.16.1 GPIO Direction Control Register – Offset 0x00000400 ...............................................................................................................35
3.16.2 GPIO Data Register – Offset 0x00000402.........................................................................................................................................35
3.16.3 GPIO Polarity Control Register – Offset 0x00000404 ..................................................................................................................35
3.16.4 GPIO Interrupt Mode Register – Offset 0x00000406 ...................................................................................................................35
3.16.5 GPIO Interrupt Active Register – Offset 0x00000408 ..................................................................................................................36
3.16.6 GPIO Interrupt Enable Register – Offset 0x0000040A ................................................................................................................36
3.16.7 GPIO Masked Interrupt Status Register – Offset 0x0000040C................................................................................................36
3.17 CompactPCI Arbiter ........................................................................................................................................................................36
3.18 Resets ....................................................................................................................................................................................................37
3.19 Interrupts..............................................................................................................................................................................................38
3.20 JTAG........................................................................................................................................................................................................39
3.21 LEDs ........................................................................................................................................................................................................40
3.22 Front Panel ..........................................................................................................................................................................................41
4 • Connectors................................................................................................................................................ 42
4.1 J2 Connector Pinout..........................................................................................................................................................................43
4.1.1 System Controller Card (IMP2B-xxxxA).................................................................................................................................................43
4.1.2 Peripheral Only Card (IMP2B-xxxxB) ......................................................................................................................................................44
4.1.3 Limited Host, Full PMC User I/O Card (IMP2B-xxxxD) .....................................................................................................................45
4.1.4 System Controller Card – Alternative PMC I/O (IMP2B-xxxxE)....................................................................................................46
4.1.5 J2 Connector Signal Descriptions...........................................................................................................................................................47
4.1.6 PMC Rear I/O Tracking..................................................................................................................................................................................47
4.2 JTAG Test Header (P38)....................................................................................................................................................................47
A • Specifications........................................................................................................................................... 48
A.1 Technical Specification....................................................................................................................................................................48
A.2 Electrical Specification.....................................................................................................................................................................49
A.3 Weight......................................................................................................................................................................................................50
A.4 Reliability (MTBF)..................................................................................................................................................................................50
A.5 Product Codes......................................................................................................................................................................................51
A.6 Software Support................................................................................................................................................................................51
A.7 Development Tools............................................................................................................................................................................52
A.8 I/O Modules ...........................................................................................................................................................................................52
Index .................................................................................................................................................................... 53

6IMP2B 3U cPCI Single Board Computer Publication No. IMP2B-0HH/5
List of Tables
Table 2-1 Link Functions...............................................................................................................................................................................10
Table 2-2 Suggested Link Settings ..........................................................................................................................................................11
Table 2-3 Links P2 1-2 and 3-4..................................................................................................................................................................11
Table 2-4 Link P2 5-6......................................................................................................................................................................................12
Table 2-5 Link P3 1-2......................................................................................................................................................................................12
Table 2-6 Links P3 3-4 and 5-6..................................................................................................................................................................13
Table 2-7 Link P4 1-2......................................................................................................................................................................................13
Table 2-8 Link P4 3-4......................................................................................................................................................................................14
Table 2-9 Link P4 5-6......................................................................................................................................................................................14
Table 2-10 Link P5 1-2...................................................................................................................................................................................14
Table 2-11 Link P5 3-4...................................................................................................................................................................................15
Table 3-1 SDRAM Options............................................................................................................................................................................18
Table 3-2 Flash Options ................................................................................................................................................................................19
Table 3-3 Boot Image Selection................................................................................................................................................................19
Table 3-4 VxWorks Card-level Memory Map......................................................................................................................................21
Table 3-5 PMC Site IDSEL Connections..................................................................................................................................................21
Table 3-6 Alternative PMC I/O Mode Signals ......................................................................................................................................23
Table 3-7 Signal Sets Per Port in Available Modes...........................................................................................................................24
Table 3-8 I2C Device Addresses.................................................................................................................................................................26
Table 3-9 EPLD Registers..............................................................................................................................................................................28
Table 3-10 Board ID Register 1..................................................................................................................................................................29
Table 3-11 Board ID Register 2..................................................................................................................................................................29
Table 3-12 Device/Bus Information Register 1..................................................................................................................................29
Table 3-13 Device/Bus Information Register 2..................................................................................................................................30
Table 3-14 Configuration Register 1.......................................................................................................................................................30
Table 3-15 Configuration Register 2.......................................................................................................................................................31
Table 3-16 Control Register 1 .................................................................................................................................................................... 31
Table 3-17 Control Register 2 ....................................................................................................................................................................32
Table 3-18 Test Registers.............................................................................................................................................................................32
Table 3-19 Scratchpad Registers.............................................................................................................................................................32
Table 3-20 EPLD Interrupt Register .........................................................................................................................................................33
Table 3-21 Software Reset Register........................................................................................................................................................33
Table 3-22 Semaphore Register ...............................................................................................................................................................34
Table 3-23 GPIO Line to Register Bit Mapping ................................................................................................................................... 35
Table 3-24 Reset Causes..............................................................................................................................................................................37
Table 3-25 Interrupt Mapping....................................................................................................................................................................38
Table 3-26 Interrupt Combination ...........................................................................................................................................................38
Table 3-27 JTAG Chains................................................................................................................................................................................39
Table 3-28 LEDs ................................................................................................................................................................................................40
Table 3-29 BIT Status LEDs..........................................................................................................................................................................41
Table 4-1 Connector Functionality ..........................................................................................................................................................42

Publication No. IMP2B-0HH/5 List of Tables 7
Table 4-2 J2 Pinout (System Controller) ................................................................................................................................................43
Table 4-3 J2 Pinout (Peripheral Only)......................................................................................................................................................44
Table 4-4 J2 Pinout (Limited Host, Full PMC User I/O) ....................................................................................................................45
Table 4-5 J2 Pinout (System Controller- Alternative PMC I/O)....................................................................................................46
Table 4-6 J2 Signal Descriptions ..............................................................................................................................................................47
Table A-1 Technical Specification ............................................................................................................................................................48
Table A-2 Voltage Supply Requirements ..............................................................................................................................................49
Table A-3 Power Dissipation.......................................................................................................................................................................49
Table A-4 Reliability (MTBF)..........................................................................................................................................................................50
Table A-5 Product Codes..............................................................................................................................................................................51
List of Figures
Figure 1-1 View of IMP2B ................................................................................................................................................................................9
Figure 2-1 Link Positions (Top) ...................................................................................................................................................................10
Figure 3-1 Block Diagram ............................................................................................................................................................................16
Figure 3-2 RS422/485 Signal Definition ................................................................................................................................................24
Figure 3-3 LED Positions...............................................................................................................................................................................40
Figure 3-4 Front Panel...................................................................................................................................................................................41
Figure 4-1 Connector Positions.................................................................................................................................................................42

8IMP2B 3U cPCI Single Board Computer Publication No. IMP2B-0HH/5
1 • Overview
Available with the PowerPC MC7448 RISC CPU with integrated L2 cache, running at
up to 1.4 GHz, the IMP2B is based around a Marvell Discovery V (MV64560)
Integrated System Controller, which combines high performance system control
with multiple communication peripherals including high speed serial and dual
Ethernet ports, all on a single chip.
1.1 Features
•Freescale MPC7448 processor clocked at up to 1.4 GHz
•Marvell MV64560 bridge (‘Discovery V’)
•Up to 1 GByte of DDR2-400 SDRAM with ECC (512 MBytes as standard)
•Up to 256 MBytes of Spansion Flash memory (128 MBytes as standard)
•128 KByte AutoStore NVRAM
•32-bit/66 MHz CompactPCI interface (3.3 V signaling only)
•64-bit/133 MHz PCI-X to PMC site (3.3 V signaling only)
•1 to 49 PMC user rear I/O (1 to 64 if built in ‘Peripheral Only’ or ‘Limited Host,
Full PMC User I/O’ modes)
•Two serial ports, software-configurable for RS232/RS422, asynchronous only
•One 10/100/1000BaseT or two 10/100BaseT Ethernet channels, software selectable
•Two USB 2.0 Host Ports (OHCI/EHCI compliant) with power controllers
•4 bits of discrete digital I/O, each bit able to generate an interrupt
•Four 32-bit timers
•Six DMA channels including two XOR DMA engines for CRC32 calculation,
memory initialization and ECC error correction
•Watchdog timer
•Real-time clock
•Elapsed time indicator

Publication No. IMP2B-0HH/5 Overview 9
Figure 1-1 View of IMP2B

10 IMP2B 3U cPCI Single Board Computer Publication No. IMP2B-0HH/5
2 • Configuration
The IMP2B is delivered with push-on jumpers, but for rugged or military
applications, use optional zero Ohm resistors.
This manual refers to link settings as “In” or “Out”. Meanings are as follows:
In = jumper fitted -
Out = jumper not fitted -
TIP
Before changing any of the link options, refer to the appropriate section(s) in the following pages.
Figure 2-1 Link Positions (Top)
2.1 Link Functions
Table 2-1 Link Functions
Link Pins Function Link Pins Function
P5
5-6 Spare
P3
5-6 User Flash write enable
3-4 NVRAM write enable 3-4 Boot Flash write enable
1-2 Force CPCI 33 MHz operation 1-2 Flash protection password unlock
P4
5-6 Backplane JTAG AutoWrite enable
P2
5-6 Backplane Flash programming
3-4 Backplane JTAG buffer enable 3-4 Use Recovery Flash boot image
1-2 JTAG Scanbridge enable 1-2 Use Alternate Flash boot image
P1 All Factory test only
The IMP2B is shipped with no jumpers fitted.