GE IMP2B Quick user guide

GE
Intelligent Platforms
Hardware Reference Manual
IMP2B 3U cPCI Single Board Computer
Edition 5
Publication No. IMP2B-0HH/5

2IMP2B 3U cPCI Single Board Computer Publication No. IMP2B-0HH/5
Document History
Edition Date Board Artwork Revision
1 September 2007 Rev 1
2 June 2008 Rev 2
3 July 2009 Rev 4
4 August 2010 Rev 4
4 + Errata April 2011 Rev 4
5 October 2011 Rev 4
Waste Electrical and Electronic Equipment (WEEE) Returns
GE Intelligent Platforms Limited is registered with an approved Producer Compliance Scheme (PCS) and,
subject to suitable contractual arrangements being in place, will ensure WEEE is processed in
accordance with the requirements of the WEEE Directive.
GE Intelligent Platforms Limited will evaluate requests to take back products purchased by our
customers before August 13, 2005 on a case by case basis. A WEEE management fee may apply.

Publication No. IMP2B-0HH/5 Preface 3
Preface
This manual contains hardware information for the IMP2B boards with PCB artwork
revisions 4 and onwards. The information contained in this manual must be used in
conjunction with the PowerPact3 Family Product Manual.
LINK
PowerPact3 Family Product Manual, publication number PP3-0HH.

4IMP2B 3U cPCI Single Board Computer Publication No. IMP2B-0HH/5
Contents
1 • Overview........................................................................................................................................................8
1.1 Features .....................................................................................................................................................................................................8
2 • Configuration ........................................................................................................................................... 10
2.1 Link Functions.......................................................................................................................................................................................10
2.2 Suggested Link Settings ..................................................................................................................................................................11
2.3 Factory Test Link (P1).........................................................................................................................................................................11
2.4 Flash Boot Image Select Links (P2 1-2 and 3-4)................................................................................................................... 11
2.5 Backplane Flash Programming Link (P2 5-6)......................................................................................................................... 12
2.6 Flash Protection Password Unlock Link (P3 1-2)..................................................................................................................12
2.7 Boot Flash Write Enable Link (P3 3-4) and User Flash Write Enable Link (P3 5-6) ............................................... 13
2.8 JTAG Scanbridge Enable Link (P4 1-2) ......................................................................................................................................13
2.9 Backplane JTAG Buffer Enable Link (P4 3-4)..........................................................................................................................14
2.10 Backplane JTAG Auto-Write Enable Link (P4 5-6).............................................................................................................14
2.11 Force 33 MHz Operation Link (P5 1-2)....................................................................................................................................14
2.12 NVRAM/Serial EEPROM Write Enable Link (P5 3-4)...........................................................................................................15
2.13 Spare Link (P5 5-6) ...........................................................................................................................................................................15
2.14 Special Linking Requirements....................................................................................................................................................15
3 • Functional Description......................................................................................................................... 16
3.1 PowerPC Processor............................................................................................................................................................................16
3.2 Host Bridge ............................................................................................................................................................................................17
3.3 RAM............................................................................................................................................................................................................18
3.4 Non-Volatile RAM (NVRAM).............................................................................................................................................................18
3.5 Flash Memory .......................................................................................................................................................................................19
3.5.1 Boot Flash...........................................................................................................................................................................................................19
3.5.2 User Flash...........................................................................................................................................................................................................20
3.5.3 Flash Sector Protection................................................................................................................................................................................20
3.6 Memory Map set up by VxWorks (as seen by CPU) ............................................................................................................ 21
3.7 PMC Site...................................................................................................................................................................................................21
3.7.1 PMC Rear I/O Tracking..................................................................................................................................................................................22
3.7.2 ‘Peripheral Only’ Mode..................................................................................................................................................................................22
3.7.3 ‘Limited Host, Full PMC User I/O’ Mode.................................................................................................................................................22
3.7.4 ‘Alternative PMC I/O’ Mode.........................................................................................................................................................................23
3.8 Serial Ports .............................................................................................................................................................................................24
3.9 Ethernet...................................................................................................................................................................................................25
3.10 USB 2.0 ..................................................................................................................................................................................................25
3.11 Timers ....................................................................................................................................................................................................25
3.12 Watchdog Timer...............................................................................................................................................................................25
3.13 DMA Engines.......................................................................................................................................................................................26
3.14 I2C Interface ........................................................................................................................................................................................26
3.14.1 Serial EEPROM................................................................................................................................................................................................26
3.14.2 Real-Time Clock ............................................................................................................................................................................................26
3.14.3 Elapsed Time Indicator..............................................................................................................................................................................27
3.14.4 Temperature Sensing.................................................................................................................................................................................27
(continued overleaf)

Publication No. IMP2B-0HH/5 Contents 5
3 • Functional Description (continued)
3.15 EPLD........................................................................................................................................................................................................28
3.15.1 Internal EPLD Registers .............................................................................................................................................................................28
3.15.2 Board ID Register 1 – Offset 0x00000000 ........................................................................................................................................29
3.15.3 Board ID Register 2 – Offset 0x00000002 ........................................................................................................................................29
3.15.4 Device/Bus Information Register 1 – Offset 0x00000004.........................................................................................................29
3.15.5 Device/Bus Information Register 2 – Offset 0x00000006.........................................................................................................30
3.15.6 Configuration Register 1 – Offset 0x00000008..............................................................................................................................30
3.15.7 Configuration Register 2 – Offset 0x0000000A..............................................................................................................................31
3.15.8 Control Register 1 – Offset 0x0000000C...........................................................................................................................................31
3.15.9 Control Register 2 – Offset 0x0000000E ...........................................................................................................................................32
3.15.10 Test Registers..............................................................................................................................................................................................32
3.15.11 Scratchpad Registers ..............................................................................................................................................................................32
3.15.12 EPLD Interrupt Register – Offset 0x00000020 .............................................................................................................................33
3.15.13 Software Reset Register – Offset 0x00000040............................................................................................................................33
3.15.14 Semaphore Register – Offset 0x00000060 ...................................................................................................................................34
3.16 General Purpose I/O Controller .................................................................................................................................................34
3.16.1 GPIO Direction Control Register – Offset 0x00000400 ...............................................................................................................35
3.16.2 GPIO Data Register – Offset 0x00000402.........................................................................................................................................35
3.16.3 GPIO Polarity Control Register – Offset 0x00000404 ..................................................................................................................35
3.16.4 GPIO Interrupt Mode Register – Offset 0x00000406 ...................................................................................................................35
3.16.5 GPIO Interrupt Active Register – Offset 0x00000408 ..................................................................................................................36
3.16.6 GPIO Interrupt Enable Register – Offset 0x0000040A ................................................................................................................36
3.16.7 GPIO Masked Interrupt Status Register – Offset 0x0000040C................................................................................................36
3.17 CompactPCI Arbiter ........................................................................................................................................................................36
3.18 Resets ....................................................................................................................................................................................................37
3.19 Interrupts..............................................................................................................................................................................................38
3.20 JTAG........................................................................................................................................................................................................39
3.21 LEDs ........................................................................................................................................................................................................40
3.22 Front Panel ..........................................................................................................................................................................................41
4 • Connectors................................................................................................................................................ 42
4.1 J2 Connector Pinout..........................................................................................................................................................................43
4.1.1 System Controller Card (IMP2B-xxxxA).................................................................................................................................................43
4.1.2 Peripheral Only Card (IMP2B-xxxxB) ......................................................................................................................................................44
4.1.3 Limited Host, Full PMC User I/O Card (IMP2B-xxxxD) .....................................................................................................................45
4.1.4 System Controller Card – Alternative PMC I/O (IMP2B-xxxxE)....................................................................................................46
4.1.5 J2 Connector Signal Descriptions...........................................................................................................................................................47
4.1.6 PMC Rear I/O Tracking..................................................................................................................................................................................47
4.2 JTAG Test Header (P38)....................................................................................................................................................................47
A • Specifications........................................................................................................................................... 48
A.1 Technical Specification....................................................................................................................................................................48
A.2 Electrical Specification.....................................................................................................................................................................49
A.3 Weight......................................................................................................................................................................................................50
A.4 Reliability (MTBF)..................................................................................................................................................................................50
A.5 Product Codes......................................................................................................................................................................................51
A.6 Software Support................................................................................................................................................................................51
A.7 Development Tools............................................................................................................................................................................52
A.8 I/O Modules ...........................................................................................................................................................................................52
Index .................................................................................................................................................................... 53

6IMP2B 3U cPCI Single Board Computer Publication No. IMP2B-0HH/5
List of Tables
Table 2-1 Link Functions...............................................................................................................................................................................10
Table 2-2 Suggested Link Settings ..........................................................................................................................................................11
Table 2-3 Links P2 1-2 and 3-4..................................................................................................................................................................11
Table 2-4 Link P2 5-6......................................................................................................................................................................................12
Table 2-5 Link P3 1-2......................................................................................................................................................................................12
Table 2-6 Links P3 3-4 and 5-6..................................................................................................................................................................13
Table 2-7 Link P4 1-2......................................................................................................................................................................................13
Table 2-8 Link P4 3-4......................................................................................................................................................................................14
Table 2-9 Link P4 5-6......................................................................................................................................................................................14
Table 2-10 Link P5 1-2...................................................................................................................................................................................14
Table 2-11 Link P5 3-4...................................................................................................................................................................................15
Table 3-1 SDRAM Options............................................................................................................................................................................18
Table 3-2 Flash Options ................................................................................................................................................................................19
Table 3-3 Boot Image Selection................................................................................................................................................................19
Table 3-4 VxWorks Card-level Memory Map......................................................................................................................................21
Table 3-5 PMC Site IDSEL Connections..................................................................................................................................................21
Table 3-6 Alternative PMC I/O Mode Signals ......................................................................................................................................23
Table 3-7 Signal Sets Per Port in Available Modes...........................................................................................................................24
Table 3-8 I2C Device Addresses.................................................................................................................................................................26
Table 3-9 EPLD Registers..............................................................................................................................................................................28
Table 3-10 Board ID Register 1..................................................................................................................................................................29
Table 3-11 Board ID Register 2..................................................................................................................................................................29
Table 3-12 Device/Bus Information Register 1..................................................................................................................................29
Table 3-13 Device/Bus Information Register 2..................................................................................................................................30
Table 3-14 Configuration Register 1.......................................................................................................................................................30
Table 3-15 Configuration Register 2.......................................................................................................................................................31
Table 3-16 Control Register 1 .................................................................................................................................................................... 31
Table 3-17 Control Register 2 ....................................................................................................................................................................32
Table 3-18 Test Registers.............................................................................................................................................................................32
Table 3-19 Scratchpad Registers.............................................................................................................................................................32
Table 3-20 EPLD Interrupt Register .........................................................................................................................................................33
Table 3-21 Software Reset Register........................................................................................................................................................33
Table 3-22 Semaphore Register ...............................................................................................................................................................34
Table 3-23 GPIO Line to Register Bit Mapping ................................................................................................................................... 35
Table 3-24 Reset Causes..............................................................................................................................................................................37
Table 3-25 Interrupt Mapping....................................................................................................................................................................38
Table 3-26 Interrupt Combination ...........................................................................................................................................................38
Table 3-27 JTAG Chains................................................................................................................................................................................39
Table 3-28 LEDs ................................................................................................................................................................................................40
Table 3-29 BIT Status LEDs..........................................................................................................................................................................41
Table 4-1 Connector Functionality ..........................................................................................................................................................42

Publication No. IMP2B-0HH/5 List of Tables 7
Table 4-2 J2 Pinout (System Controller) ................................................................................................................................................43
Table 4-3 J2 Pinout (Peripheral Only)......................................................................................................................................................44
Table 4-4 J2 Pinout (Limited Host, Full PMC User I/O) ....................................................................................................................45
Table 4-5 J2 Pinout (System Controller- Alternative PMC I/O)....................................................................................................46
Table 4-6 J2 Signal Descriptions ..............................................................................................................................................................47
Table A-1 Technical Specification ............................................................................................................................................................48
Table A-2 Voltage Supply Requirements ..............................................................................................................................................49
Table A-3 Power Dissipation.......................................................................................................................................................................49
Table A-4 Reliability (MTBF)..........................................................................................................................................................................50
Table A-5 Product Codes..............................................................................................................................................................................51
List of Figures
Figure 1-1 View of IMP2B ................................................................................................................................................................................9
Figure 2-1 Link Positions (Top) ...................................................................................................................................................................10
Figure 3-1 Block Diagram ............................................................................................................................................................................16
Figure 3-2 RS422/485 Signal Definition ................................................................................................................................................24
Figure 3-3 LED Positions...............................................................................................................................................................................40
Figure 3-4 Front Panel...................................................................................................................................................................................41
Figure 4-1 Connector Positions.................................................................................................................................................................42

8IMP2B 3U cPCI Single Board Computer Publication No. IMP2B-0HH/5
1 • Overview
Available with the PowerPC MC7448 RISC CPU with integrated L2 cache, running at
up to 1.4 GHz, the IMP2B is based around a Marvell Discovery V (MV64560)
Integrated System Controller, which combines high performance system control
with multiple communication peripherals including high speed serial and dual
Ethernet ports, all on a single chip.
1.1 Features
•Freescale MPC7448 processor clocked at up to 1.4 GHz
•Marvell MV64560 bridge (‘Discovery V’)
•Up to 1 GByte of DDR2-400 SDRAM with ECC (512 MBytes as standard)
•Up to 256 MBytes of Spansion Flash memory (128 MBytes as standard)
•128 KByte AutoStore NVRAM
•32-bit/66 MHz CompactPCI interface (3.3 V signaling only)
•64-bit/133 MHz PCI-X to PMC site (3.3 V signaling only)
•1 to 49 PMC user rear I/O (1 to 64 if built in ‘Peripheral Only’ or ‘Limited Host,
Full PMC User I/O’ modes)
•Two serial ports, software-configurable for RS232/RS422, asynchronous only
•One 10/100/1000BaseT or two 10/100BaseT Ethernet channels, software selectable
•Two USB 2.0 Host Ports (OHCI/EHCI compliant) with power controllers
•4 bits of discrete digital I/O, each bit able to generate an interrupt
•Four 32-bit timers
•Six DMA channels including two XOR DMA engines for CRC32 calculation,
memory initialization and ECC error correction
•Watchdog timer
•Real-time clock
•Elapsed time indicator

Publication No. IMP2B-0HH/5 Overview 9
Figure 1-1 View of IMP2B

10 IMP2B 3U cPCI Single Board Computer Publication No. IMP2B-0HH/5
2 • Configuration
The IMP2B is delivered with push-on jumpers, but for rugged or military
applications, use optional zero Ohm resistors.
This manual refers to link settings as “In” or “Out”. Meanings are as follows:
In = jumper fitted -
Out = jumper not fitted -
TIP
Before changing any of the link options, refer to the appropriate section(s) in the following pages.
Figure 2-1 Link Positions (Top)
2.1 Link Functions
Table 2-1 Link Functions
Link Pins Function Link Pins Function
P5
5-6 Spare
P3
5-6 User Flash write enable
3-4 NVRAM write enable 3-4 Boot Flash write enable
1-2 Force CPCI 33 MHz operation 1-2 Flash protection password unlock
P4
5-6 Backplane JTAG AutoWrite enable
P2
5-6 Backplane Flash programming
3-4 Backplane JTAG buffer enable 3-4 Use Recovery Flash boot image
1-2 JTAG Scanbridge enable 1-2 Use Alternate Flash boot image
P1 All Factory test only
The IMP2B is shipped with no jumpers fitted.

Publication No. IMP2B-0HH/5 Configuration 11
2.2 Suggested Link Settings
For initial testing of the board, the following link settings are recommended:
Table 2-2 Suggested Link Settings
Link Setting Function
P5 5-6 Out Spare link
P5 3-4 Out NVRAM write protected
P5 1-2 Out CPCI speed defined by system
P4 5-6 Out Backplane JTAG AutoWrite not connected
P4 3-4 Out Backplane JTAG signals disabled
P4 1-2 Out JTAG Scanbridge disabled
P3 5-6 Out User Flash write protected
P3 3-4 Out Boot Flash write protected
P3 1-2 Out Flash Password not visible
P2 5-6 Out Normal operation
P2 3-4 Out Use Main boot image
P2 1-2 Out
P1 Out Factory test only
2.3 Factory Test Link (P1)
This link is for factory test use only and should not be fitted.
2.4 Flash Boot Image Select Links (P2 1-2 and 3-4)
The Boot Flash is divided into four sections, with all sections accessible all of the
time. This allows for three user boot images to be stored in the Flash, along with a
factory-programmed recovery boot image. Using these links, the four sections can be
swapped around in the memory map, selecting which image is used at boot time.
The state of the links is reflected in Configuration Register 1 in the EPLD. With no
jumpers fitted, the IMP2B boots from the default (Main) boot image; when a jumper
is fitted on either of the links, the IMP2B boots from another boot image, as follows:
Table 2-3 Links P2 1-2 and 3-4
1-2 3-4 Boot Image Selected
Out Out Main (default)
In Out Alternate
Out In Recovery
In In Extended

12 IMP2B 3U cPCI Single Board Computer Publication No. IMP2B-0HH/5
2.5 Backplane Flash Programming Link (P2 5-6)
This link holds the IMP2B’s processor in reset, allowing another processor card to
program the IMP2B’s Flash across the CompactPCI backplane. This is for use during
production programming only.
Table 2-4 Link P2 5-6
Link Function
Out Normal operation
In Backplane Flash Programming mode
2.6 Flash Protection Password Unlock Link (P3 1-2)
Fitting a jumper across this link allows software to read the password used to
disable the persistent mode sector protection (which remains unchanged following a
reset or a power-cycle). See the Flash Sector Protection section for further details.
Not fitting a jumper prevents the software from altering any previously configured
sector protection.
Table 2-5 Link P3 1-2
Link Meaning
Out Flash sector protection cannot be altered
In Flash sector protection can be altered

Publication No. IMP2B-0HH/5 Configuration 13
2.7 Boot Flash Write Enable Link (P3 3-4) and
User Flash Write Enable Link (P3 5-6)
These links tell the software how it should configure the default non-persistent
sector protection of the Boot and User areas of Flash. This emulates the type of
protection previously implemented in hardware for users who are familiar with
previous revisions of, or are using, existing software on the IMP2B. The state of these
links is reflected in the EPLD Configuration Register 1.
These links are provided for compatibility with previous hardware, where links
enabled write accesses to the 8 MByte Boot Area of Flash and the remaining User
Flash. These links now have no effect on the hardware interface to the Flash devices,
as all sector protection is controlled by software. See the Flash Sector Protection
section for further details.
NOTE
After the boot sequence, user software may alter sector protection at any time.
Table 2-6 Links P3 3-4 and 5-6
Link Meaning
Out Boot/User Flash sectors are write-protected by default
In Boot/User Flash sectors are write-enabled by default
CAUTION
P3 3-4 and/or P3 5-6 out provides no hardware write protection. Software provides all Flash write
protection
2.8 JTAG Scanbridge Enable Link (P4 1-2)
The IMP2B uses a JTAG Scanbridge device to connect all of the JTAG-compliant
devices on the board. This link is provided to enable the Scanbridge during test and
should not normally be fitted in deployed systems.
Table 2-7 Link P4 1-2
Link Function
Out JTAG Scanbridge disabled
In JTAG Scanbridge enabled

14 IMP2B 3U cPCI Single Board Computer Publication No. IMP2B-0HH/5
2.9 Backplane JTAG Buffer Enable Link (P4 3-4)
This link allows the JTAG Scanbridge to be driven from the backplane signals as
allocated by PICMG 2.0, Rev 3.0.
Table 2-8 Link P4 3-4
Link Function
Out Backplane JTAG signals disabled
In Backplane JTAG signals enabled
NOTE
In PICMG 2.0, Rev 3.0, it is recommended that the backplane JTAG signals are not used. When this link
is out, the IMP2B does not drive these pins and so these signals may be used for any other purpose
allocated to them.
2.10 Backplane JTAG Auto-Write Enable Link (P4 5-6)
This link connects the AutoWrite signal (as used by the JTAG Technologies Flash
Programming equipment) from the backplane to the JTAG Scanbridge device.
Table 2-9 Link P4 5-6
Link Function
Out Backplane JTAG AutoWrite signal not connected
In Backplane JTAG AutoWrite signal connected
NOTE
The AutoWrite signal is allocated to a bused-reserved pin (A5) on connector J1. This link allows the
signal to be disconnected if this pin is not being used for this purpose.
2.11 Force 33 MHz Operation Link (P5 1-2)
The IMP2B is compatible with both 33 MHz and 66 MHz CompactPCI backplane
speeds. This link forces the CompactPCI backplane to operate at 33 MHz, even if the
system is capable of operating at 66 MHz. The CompactPCI bus speed can be read
from the EPLD Device/Bus Information Register 1.
Table 2-10 Link P5 1-2
Link Function
Out CompactPCI backplane speed defined by system
In CompactPCI backplane forced to 33 MHz

Publication No. IMP2B-0HH/5 Configuration 15
2.12 NVRAM/Serial EEPROM Write Enable Link (P5 3-4)
This link enables or disables writes to the NVRAM and I2C Serial EEPROM. Its status
may be read back in the EPLD Configuration Register 1.
Table 2-11 Link P5 3-4
Link Function
Out NVRAM writes disabled
In NVRAM writes enabled
NOTE
This link write-enables the I2C EEPROM in conjunction with a bit in the EPLD Control Register 1.
2.13 Spare Link (P5 5-6)
This link is reserved for future use. Its status may be read back in the EPLD
Configuration Register 1.
Also see the ‘Limited Host, Full PMC User I/O’ Mode section.
2.14 Special Linking Requirements
For ‘deployed-use’, any of the nine links on P3, P4 and P5 can be permanently made
using zero Ohm, 0402 resistors. Consult the factory for individual requirements.

16 IMP2B 3U cPCI Single Board Computer Publication No. IMP2B-0HH/5
3 • Functional Description
Figure 3-1 Block Diagram
3.1 PowerPC Processor
The PowerPC processor used on the IMP2B is a Freescale MPC7448, clocked at up to
1.4 GHz. This is a 32-bit superscalar RISC processor with the following features:
•64-bit external data bus
•On-chip 32 KByte L1 instruction and data caches
•On-chip 1 MByte L2 cache running at core frequency
•Altivec Vector Unit
•Enhanced branch prediction capabilities
•MMU and integral FPU
The processor implements a fully static architecture and offers sophisticated power
management capabilities, including Dynamic Frequency Switching, Dynamic Power
Management and Instruction Cache Throttling.
More information on the MPC7448 can be found on the Freescale website.
LINK
http://www.freescale.com/webapp/sps/library/docu_lib.jsp

Publication No. IMP2B-0HH/5 Functional Description 17
3.2 Host Bridge
The Marvell MV64560 Discovery V Bridge provides the host, memory and PCI
interface on the IMP2B. This device provides:
•Host bridge between the processor and the rest of the system
•CompactPCI interface (PCI1)
•PCI-X interface to PMC site (PCI0)
•DDR2 SDRAM memory controller
•Device Bus interface to Flash, NVRAM and EPLD devices
•Two 10/100/1000BaseT Ethernet MACs
•Two USB 2.0 host ports (OHCI/EHCI)
•Two RS232/422 asynchronous serial channels
•Four IDMA engines
•Two XOR DMA engines
•Four 32-bit timers
•Watchdog timer
•Interrupt handler
•I2C Bus interface
NOTE
At the time of writing, Discovery MV64560 data is under NDA (Non-Disclosure Agreement). Contact
Marvell for more details.

18 IMP2B 3U cPCI Single Board Computer Publication No. IMP2B-0HH/5
3.3 RAM
The IMP2B supports up to 1 GByte of DDR2 SDRAM, with 512 MBytes fitted as
standard. This is configured as a single bank (512 MBytes) or two banks (1 GByte) of
contiguous 64-bit wide memory, and is interfaced to the memory controller in the
MV64560 by a 64-bit data bus running at 200 MHz (DDR2-400).
The following table shows the RAM options available for the IMP2B:
Table 3-1 SDRAM Options
SDRAM Size (MBytes) Banks SDRAM Device Organization
512 1 64M x 16
1024 2 64M x 16
The RAM array is protected by an 8-bit ECC, capable of detecting all single-bit,
double-bit and nibble errors, and correcting single bit errors.
CAUTIONS
The second DDR2 RAM bank physically resides in the PMC ‘Keep-Out’ area. When the IMP2B is fitted
with 1 GByte of DRAM memory, the available component height in the PMC ‘Keep-Out’ region for an
install PMC is reduced from 10mm to 5mm.
Integrity of SDRAM data cannot be guaranteed during hard reset, since the memory controller is reset
and SDRAM refresh disabled.
3.4 Non-Volatile RAM (NVRAM)
A 128 KByte Simtek STK14CA8 AutoStore NVRAM is provided for non-volatile set-
up and configuration data storage. The NVRAM is configured as an 8-bit wide
device, accessed using the device bus at DEV_CS2. For more details, see the data
sheet.
LINK
http://www.simtek.com/product-selector-guide.htm
The NVRAM is write-protected by the NVRAM Write Enable Link (P5 3-4). The
status of the link may be read back in the EPLD Configuration Register 1.

Publication No. IMP2B-0HH/5 Functional Description 19
3.5 Flash Memory
The IMP2B supports up to 256 MBytes of Flash memory, with 128 MBytes fitted as
standard. This memory is implemented using Spansion S29GL512P Flash devices.
These are configured as two banks of 16-bit wide devices, accessed via the MV64560
Device Bus. The Flash supports burst accesses to allow for maximum bus bandwidth
and must be written to as 16-bits. The Flash is arranged in 128 KByte sectors and has
an erase capacity of 100,000 cycles per sector. For further details, see the S29GL512P
512 Mb page-mode Flash data sheet.
LINK
http://www.spansion.com/support/technical_documents/flash_datasheets.html
The following table shows the Flash options available for the IMP2B:
Table 3-2 Flash Options
Flash Size (MBytes) Banks Flash Bank Organization
128 2 2 x 512Mbit
256 2 2 x 1024Mbit
The Flash is divided into two areas: Boot Flash and User Flash. The top 8 MBytes of
the first bank are reserved as Boot Flash. The remainder of the Flash memory is
allocated as User Flash.
NOTE
Integrity of Flash data cannot be guaranteed if a hard reset occurs during a Flash write cycle.
3.5.1 Boot Flash
The Boot Flash, in the top 8 MBytes of Flash memory, holds initialization and
operating system boot routines. This area is divided into four 2 MByte boot images
that may be selected using links P2 1-2 and 3-4 as follows:
Table 3-3 Boot Image Selection
1-2 3-4 Boot Image Selected
Out Out Normal
In Out Alternate
Out In Recovery/BIT
In In Extended
The Recovery boot image contains a 128 KByte factory-programmed boot image,
allowing the Flash to be reprogrammed if all other boot images become unusable.
This area is not writeable by the user. The remainder of this 2 MByte boot image can
be used to store BIT results, but can only be accessed through DEV_CS3.

20 IMP2B 3U cPCI Single Board Computer Publication No. IMP2B-0HH/5
3.5.2 User Flash
The 8 MBytes of Boot Flash appears at the top of the User Flash area, with the four
boot images appearing in their physical locations unaffected by the state of links P2
1-2 and 3-4 (see above). The remainder of the Flash array is available as User Flash
and appears as a contiguous block below this. This Flash area is intended to hold
user application code or data.
3.5.3 Flash Sector Protection
The Spansion S29GL512P Flash devices provide advanced methods of sector
protection to ensure the integrity of code data contained in the Flash array.
Protection is available for each 128 KByte sector. Locked sectors cannot be erased or
programmed; they may only be read.
Hardware provides no Flash write protection; software must be used to configure
the Flash devices to protect against corruption of Flash data. The following types of
protection are provided:
1. Persistent sector protection provides non-volatile protection that remains in place
when a board is power-cycled or reset. Each Flash sector may be set as locked
(write-protected) or unlocked (write-enabled) by writing to configuration
registers within the Flash. The configuration of this protection is only possible
when the Flash Protection Password Unlock Link (P3 1-2) is fitted. If no jumper is
fitted on this link, the software is unable to change the sector protection and
those sectors that are locked may not be erased or reprogrammed under any
circumstances.
2. Non-persistent protection may also be used. This protection is only present until
a power cycle or hardware reset occurs and may be modified by user software.
NOTE
Sectors that are locked using the Persistent mode may not be unlocked using this mechanism.
The IMP2B boot software uses the non-persistent protection method to lock the
sectors in the Boot or User Flash areas depending on the state of the Boot and User
Flash Write Enable Links (P3 3-4 and 5-6). This provides a protection mode
compatible with existing hardware (where Flash write protection was provided by
hardware mechanisms).
NOTE
Do not rely on non-persistent protection, as it may be subsequently altered by software. If further
protection is required, use the Persistent protection method.
For further details of these protection mechanisms, refer to the Spansion data sheet.
LINK
http://www.spansion.com/support/technical_documents/flash_datasheets.html