SiTime ClockSoC SiT9514 Series User manual

SiT9514x GUI-UM Rev 1.04
19 February 2021
www.sitime.com
Cascade Platform of SiT9514x
ClockSoC Products
Clock Generators, Jitter Cleaners, and Network Synchronizers
GUI User Manual
Contents
1Introduction ........................................................................................................................... 3
2Document applicability.......................................................................................................... 4
3Cascade GUI installation ........................................................................................................ 5
4Starting the GUI ................................................................................................................... 10
5Functional descriptions of SiT9514x device variants........................................................... 11
6GUI usage............................................................................................................................. 17
Sections in the GUI ..................................................................................................................17
6.1.1 GUI Sections overview...............................................................................................................17
Chip Communication and Interrupt ........................................................................................18
6.2.1 Input Clock Reference section ...................................................................................................19
6.2.2 Input section..............................................................................................................................20
6.2.3 PLL section .................................................................................................................................21
6.2.4 Output section...........................................................................................................................22
6.2.5 Bird’s Eye section.......................................................................................................................23
7SiT9514x device configuration tasks.................................................................................... 24
TASK 1: Select inputs...............................................................................................................24
SiT95141, SiT95145 input configuration .................................................................................26
7.2.1 SiT95147, SiT95148 input configuration....................................................................................27
7.2.2 SiT95148 clock loss configuration..............................................................................................28
TASK 2: Set up PLL parameters................................................................................................29
TASK 3: Save or load UI configuration and program the SiT9514x device..............................31
7.4.1 Saving and loading the UI configuration file..............................................................................31
7.4.2 Using the dump function ...........................................................................................................34
7.4.3 Saving efuse.NVM.py (I2C/SPI) files...........................................................................................37
7.4.4 Saving the Cascade SiTime GUI state.........................................................................................39
7.4.5 Using the load NVM function ....................................................................................................41

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7.4.6 Using the load NVM function ....................................................................................................46
TASK 4: Use Realtime to set output frequency with DCO or view clock monitor status ........48
7.5.1 Interrupts...................................................................................................................................49
7.5.2 On-the-fly change ......................................................................................................................51
7.5.3 Managing on-the-fly frequencies ..............................................................................................52
7.5.4 Using the dump fly function ......................................................................................................53
7.5.5 Dynamic profile on-the-fly with single output per PLL..............................................................55
7.5.6 Description of dynamic header files ..........................................................................................59
Using the load fly function ......................................................................................................63
FlexIO.......................................................................................................................................64
Phase sync feature ..................................................................................................................67
Input to output delay control feature.....................................................................................69
SiT9514x jitter attenuator as timing source for JESD204B RF converters in 5G RRU .............71
7.10.1 JESD204B overview....................................................................................................................71
Cascade as clock source for JESD204B timing signals .............................................................72
Configuring the SiT9514x for JESD204B timing signals ...........................................................74
Generating SYSREF via SYSREF_REQ........................................................................................74
8Snapshots of specific use case scenarios............................................................................. 81
Free running DCO....................................................................................................................85
Zero-delay buffer mode ..........................................................................................................88
9Low wander mode ............................................................................................................... 89
10 Usage guidelines for jitter performance optimization ........................................................ 90
Output placement and frequency planning............................................................................90
CMOS output type selection ...................................................................................................93
11 Document Information ........................................................................................................ 95

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1Introduction
The SiT9514x ClockSoC™products are based on the SiTime’s Cascade Platform™that integrates multiple
clock ICs and oscillators into a single device. The SiTime ClockSoC products include clock generators,
jitter cleaners, and network synchronizers that support up to four clock inputs and up to the 11
differential or the 22 single-ended clock outputs. The clock outputs can be derived from the 4 PLLs in a
manner that provides high flexibility in terms of frequency planning options. These clocks are fully
programmable with the I2C/SPI interface for selecting the input frequency to output frequency
translations and associated jitter attenuation loop bandwidths. Using advanced design technology,
SiT9514x devices provide excellent jitter performance while working reliably under ambient
temperatures from -40°C to 85°C. These features make it ideally suited for communications applications
(e.g., OTN, SONET/SDH, xDSL, GbE, networking, wireless infrastructure, IEEE 1588 clock steering),
broadcast video with genlock, test and instrumentation applications, and high-speed data converters.
Additionally, on-chip programmable non-volatile memory enables factory preprogrammed devices that
power up with a known configuration.

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2Document applicability
This document applies to the Cascade Platform products shown in Table 1.
This document only describes operation of the Cascade SiTime GUI version 1.30.4 with the SiTime
products shown in Table 1. Operation with other versions may differ from that described in in this
document.
Refer to the user documentation for your SiTime evaluation board for information about its deployment.
Table 1: Applicable part numbers
Part
number
Number of
outputs
Device type
Supported by GUI as
described in this document
Supported
evaluation board
SiT95141
10
Clock
Generator
Yes
SiT6503EB
SiT95143
10
Clock
Generator
No —contact SiTime Technical
Support to configure
SiT6503EB
SiT95145
10
Jitter Cleaner
Yes
SiT6503EB
SiT95147
8
Network
Synchronizer
Yes
SiT6502EB
SiT95148
11
Network
Synchronizer
Yes
SiT6503EB
NOTE: About operating parameters
For this document, the application was tested using Microsoft WindowsTM 10 Pro, version 1909. Other
versions should also work in most cases.
Recommended display resolution is 1600 x 1080 or better. Other resolutions will work; however, if you
operate this application using a display with lower resolution (e.g. 1366 x 768), portions of the screen
may appear different, such as overlapping sections or wrapping of labels, buttons, fields, etc. Some
screenshots in this document were created using lower resolution and may display somewhat different
in your deployment.

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3Cascade GUI installation
Open the setup_Cascade-vn.n.n-SiTime.exe file and select the folder in which to install the Cascade GUI
application, see Figure 1 and Figure 2.
Figure 1: Selection of the destination location
Figure 2: Selection of the Start Menu folder

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Optionally, click the checkbox to create a desktop shortcut. Click Next to proceed with the installation,
see Figure 3.
Figure 3: Option to create a desktop shortcut and proceed
All SiT9514x related software is installed first, see Figure 4.
Figure 4: Ready to install

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The SiTime evaluation boards use an FTDI chip solution for the USB-to-serial interface conversion. The
FTDI driver is installed next, see Figure 5 and Figure 6.
Figure 5: Installation progress
Figure 6: Extracting FTDI CDM drivers
Click Extract to proceed with the FTDI driver installation, see Figure 7,Figure 8, and Figure 9.

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Figure 7: Click Next to start the device driver installation wizard
Figure 8: Read and accept the license agreement

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Figure 9: Finish the driver installation
Click Finish to complete setup installation Figure 10.
Figure 10: Finish the Cascade setup wizard

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4Starting the GUI
The Cascade GUI provides an easy interface to configure the selected device. Since the GUI uses the FTDI
chip for the USB-to-serial I2C communication on the SiTime evaluation board, the FTDI chip related
software drivers are also installed by the installation file.
When the Cascade GUI application is launched, the Choose Variant selection menu appears to prompt
for selection of one of the product variants. Select the SiT9514xvariant you are using and click Select.
It is possible to start and use multiple instances of the application simultaneously.
NOTE: Contact SiTime Technical Support to configure the SiT95143 device.
An example selection of the SiT95141 product variant is shown in Figure 11:
Figure 11: Option for SiT95141
The GUI software will launch for the selected SiT95141 device variant, see Figure 12.
Figure 12: GUI view for SiT9514
Users can move between the individual sections, configuring parameters, while related parameters in
the other sections remain visible. Programmed configurations can be saved in configuration profile files
containing the configuration parameters, or in sets of I2C/SPI read and write scripts for reuse, etc.

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5Functional descriptions of SiT9514x device variants
The SiT95141 is a clock generator device that offers four fractional-frequency translations from the same
input. Any one of the four clock inputs map to all four PLLs. The PLL outputs are mapped to the
10 outputs, offering flexible frequency translation configurations, see Figure 13.
The SiT95145 is a jitter attenuating frequency translation device that offers four fractional translations
from the same input. The four clock inputs map to all four PLLs. The PLL outputs can be mapped to a
subset of the 10 outputs, offering flexible frequency translation configuration with independent control
of each PLL in terms of jitter attenuation, bandwidth control, and input clock selection with redundancy,
see Figure 13.
Figure 13: SiT95141/SiT95145 overall architecture

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SiT95147 is a jitter attenuating and network synchronizing frequency translation device that offers four
independent PLLs. The four clock inputs can map to any of the four PLLs. The PLL outputs are mapped to
the eight outputs offering flexible frequency translation configurations with independent control of each
PLL in terms of jitter attenuation, bandwidth control, and input clock selection with redundancy, see
Figure 14.
Figure 14: SiT95147 overall architecture

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SiT95148 is a jitter attenuating frequency translation device that offers four independent fractional PLLs.
PLL outputs are mapped to the 11 outputs. This allows flexible frequency translation configuration with
independent control of each PLL in terms of jitter attenuation, bandwidth control, and input clock
selection with redundancy, see Figure 15.
Figure 15: SiT95148 overall architecture

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Clock hierarchy, various frequency dividers nomenclature, and clock translation pathways available are
shown in Figure 16 for the SiT95141 and SiT95145 devices.
Figure 16: SiT95141 and SiT95145 clock hierarchy

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The clock hierarchy, nomenclature of the various frequency dividers, and clock translation pathways
available for the SiT95147 are shown in Figure 17.
Figure 17: SiT95147 clock hierarchy

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The clock hierarchy, various frequency dividers nomenclature, and clock translation pathways available
on the SiT95148 device are shown in Figure 18.
Figure 18: SiT95148 clock hierarchy

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6GUI usage
Sections in the GUI
6.1.1 GUI Sections overview
The GUI layout is divided into sections, used to configure distinct sets of parameters, and unique to the
specific sections, described in detail in subsequent section of this document.
•Chip Communication –See the top-left section.
•Internal Clock Configuration –See the top-center section.
•Input (0,1,2,3) –See the left-middle section.
•PLL (A,B,C,D), Clock Switch and Lock Loss –See the center section.
•Output (0T,7,6,5,4,3,2,1,OB) –See the right-middle section.
•Bird’s Eye view –See the bottom section.
Figure 19: Sections in the GUI interface

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Chip Communication and Interrupt
The Chip Communication option allows the user to specify how to connect to the chip.
The Interrupt section is used to configure interrupt related settings.
Figure 20: Communication and interrupt options
Type of chip
communication:
Either I2C or SPI
can be selected
Chip Connection
Interrupt
Related

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6.2.1 Input Clock Reference section
The Input Clock Reference section is used to configure:
•Golden clock (for frequency drift monitoring)
•Embedded MEMS frequency
Figure 21: Input Clock Reference section
IMPORTANT:
Embedded MEMS must be set to 76.86144 MHz only. Operation in the 76.8 MHz setting is not generally
supported and should only be used if advised to do so by SiTime Technical Support.

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6.2.2 Input section
The Input section is divided into similar individual tabs for Input #(0-3) where the following parameters
can be set:
•Frequency, clock type, and clock loss/frequency drift
•FlexIO, for setting Clock Switch fine and coarse frequency drift monitors for the input clocks
•Input assignment (or not) to all PLLs
Figure 22: GUI Input section
NOTE: If no input is assigned to the PLL section, then the device’s internal PLL oscillator is the primary clock source.