Genesys Logic GL823 Guide

GL823
USB 2.0 SD/MMC Card Reader
Controller
Design Guide
Rev. 1.00
Sep 8, 2009
Genesys Logic, Inc.

GL823 Design Guide
©2009 Genesys Logic, Inc. - All rights reserved. Page 2
Copyright:
Copyright © 2009 Genesys Logic, Inc. All rights reserved. No part of the materials shall be reproduced in any
form or by any means without prior written consent of Genesys Logic, Inc.
Ownership and Title
Genesys Logic, Inc. owns and retains of its right, title and interest in and to all materials provided herein.
Genesys Logic, Inc. reserves all rights, including, but not limited to, all patent rights, trademarks, copyrights
and any other propriety rights. No license is granted hereunder.
Disclaimer
All Materials are provided “as is”. Genesys Logic, Inc. makes no warranties, express, implied or otherwise,
regarding their accuracy, merchantability, fitness for any particular purpose, and non-infringement of
intellectual property. In no event shall Genesys Logic, Inc. be liable for any damages, including, without
limitation, any direct, indirect, consequential, or incidental damages. The materials may contain errors or
omissions. Genesys Logic, Inc. may make changes to the materials or to the products described herein at
anytime without notice.
Genesys Logic, Inc.
12F, No. 205, Sec. 3, Beishin Rd., Shindian City,
Taipei, Taiwan
Tel: [phone]
Fax: [phone]
http://www.genesyslogic.com

GL823 Design Guide
©2009 Genesys Logic, Inc. - All rights reserved. Page 3
Revision History
Revision Date Description
1.00 09/08/2009 First formal release

GL823 Design Guide
©2009 Genesys Logic, Inc. - All rights reserved. Page 4
CONTENTS
1. PREFACE…. .................................................................................................. 5
2. GENERAL MAIN BOARD LAYOUT GUIDELINE ................................ 5
2.1 Component Routing and Placement...................................................... 5
2.2 Recommended Layout Sequence ........................................................... 5
2.3 Differential Signal ................................................................................... 5
2.4 Power Line ............................................................................................... 8
2.5 Card Interface Signal.............................................................................. 8

GL823 Design Guide
©2009 Genesys Logic, Inc. - All rights reserved. Page 5
1. PREFACE
The purpose of this document is to provide suggestions and descriptions for the design of PCB layout
concerning the GL823 Card Reader Controller of Genesys Logic Inc., so that the client can verify in the
shortest time and start mass production.
2. GENERAL MAIN BOARD LAYOUT GUIDELINE
2.1 Component Routing and Placement
2.1.1
2-layer PCB: Layer 1 is used for components and signals; Layer 2 is recommended used for signal routing
and continuous ground.
Table 2.1 2-Layer Board Description
Layer Description
Layer 1 Component and Signals
Layer 2 Signals
2.1.2
4-layer PCB: Layer 1 is used for component placement and signal layout, Layer 2 is GND plane, Layer 3 is
Power plane, and Layer 4 is used for component placement and signal layout.
Table 2.2 4-Layer Board Description
Layer Description
Layer 1 Components and Signals
Layer 2 Ground
Layer 3 Power
Layer 4 Components and Signals
Routing of USB2.0 D+/D- signal is recommended on Layer 1
2.2 Recommended Layout Sequence
2.2.1
D+,D- Power Trace Card Clock Interface signal Others
2.3 Differential Signal
2.3.1
The target impedance is 90 Ω
ΩΩ
Ω for 4-layer PCB.

GL823 Design Guide
©2009 Genesys Logic, Inc. - All rights reserved. Page 6
2.3.2
The space between GND or digital signal and the USB signal pairs shall be at least 20mils. Keep away from
the high speed signal or clock; the space should be at least 50mils. The width of the D+/D- tracing shall be
the same and approximate spacing (W approximate to S). See Figure 2.1.
Figure 2.1 - Differential Pair Routing Space Rule
2.3.3
USB signal traces shall be placed parallel as in Figure 2.2, not as in Figure2. 3.
Figure 2.2 - Symmetric Routing with Differential Pairs
Figure 2.3 - Bad Differential Pair Routing

GL823 Design Guide
©2009 Genesys Logic, Inc. - All rights reserved. Page 7
2.3.4
Keep differential pair in the same layer as possible; keep minimum turns and shortest length to the USB
connector. When vias are used, they should always be placed in same location and symmetric. See Figure
2.4.
2.3.5
USB signal pair (D+, D-) traces shall be have equal length, Max trace-length mismatch should be no greater
than 60 mils. And guarded by ground plane is recommended. See Figure 2.5.
Figure 2.4 - Same Locations and Symmetric Routing for Vias
Figure 2.5 - Differential Pair Guarded by Ground Plane
2.3.6
Place continuous ground area or power plane under signal traces. Please avoid crossing the different
reference power plane.

GL823 Design Guide
©2009 Genesys Logic, Inc. - All rights reserved. Page 8
2.3.7
Place continuous ground area or power plane under signal traces. Please avoid crossing the different
reference power plane.
2.4 Power Line
2.4.1
Recommend that 5V power trace is at least 30mils and the others are at least 15mils.
2.4.2
Place the bypass capacitor as close as possible to the chip, such as C7. See Figure 2.6.
Figure 2.6 - Bypass Capacitor Placement
2.4.3
It is best to have a complete GND below the IC. You can add some holes to increase the GND area. The EMI
will also have a better performance if you do so.
2.4.4
Add a series DC decoupling component (bead-100 ohm) to isolate the noise of DC-Power.
2.5 Card Interface Signal
2.5.1
The space of two adjacent trace should be greater than double of trace width (2W rule)
2.5.2
GL823’s Pin “SD_CLK” is clock signals. Please make it far away from other signals to avoid the noise
crosstalk.
2.5.3
Add a 4.7 u F capacitor at SD card power (PMOS) trace and close to SD card connector.

GL823 Design Guide
©2009 Genesys Logic, Inc. - All rights reserved. Page 9
2.5.4
When traces are encountered, please use 45 °
°°
° bends (or turns) of traces. It shows at Figure 2.7. All angles
between traces should be greater than 135 degrees. ( α
αα
α ≥
≥≥
≥ 135 °
°°
° )and the length of Band Cshould be
minimized. The number of left and right bends should be matched as closely as possible. This reduces
reflections on the signal by minimizing impedance discontinuities.
2.5.5
Keep the card bus as short as possible and keep the length of each data line equal in PCB design.
Figure 2.7 - Use the 45°
°°
°Bends, Preferred and Alternative Layout