hilscher NXHX 51-ETM Operating and installation instructions

Device Description
NXHX 51-ETM
Development Board
Hilscher Gesellschaft für Systemautomation mbH
www.hilscher.com
DOC120606HW05EN | Revision 5 | English | 2013-10 | Released | Public

Table of Contents 2/60
NXHX 51-ETM | Development Board
DOC120606HW05EN | Revision 5 | English | 2013-10 | Released | Public © Hilscher, 2012 - 2013
Table of Contents
1INTRODUCTION.........................................................................................................4
1.1 About This Manual......................................................................................................4
1.1.1 List of Revisions ...................................................................................................4
1.1.2 Conventions in this Manual ..................................................................................4
1.1.3 Reference to Hardware ........................................................................................5
1.2 Other Relevant Documentation ..................................................................................5
2DESCRIPTIONS AND DRAWINGS ............................................................................6
2.1 Description of the NXHX 51-ETM ...............................................................................6
2.2 Drawings.....................................................................................................................7
2.2.1 Block Diagram ......................................................................................................7
2.2.2 Printed Circuit Board ............................................................................................8
2.3 Operating Elements ..................................................................................................10
2.3.1 Push Buttons ......................................................................................................10
2.3.2 Switches .............................................................................................................10
2.3.3 Host Interface Configuration Jumper (X10)........................................................14
2.4 Interfaces ..................................................................................................................16
2.4.1 Host Interface (X3) .............................................................................................16
2.4.2 Mini-B USB Connector (X2, 5-pin) .....................................................................22
2.4.3 microSD Card Reader (X4) ................................................................................22
2.4.4 Fieldbus Connector (X5 - 10-pin) .......................................................................23
2.4.5 Fieldbus Connector (X6 - 10-pin) .......................................................................23
2.4.6 Serial Connector (X7 - 10-pin)............................................................................24
2.4.7 USB Connector HI TOP (X8)..............................................................................24
2.4.8 ETM Connector (X9)...........................................................................................25
2.4.9 2*RJ45 RT-Ethernet (X50) .................................................................................26
2.4.10 Power Supply +24 V (X100)...............................................................................26
2.5 LEDs .........................................................................................................................27
3USING EXTERNAL DEBUGGERS ...........................................................................28
4ACCESSORIES ........................................................................................................29
4.1 Devices for Host Interface ........................................................................................29
4.1.1 I/O Device at Host Interface (NXHX-IO).............................................................30
4.1.2 SDRAM Device at Host Interface (NXHX-SDR).................................................31
4.1.3 PHY and Serial Dual-Port Memory Device at Host Interface (NXHX-PHY).......32
4.1.4 PHY and SDR Memory Device at Host Interface (NXHX-PHYSDR) .................34
4.1.5 Parallel Dual-Port Memory at Host Interface......................................................35
4.1.6 Using NXHX 6-RE or NXHX 52-RE as Extension Bus at Host Interface ...........35
4.1.7 Accessory Cables and Connectors for Host Interface .......................................36
4.2 Fieldbus and Serial Adapters/Interfaces...................................................................37
4.2.1 NXHX-DP ...........................................................................................................38
4.2.2 NXHX-CO ...........................................................................................................38

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4.2.3 NXHX-DN ...........................................................................................................39
4.2.4 NXHX-RS ...........................................................................................................39
4.2.5 NXHX-CC ...........................................................................................................40
4.3 NXAC-Power ............................................................................................................40
4.4 NXAC-JTAG-ETM.....................................................................................................40
5REFERENCE ............................................................................................................41
5.1 Schematics ...............................................................................................................41
5.2 Bill of Materials .........................................................................................................51
5.2.1 NXHX 51-ETM....................................................................................................51
5.2.2 NXHX-IO.............................................................................................................53
5.2.3 NXHX-SDR.........................................................................................................53
5.2.4 NXHX-PHY .........................................................................................................54
5.2.5 NXHX-PHYSDR .................................................................................................55
6TECHNICAL DATA ...................................................................................................56
6.1 NXHX 51-ETM ..........................................................................................................56
7APPENDIX ................................................................................................................57
7.1 Matrix Label ..............................................................................................................57
7.2 List of Figures ...........................................................................................................57
7.3 List of Tables ............................................................................................................58
7.4 Contacts....................................................................................................................60

Introduction 4/60
NXHX 51-ETM | Development Board
DOC120606HW05EN | Revision 5 | English | 2013-10 | Released | Public © Hilscher, 2012 - 2013
1 Introduction
1.1 About This Manual
This manual describes the NXHX51-ETM development board.
1.1.1 List of Revisions
Index Date Chapter Revision
1 2012-09-03 All Created
2 2013-03-21 All
2.3.2.1
2.4.1
4.2
Structure of document revised.
Description of boot strap options (S1) revised.
Tables with pin assignments for DPM and SDRAM Modes, Extension Bus
Modes, MII Mode added.
Section Fieldbus and Serial Adapters/Interfaces: graphics added.
3 2013-07-08 4.1.7 Section Accessory Cables and Connectors for Host Interface added.
4 2013-07-16 2.3.2.1
4.1
Description of Configuration of Boot Strap Options – Switch (S1) revised.
Section Devices for Host Interface revised (formerly section Host Interfaces).
5 2013-10-28
2.3.2.2
5.1
Description of the Host Mode Configuration Switch (S2) updated for hardware
revision 4.
Schematics updated for hardware revision 4.
Table 1: List of Revisions
1.1.2 Conventions in this Manual
#means active low signal.
Notes are marked as follows:
Important: <important note>
Note: <note>
<note, where to find further information>
Positions in Figures
The Positions , , ... or , , ... or , , ... refer to the
figure used in that section. If the numbers reference to a section outside the
current section then a cross reference to that section and figure is
indicated.

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1.1.3 Reference to Hardware
Hardware Revision Part Number
NXHX51-ETM 4 7763. 200
Table 2: Reference to Hardware
1.2 Other Relevant Documentation
Besides this device description, the following documents are also relevant
for the user of the NXHX 51-ETM development board:
Manual Contents Document Name
NXHX 51-ETM Getting
Started Guide
Describes typical use cases of the
NXHX 51 ETM Development Board.
NXHX 51-ETM Getting Started GS XX EN.pdf
Migration Guide
netX 50 to netX 51/52
Describes the differences between
the netX 50 and netX 51/52.
Migration_netX50_to_netX5152_MG03EN.pdf
Programming
Reference Guide
netX 51/52
Describes all available registers of
the netX 51.
netX 51 52 Programming Reference Guide PRG
xx EN.pdf
User Manual NXPCA-
PCI
Describes the coupling of the parallel
dual-port memory with a PC.
User Manual NXPCA-PCI_Rev_2_EN.pdf
Table 3: Additional Documentation

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2 Descriptions and Drawings
2.1 Description of the NXHX 51-ETM
The NXHX 51-ETM is a development board for the netX 51 controller.
It is equipped with an netX 51 and features:
Host interface, usable in different interface modes: 8/16/32 bit parallel
dual-port memory, 16 bit TI multiplexed parallel dual-port memory, serial
dual-port memory (SPI Slave), MII and PIO
2-port RJ45 Real-Time Ethernet interface
DIP switch to configure boot mode and host interface mode
Power supply and diagnostic via USB interface
MMIO signals and I2C interface
ETM interface for debugging
System status and communication status LEDs
Quad SPI flash for Fast Start-Up feature of PROFINET IO Device
microSD Card slot
3 interfaces for additional Fieldbus and RS-232 modules
HiTOP USB debugging interface

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2.2 Drawings
2.2.1 Block Diagram
Figure 1: NXHX51-ETM Block Diagram

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2.2.2 Printed Circuit Board
Figure 2: NXHX51-ETM Printed Circuit Board
No. in
figure Name Description For details see section Page
X5 Fieldbus interface CH0 Fieldbus Connector (X5 - 10-pin) 23
X6 Fieldbus interface CH1 Fieldbus Connector (X6 - 10-pin) 23
V30 Communication status LED 0
(green / red) LEDs 27
V31 Communication status LED 1
(green / red) LEDs 27
S1 Boot strap options Configuration Boot Strap Options -
Switch (S1) 10
X9 ETM-Interface netX 51 ETM Connector (X9) 25
X7 UART0 interface Serial Connector (X7 - 10-pin) 24
SW30 4 pol. DIL switch as general input MMIO General Input - Switch (S30 13
V15 LED yellow, MMIO27 as general output LEDs 27
V14 LED yellow, MMIO26 as general output LEDs 27
V13 LED yellow, MMIO25 as general output LEDs 27
V12 LED yellow, MMIO24 as general output LEDs 27
X4 microSD Card connector microSD Card Reader (X4) 22
X8 USB connector Typ B, HiTOP USB Connector HI TOP (X8) 24
X100 24 V power connector for board Power Supply +24 V (X100) 26

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No. in
figure Name Description For details see section Page
X50 2 x RJ45 connector 2*RJ45 RT-Ethernet 26
- Matrix label Matrix Label 57
V1 System status LED (yellow / green) LEDs 27
T1 Power on reset Reset 10
X2 Mini-B USB connector Mini-B USB Connector (X2, 5-pin) 22
X3 Host interface Host Interface (X3) 16
S2 Host interface mode Configuration Host Mode - Switch
(S2) 13
X10 Host interface configuration jumper Host Interface Configuration
Jumper (X10) 14
Table 4: List of Positions on Printed Circuit Board

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2.3 Operating Elements
2.3.1 Push Buttons
2.3.1.1 Reset (T1)
T1 Function
When button is pushed, system initiates power-on reset.
Table 5: Push Button T1
Position in Figure 2: NXHX51-ETM Printed Circuit Board on page 8.
2.3.2 Switches
2.3.2.1 Configuration Boot Strap Options - Switch (S1)
Boot strap options.
S1 SW Signal Connect to Functions
1 RDY# with 390 Ωto GND
2 RUN# with 390 Ωto GND
Boot mode
3 SPI_MOSI with 1.5 kΩto +3.3 V
4 SPI_CLK with 1.5 kΩto +3.3 V
5 SPI_MISO with 1.5 kΩto +3.3 V
Host interface mode
6 RUN# SDA of Security
Memory
Access to Security Memory
ON = Enable
OFF = Disable
Note that the Security
Memory will only be
accessed if SW 1 and SW 2
(RDY# and RUN#) are set
to OFF !
Table 6: Boot Strap Options Configuration Switch S1
Position in Figure 2: NXHX51-ETM Printed Circuit Board on page 8.
The boot mode and the host interface mode are evaluated by the ROM
loader during boot.

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Boot Mode
If S1.6 is ON and S1.1 and S1.2 are both set to OFF, the boot mode is read
from the security memory. The boot mode defined in the security memory is
the FLASH boot mode (see No. 4 in the table below).
If S1.6 is set to OFF or one or both of the S1.1 and S1.2 switches are set to
ON, the security memory will not be accessed. In this case, the boot mode
is determined by S1.1 and S1.2 as described in the following table:
No. Selection S1.1 S1.2 Boot Sequence
1 FLASH/Ethernet boot mode off off 1. Boot from serial FLASH using Quad SPI
and XIP (CS0), if bootloader code is found.
2. Boot from SD card, if bootloader code is
found.
3. Boot from Ethernet CH_A with DHCP and
TFTP, if bootloader code is found.
2 Serial – UART0 and USB boot mode on off Boot from serial interface: UART0 or USB.
3 FLASH/Dual-Port Memory boot
mode
off on 1. Boot from serial FLASH using Quad SPI
and XIP (CS0), if bootloader code is found.
2. Boot from SD card, if bootloader code is
found.
3. Boot from dual-port memory. Select the host
interface mode with S1.3, S1.4 and S1.5
(as described in Table 8 on page 12).
4 FLASH boot mode on on 1. Boot from serial FLASH using Quad SPI
and XIP (CS0), if bootloader code is found.
2. Boot from SD card, if bootloader code is
found.
Table 7: Boot Mode Settings
Note: If you use boot mode 1, 2 or 4, set host interface mode to “Ignore
host interface during boot” (see following table).

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Host Interface Mode
The Host Interface Mode is selected by the signals SPI_MOSI (S1.3),
SPI_CLK (S1.4) and SPI_MISO (S1.5). The ROM code reads these signals
and uses them to initialize the Host Interface during the boot process. This
means that depending on the selected mode, signals are driven actively
from netX or from the host.
To select the right Host Interface Mode consider the following:
1. specify the device that is physically connected to the host interface of
the netX and
2. specify which device netX has to use as source or destination device
during boot.
S1.3 S1.4 S1.5 Description Usable
with boot
mode No.
Note
netX boots from the connected memory
off off off Ignore host interface during boot
Use this setting, if netX should not boot from
the host interface.
1, 2, 4
-
off off on SDRAM 16 bit data / 4 MByte
Use this setting, when using the module
NXHX-PHYSDR. SDRAM is used as
destination device.
1, 3, 4
off on off SRAM 16 bit data / 4 MB
Use this setting, if you have connected
parallel Flash (CS0) at the host interface and
netX has to boot from it. The parallel Flash is
used as source device.
- or -
Use this setting, if you have connected static
RAM (CS0, 1, 2 or 3) at the host interface.
The static RAM is used as destination device.
1, 3, 4
on off on SDRAM 32 bit data / 4 MB
Use this setting, when using the module
NXHX-SDR. SDRAM is used as destination
device.
1, 3, 4
Using this mode requires
additionally that the
destination device in the boot
block of the bootable image is
set properly.
Host CPU supported: Host CPU boots netX via Dual-Port Memory
off on on Serial dual-port memory (SPM) mode
Use this setting, if you have connected a
serial dual-port memory at the host interface
and netX has to boot from it. The serial dual-
port memory is used as source device.
3
on off off Parallel dual-port memory (DPM) 8 bit data
/ 2 KB
Use this setting, if you have connected a
parallel dual-port memory at the host interface
and netX has to boot from it. The parallel
dual-port memory is used as source device.
3
on on on Parallel dual-port memory (DPM) 8 bit data
/ 64 Kbyte
Use this setting, if you have connected a
parallel dual-port memory at the host interface
and netX has to boot from it. The parallel
dual-port memory is used as source device.
3
The dual-port memory is used
for booting netX. The netX
waits for the Host CPU, which
has to transfer the bootable
image (e. g. Second Stage
Bootloader). Therefore the
Host CPU has to use the
mailboxes of netX for
transferring the boot code.
Reserved
on on off Do not use this setting! - -
Table 8: Host Interface Mode at X3 (Settings)

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2.3.2.2 Configuration Host Mode - Switch (S2)
The host mode is evaluated by the Second Stage Bootloader during boot.
The Second Stage Bootloader uses this setting to initialize the selected
Dual-Port Memory Mode in the host interface.
Note: The S2 Switch was altered in the hardware revision 4 of the NXHX
board. Please note the different settings relating to hardware revisions ≤3
and 4 shown in the tables below.
Hardware Revisions 1 – 3:
S2 1 2 Function
ONON
OFF
Serial Dual-Port Memory Mode (SPI Slave
Mode 3)
OFF ON Parallel Dual-Port Memory Mode
16 bit mode
OFF OFF Parallel Dual-Port Memory Mode
8 bit mode
Table 9: Configuration - Switch S2, Host Mode (valid for Hardware Revisions 1 – 3)
Since Hardware Revision 4:
S2 1 2 Function
ONON
OFF
Serial Dual-Port Memory Mode (SPI Slave
Mode 3)
OFF ON Parallel Dual-Port Memory Mode
8 bit mode
OFF OFF Parallel Dual-Port Memory Mode
16 bit mode
Table 10: Configuration - Switch S2, Host Mode (valid since Hardware Revision 4)
Position in Figure 2: NXHX51-ETM Printed Circuit Board on page 8.
2.3.2.3 MMIO General Input - Switch (S30)
These four signals can be used by the user software.
S30 SW Signal Connected to Description
1 MMIO36 with 1.5 kΩto +3.3 V
2 MMIO37 with 1.5 kΩto +3.3 V
3 MMIO38 with 1.5 kΩto +3.3 V
4 MMIO39 with 1.5 kΩto +3.3 V
ON = Pull-up connected
OFF = No Pull-up connected
Table 11: DIL-Switch S30
Position in Figure 2: NXHX51-ETM Printed Circuit Board on page 8.

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2.3.3 Host Interface Configuration Jumper (X10)
These jumpers configure a few signals at the host interface according to
the connected extension modules and DPM modes.
X10 Pin Description
1 MMIO02 (netX 51)
2 MMIO05 (netX 51)
3 DPM_SIRQ# (X3 pin 4)
4 DPM_DIRQ# (X3 pin 11)
5 DPM_SIRQ# (netX 51)
6 DPM_DIRQ#/PI047 (netX 51)
7 RSTIN# (X3 pin 7)
8 DPM_A16 (netx 51)
9 RSTIN# (X3 pin 7)
10 RSTIN# (netx 51)
Table 12: Pin Assignment X10
Position in Figure 2: NXHX51-ETM Printed Circuit Board on page 8.
Use the following setting, if dual-port memory is connected:
X10 DPM Description
DPM_DIRQ# signal is connected to X3 pin 11
DPM_SIRQ# signal is connected to X3 pin 4
RSTIN# signal is connected to X3 pin 7
Table 13: X10 – Setting for Dual-Port Memory at Host Interface X3
Use the following setting, if Extension bus is connected:
X10 EXT Description
If NXHX 6-RE or NXHX 52-RE Board is connected to the host interface
and used as extension bus!
MMIO02 signal is connected to X3 pin 4 (configure MMIO02 as
interrupt input for DPM_SIRQ#)
MMIO05 signal is connected to X3 pin 11 (configure MMIO05 as
interrupt input for DPM_DIRQ#)
DPM_A16 signal is connected to X3 pin 7 (256 KB address range at
HIF)
Table 14: X10 - Setting for Extension Bus at Host Interface X3

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Use the following setting, if the NXHX-IO Board is connected:
X10 DPM Description
DPM_DIRQ#/PIO 47 is connected to X3 pin 11
Table 15: X10 - Setting for NXHX-IO Board at Host Interface X3
Use the following setting, if the NXHX-SDR Board is connected:
X10 SDRAM Description
SDRAM_CLK is connected to X3 pin 4
SDRAM RAS# is connected to X3 pin 7
Table 16: X10 - Setting for NXHX-SDR Board at Host Interface X3
Use the following setting, if the NXHX-PHY Board is connected:
X10 PHY Description
DPM_DIRQ# is connected to X3 pin 11
DPM_SIRQ# is connected to X3 pin 4
Table 17: X10 - Setting for NXHX-PHY Board at Host Interface X3
Use the following setting, if the NXHX-PHYSDR Board is connected:
X10 PHYSDR Description
SDRAM_CLK is connected to X3 pin 4
MII_RXD0 to X3 pin 11
SDRAM RAS# is connected to X3 pin 7
Table 18: X10 - Setting for NXHX-PHYSDR Board at Host Interface X3

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2.4 Interfaces
2.4.1 Host Interface (X3)
Position in Figure 2: NXHX51-ETM Printed Circuit Board on page 8.
2.4.1.1 DPM and SDRAM Modes
Host Interface ModesX3 Pin Signal
PIO SDRAM
32 Bit DPM 32 Bit DPM 8/16 Bit DPM 16 Bit
TI Multiplex
1 +3V3
2 GND
3 PIO59 SDRAM_CASn DPM_A17 DPM_A17
4 DPM_SIRQ# SDRAM_CLK
5 GND
6 RSTOUTn
7 RSTIN# or PIO58 SDRAM_RASn DPM_A16
8 PIO85 SDRAM_D15 DPM_D31
9 PIO40 SDRAM_D10 DPM_D18
10 PIO36 SDRAM_D8 DPM_D16
11 MMIO05 or PIO47 DPM_DIRQ DPM_DIRQ
12 PIO46 SDRAM_CKE DPM_RDY DPM_RDY DPM_RDY
13 GND
14 PIO52 SDRAM_DQM2n DPM_RDn DPM_RDn DPM_RDn
15 PIO44 SDRAM_DQM3n DPM_BE3n
16 PIO45 SDRAM_WEn DPM_WRn DPM_WRn DPM_WRn
17 WDG_
ACT
SDRAM_D11 DPM_D19
18 PIO35 SDRAM_D9 DPM_D17
19 PIO43 SDRAM_DQM1n DPM_BE1n DPM_BHEn DPM_BE1n
20 GND
21 PIO84 SDRAM_D14 DPM_D30
22 PIO79 DPM_D28 DPM_D28
23 PIO80 DPM_D29 DPM_D29
24 PIO51 SDRAM_CSn DPM_CSn DPM_CSn DPM_CSn
25 GND
26 PIO72 SDRAM_D13 DPM_D27
27 PIO71 SDRAM_D12 DPM_D26
28 PIO68 SDRAM_D25 DPM_D25
29 PIO67 SDRAM_D24 DPM_D24
30 PIO63 SDRAM_D23 DPM_D23
31 PIO62 SDRAM_D22 DPM_D22
32 PIO59 SDRAM_D21 DPM_D21
33 GND
34 PIO55 SDRAM_BA1 DPM_A15 DPM_A15
35 PIO54 SDRAM_BA0 DPM_A14 DPM_A14
36 PIO48 SDRAM_DQM0n DPM_A13 DPM_A13
37 PIO49 SDRAM_A12 DPM_A12 DPM_A12
Table 19: Pin Assignment X3 Host Interface DPM and SDRAM Modes (Part 1)

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Host Interface ModesX1 Pin Signal
PIO SDRAM
32 Bit DPM 32 Bit DPM 8/16 Bit DPM 16 Bit
TI Multiplex
38 PIO50 SDRAM_A11 DPM_A11 DPM_A11
39 PIO53 SDRAM_A10 DPM_A10 DPM_A10
40 PIO56 SDRAM_A9 DPM_A9 DPM_A9
41 PIO57 SDRAM_A8 DPM_A8 DPM_A8
42 PIO60 SDRAM_A7 DPM_A7 DPM_A7
43 PIO61 SDRAM_A6 DPM_A6 DPM_A6
44 PIO64 SDRAM_A5 DPM_A5 DPM_A5
45 PIO65 SDRAM_A4 DPM_A4 DPM_A4
46 PIO66 SDRAM_A3 DPM_A3 DPM_A3
47 PIO69 SDRAM_A2 DPM_A2 DPM_A2
48 PIO70 SDRAM_A1 DPM_BE2n DPM_A1 DPM_ADV
49 PIO73 SDRAM_A0 DPM_BE0n DPM_A0 DPM_BE0n
50 GND
51 PIO41 SDRAM_D31 DPM_D15 DPM_D15 DPM_AD15
52 PIO42 SDRAM_D30 DPM_D14 DPM_D14 DPM_AD14
53 PIO37 SDRAM_D27 DPM_D13 DPM_D13 DPM_AD13
54 PIO38 SDRAM_D26 DPM_D12 DPM_D12 DPM_AD12
55 PIO39 SDRAM_D19 DPM_D11 DPM_D11 DPM_AD11
56 PIO33 SDRAM_D18 DPM_D10 DPM_D10 DPM_AD10
57 PIO34 SDRAM_D17 DPM_D9 DPM_D9 DPM_AD9
58 PIO32 SDRAM_D16 DPM_D8 DPM_D8 DPM_AD8
59 PIO74 SDRAM_D7 DPM_D7 DPM_D7 DPM_AD7
60 PIO75 SDRAM_D6 DPM_D6 DPM_D6 DPM_AD6
61 PIO76 SDRAM_D5 DPM_D5 DPM_D5 DPM_AD5
62 PIO77 SDRAM_D4 DPM_D4 DPM_D4 DPM_AD4
63 PIO78 SDRAM_D3 DPM_D3 DPM_D3 DPM_AD3
64 PIO81 SDRAM_D2 DPM_D2 DPM_D2 DPM_AD2
65 PIO82 SDRAM_D1 DPM_D1 DPM_D1 DPM_AD1
66 PIO83 SDRAM_D0 DPM_D0 DPM_D0 DPM_AD0
67 +3V3
68 PIO58 SDRAM_D20 DPM_D20
Table 20: Pin Assignment X3 Host Interface DPM and SDRAM Modes (Part 2)

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2.4.1.2 Extension Bus Modes
Host Interface Modes
Extension Bus 8/16 Bit Mode
X1 Pin Signal
Extension Bus 8/16/32
Bit Mode SPM
Extension MMIO Extension
1 +3V3
2 GND
3 EXT_A17 EXT_A23
4 DPM_SIRQ#
5 GND
6 RSTOUTn
7 RSTIN# or EXT_A16 EXT_A22
8 EXT_D15
9 EXT_D10
10 EXT_D8
11 MMIO05 or EXT_CS1n EXT_INTn
12 EXT_BUSYn
13 GND
14 EXT_RDn
15 EXT_BE3n EXT_CS3n
EXT_A24
16 EXT_WRn
17 EXT_D11
18 EXT_D9
19 EXT_BE1n EXT_BHEn
20 GND
21 EXT_D14
22 EXT_D28 EXT_CS2n
23 EXT_D29 EXT_CS1n
24 EXT_CS0n EXT_CS0n
25 GND
26 EXT_D13
27 EXT_D12
28 EXT_D25 EXT_A21
29 EXT_D24 EXT_A20
30 EXT_D23 EXT_A19
31 EXT_D22 EXT_A18
32 EXT_D21 EXT_A17
33 GND
34 EXT_A15
35 EXT_A14
36 EXT_A13
37 EXT_A12
Table 21: Pin Assignment X3 Host Interface Extension Bus Modes (Part 1)

Descriptions and Drawings 19/60
NXHX 51-ETM | Development Board
DOC120606HW05EN | Revision 5 | English | 2013-10 | Released | Public © Hilscher, 2012 - 2013
Host Interface Modes
Extension Bus 8/16 Bit Mode
X1 Pin Signal
Extension Bus 8/16/32
Bit Mode SPM
Extension MMIO Extension
38 EXT_A11
39 EXT_A10
40 EXT_A9
41 EXT_A8
42 EXT_A7
43 EXT_A6
44 EXT_A5
45 EXT_A4
46 EXT_A3
47 EXT_A2
48 EXT_A1
EXT_BE2n
EXT_A1
49 EXT_A0
EXT_BE0n
50 GND
51 EXT_D31 extendible
by SPM or
MMIO
SPM_SIO3 MMIO47
52 EXT_D30 extendible
by SPM or
MMIO
SPM_SIO2 MMIO46
53 EXT_D27 extendible
by SPM or
MMIO
SPM_SIRQ MMIO45
54 EXT_D26 extendible
by SPM or
MMIO
SPM_DIRQ MMIO44
55 EXT_D19 extendible
by SPM or
MMIO
SPM_CLK MMIO43
56 EXT_D18 extendible
by SPM or
MMIO
SPM_CSn MMIO42
57 EXT_D17 extendible
by SPM or
MMIO
SPM_MOSI MMIO41
58 EXT_D16 extendible
by SPM or
MMIO
SPM_MISO MMIO40
59 EXT_D7
60 EXT_D6
61 EXT_D5
62 EXT_D4
63 EXT_D3
64 EXT_D2
65 EXT_D1
66 EXT_D0
67 +3V3
68 EXT_D20 EXT_A16
Table 22: Pin Assignment X3 Host Interface Extension Bus Modes (Part 2)

Descriptions and Drawings 20/60
NXHX 51-ETM | Development Board
DOC120606HW05EN | Revision 5 | English | 2013-10 | Released | Public © Hilscher, 2012 - 2013
2.4.1.3 MII Mode
Host Interface Modes
MII Mode, extendible
X1 Pin Signal
SPM
Extension MMIO Extension
1 +3V3
2 GND
3
4 DPM_SIRQ#
5 GND
6 RSTOUTn
7 RSTIN#
8
9
10
11 MMIO05
12 MII_RXCLK
13 GND
14
15
16
17
18
19 MII_RXER
20 GND
21
22
23
24
25 GND
26
27
28
29
30
31
32
33 GND
34
35
36 MII_TXDCLK
37 MII_TXDEN
Table 23: Pin Assignment X3 Host Interface MII Mode (Part 1)