hilscher NXHX 51-ETM User manual

DeviceDescription
NXHX51ETM
DevelopmentBoard
HilscherGesellschaftfürSystemautomationmbH
www.hilscher.com
DOC120606HW06EN|Revision6|English|201501|Released|Public

Tableofcontents 2/72
Tableofcontents
1 Introduction...............................................................................................................................4
1.1 Aboutthisdocument.........................................................................................................4
1.1.1 Descriptionofthecontents ................................................................................4
1.1.2 Listofrevisions..................................................................................................4
1.1.3 Conventionsinthisdocument ...........................................................................5
1.1.4 Referencetohardware ......................................................................................5
1.2 Otherrelevantdocumentation ..........................................................................................6
1.3 Legalnotes.......................................................................................................................6
1.3.1 Copyright ...........................................................................................................6
1.3.2 Importantnotes..................................................................................................6
1.3.3 Exclusionofliability ...........................................................................................7
1.3.4 Warranty ............................................................................................................7
1.3.5 Exportregulations..............................................................................................8
2 Descriptionsanddrawings......................................................................................................9
2.1 DescriptionoftheNXHX51ETM.....................................................................................9
2.2 Drawings ........................................................................................................................10
2.2.1 Blockdiagram..................................................................................................10
2.2.2 Printedcircuitboard.........................................................................................11
2.3 Operatingelements ........................................................................................................12
2.3.1 Pushbuttons....................................................................................................12
2.3.2 Switches ..........................................................................................................12
2.3.3 Hostinterfaceconfigurationjumper(X10) .......................................................16
2.4 Interfaces........................................................................................................................19
2.4.1 Hostinterface(X3)...........................................................................................19
2.4.2 MiniBUSBconnector(X2) .............................................................................27
2.4.3 microSDcardreader(X4)................................................................................27
2.4.4 Fieldbusconnector(X510pin) .....................................................................28
2.4.5 Fieldbusconnector(X610pin) .....................................................................28
2.4.6 Serialconnector(X710pin)..........................................................................29
2.4.7 USBconnectorHITOP(X8).............................................................................29
2.4.8 ETMconnector(X9) ........................................................................................30
2.4.9 2*RJ45RTEthernet(X50) ..............................................................................31
2.4.10 Powersupply+24V(X100).............................................................................31
2.5 LEDs...............................................................................................................................32
3 Usingexternaldebuggers .....................................................................................................33
4 Accessories ............................................................................................................................35
4.1 Devicesforhostinterface...............................................................................................35
4.1.1 Overview..........................................................................................................35
4.1.2 I/ODeviceathostinterface(NXHXIO)...........................................................35
4.1.3 SDRAMdeviceathostinterface(NXHXSDR) ...............................................37
4.1.4 PHYandserialDualPortMemorydeviceathostinterface(NXHXPHY) ......39
4.1.5 PHYandSDRmemorydeviceathostinterface(NXHXPHYSDR) ................41
4.1.6 SDRmemoryandSPIdeviceathostinterface(NXHXSDRSPI) ...................43
4.1.7 ParallelDualPortMemoryathostinterface....................................................45
4.1.8 UsingNXHX6REorNXHX52REasExtensionBusathostinterface .........46
4.1.9 Accessorycablesandconnectorsforhostinterface .......................................46
4.2 Fieldbusandserialadapters/interfaces..........................................................................47
4.2.1 NXHXDP ........................................................................................................48
NXHX51ETM|DevelopmentBoard
DOC120606HW06EN|Revision6|English|201501|Released|Public
©Hilscher2012–2015

Tableofcontents 3/72
4.2.2 NXHXCO ........................................................................................................49
4.2.3 NXHXDN ........................................................................................................49
4.2.4 NXHXRS ........................................................................................................50
4.2.5 NXHXCC ........................................................................................................50
4.3 NXACPower ..................................................................................................................51
4.4 NXACJTAGETM ..........................................................................................................51
5 Reference ................................................................................................................................52
5.1 Schematics.....................................................................................................................52
5.1.1 Reset,USB,JTAGandMMC ..........................................................................53
5.1.2 Memory............................................................................................................54
5.1.3 HIF,ETMandIOs............................................................................................55
5.1.4 Ethernetinterface ............................................................................................56
5.1.5 Powersupply ...................................................................................................57
5.1.6 NXHXIO..........................................................................................................58
5.1.7 NXHXSDRAM ................................................................................................59
5.1.8 NXHXPHY ......................................................................................................60
5.1.9 NXHXPHYSDR ..............................................................................................61
5.1.10 NXHXSDRSPI ................................................................................................62
5.2 Billofmaterials ...............................................................................................................63
5.2.1 NXHX51ETM.................................................................................................63
5.2.2 NXHXIO..........................................................................................................64
5.2.3 NXHXSDR......................................................................................................65
5.2.4 NXHXPHY ......................................................................................................65
5.2.5 NXHXPHYSDR ..............................................................................................66
5.2.6 NXHXSDRSPI ................................................................................................66
5.3 Matrixlabel .....................................................................................................................67
6 TechnicaldataNXHX51ETM................................................................................................68
Listoffigures..........................................................................................................................69
Listoftables ...........................................................................................................................70
Contacts ..................................................................................................................................72
NXHX51ETM|DevelopmentBoard
DOC120606HW06EN|Revision6|English|201501|Released|Public
©Hilscher2012–2015

Introduction 4/72
1 Introduction
1.1 Aboutthisdocument
1.1.1 Descriptionofthecontents
ThismanualdescribesthehardwareoftheNXHX51ETMdevelopment
board.
1.1.2 Listofrevisions
Index Date Revision
1 20120903 Created
2 20130321 Structureofdocumentrevised.
Descriptionofbootstrapoptions(S1)insectionConfiguration
bootstrapoptionsswitch(S1)[}page12]revised.
TableswithpinassignmentsforDPMandSDRAMModes,
ExtensionBusModes,MIIModeinsectionHostinterface
(X3)[}page19]added.
GraphicsinsectionFieldbusandserialadapters/interfaces[}
page47]added.
3 20130708 SectionAccessorycablesandconnectorsforhostinterface[
}page46]added.
4 20130716 DescriptionofConfigurationofBootStrapOptions–Switch
(S1)insectionConfigurationbootstrapoptionsswitch(S1)[
}page12]revised.
SectionDevicesforhostinterface[}page35]revised
(formerlysectionHostInterfaces).
5 20131028 DescriptionoftheHostModeConfigurationSwitch(S2)in
sectionConfigurationhostmodeswitch(S2)[}page15]
updatedforhardwarerevision4.
SchematicsinsectionSchematics[}page52]updatedfor
hardwarerevision4.
6 20150127 ChapterLegalnotes[}page6]added.
DescriptionofNXHXSDRSPIdeviceadded.
SectionHostinterface(X3)[}page19]updated.
DescriptionofNXHXPHYdeviceinsectionPHYandserial
DualPortMemorydeviceathostinterface(NXHXPHY)[}
page39]updatedaccordingtohardwarerevision2of
NXHXPHYdevice.
DepictionofsettingsforNXHXPHYBoardinsectionHost
interfaceconfigurationjumper(X10)[}page16]corrected.
Table1:Listofrevisions
NXHX51ETM|DevelopmentBoard
DOC120606HW06EN|Revision6|English|201501|Released|Public
©Hilscher2012–2015

Introduction 5/72
1.1.3 Conventionsinthisdocument
#meansactivelowsignal.
Notesaremarkedasfollows:
Notes
Important:
<Importantnote>
Note:
<Simplenote>
<Note,wheretofindfurtherinformation>
Referencetopositionsinfigures
Wheneverpositionnumberslike(1),(2)or(3)occurwithinatext
paragraph,theyusuallyrefertopositionsinthefigurenexttotheparagraph
onthesamepage.Iftheyrefertoafigureonadifferentpage,across
referencetothatfigureisgiven.
1.1.4 Referencetohardware
Hardware Revision Partnumber
NXHX51ETM 4 7763.200
Table2:Referencetohardware
NXHX51ETM|DevelopmentBoard
DOC120606HW06EN|Revision6|English|201501|Released|Public
©Hilscher2012–2015

Introduction 6/72
1.2 Otherrelevantdocumentation
Besidesthisdevicedescription,thefollowingdocumentsarealsorelevant
fortheuseroftheNXHX51ETMdevelopmentboard:
Manual Contents Documentname
NXHX51ETMGetting
StartedGuide
Describestypicalusecasesofthe
NXHX51ETMDevelopmentBoard.
NXHX51ETMGettingStartedGSXXEN.pdf
MigrationGuidenetX50to
netX51/52
Describesthedifferencesbetween
thenetX50andnetX51/52.
Migration_netX50_to_netX5152_MG03EN.pdf
ProgrammingReference
GuidenetX51/52
Describesallavailableregistersof
thenetX51.
netX5152ProgrammingReferenceGuidePRG
xxEN.pdf
UserManualNXPCAPCI Describesthecouplingofthe
paralleldualportmemorywithaPC.
UserManualNXPCAPCI_Rev_2_EN.pdf
Table3:Additionaldocumentation
1.3 Legalnotes
1.3.1 Copyright
©Hilscher2012−2015,HilscherGesellschaftfürSystemautomationmbH
Allrightsreserved.
Theimages,photographsandtextsintheaccompanyingmaterial(user
manual,accompanyingtexts,documentation,etc.)areprotectedby
Germanandinternationalcopyrightlawaswellasinternationaltradeand
protectionprovisions.Youarenotauthorizedtoduplicatetheseinwholeor
inpartusingtechnicalormechanicalmethods(printing,photocopyingor
othermethods),tomanipulateortransferusingelectronicsystemswithout
priorwrittenconsent.Youarenotpermittedtomakechangestocopyright
notices,markings,trademarksorownershipdeclarations.Theincluded
diagramsdonottakethepatentsituationintoaccount.Thecompany
namesandproductdescriptionsincludedinthisdocumentmaybe
trademarksorbrandsoftherespectiveownersandmaybetrademarkedor
patented.Anyformoffurtheruserequirestheexplicitconsentofthe
respectiverightsowner.
1.3.2 Importantnotes
Theusermanual,accompanyingtextsandthedocumentationwerecreated
fortheuseoftheproductsbyqualifiedexperts,however,errorscannotbe
ruledout.Forthisreason,noguaranteecanbegivenandneitherlegal
responsibilityforerroneousinformationnoranyliabilitycanbeassumed.
Descriptions,accompanyingtextsanddocumentationincludedintheuser
manualdonotpresentaguaranteenoranyinformationaboutproperuse
asstipulatedinthecontractorawarrantedfeature.Itcannotberuledout
thattheusermanual,theaccompanyingtextsandthedocumentationdo
notcorrespondexactlytothedescribedfeatures,standardsorotherdataof
thedeliveredproduct.Nowarrantyorguaranteeregardingthecorrectness
oraccuracyoftheinformationisassumed.
Wereservetherighttochangeourproductsandtheirspecificationaswell
asrelatedusermanuals,accompanyingtextsanddocumentationatall
timesandwithoutadvancenotice,withoutobligationtoreportthechange.
NXHX51ETM|DevelopmentBoard
DOC120606HW06EN|Revision6|English|201501|Released|Public
©Hilscher2012–2015

Introduction 7/72
Changeswillbeincludedinfuturemanualsanddonotconstituteany
obligations.Thereisnoentitlementtorevisionsofdelivereddocuments.
Themanualdeliveredwiththeproductapplies.
HilscherGesellschaftfürSystemautomationmbHisnotliableunderany
circumstancesfordirect,indirect,incidentalorfollowondamageorlossof
earningsresultingfromtheuseoftheinformationcontainedinthis
publication.
1.3.3 Exclusionofliability
ThesoftwarewasproducedandtestedwithutmostcarebyHilscher
GesellschaftfürSystemautomationmbHandismadeavailableasis.No
warrantycanbeassumedfortheperformanceandflawlessnessofthe
softwareforallusageconditionsandcasesandfortheresultsproduced
whenutilizedbytheuser.Liabilityforanydamagethatmayresultfromthe
useofthehardwareorsoftwareorrelateddocuments,islimitedtocasesof
intentorgrosslynegligentviolationofsignificantcontractualobligations.
Indemnityclaimsfortheviolationofsignificantcontractualobligationsare
limitedtodamagethatareforeseeableandtypicalforthistypeofcontract.
Itisstrictlyprohibitedtousethesoftwareinthefollowingareas:
·formilitarypurposesorinweaponsystems;
·forthedesign,construction,maintenanceoroperationofnuclear
facilities;
·inairtrafficcontrolsystems,airtrafficorairtrafficcommunication
systems;
·inlifesupportsystems;
·insystemsinwhichfailuresinthesoftwarecouldleadtopersonalinjury
orinjuriesleadingtodeath.
Weinformyouthatthesoftwarewasnotdevelopedforuseindangerous
environmentsrequiringfailproofcontrolmechanisms.Useofthesoftware
insuchanenvironmentoccursatyourownrisk.Noliabilityisassumedfor
damageorlossesduetounauthorizeduse.
1.3.4 Warranty
Althoughthehardwareandsoftwarewasdevelopedwithutmostcareand
testedintensively,HilscherGesellschaftfürSystemautomationmbHdoes
notguaranteeitssuitabilityforanypurposenotconfirmedinwriting.It
cannotbeguaranteedthatthehardwareandsoftwarewillmeetyour
requirements,thattheuseofthesoftwareoperateswithoutinterruptionand
thatthesoftwareisfreeoferrors.Noguaranteeismaderegarding
infringements,violationsofpatents,rightsofownershiporthefreedomfrom
interferencebythirdparties.Noadditionalguaranteesorassurancesare
maderegardingmarketability,freedomofdefectoftitle,integrationor
usabilityforcertainpurposesunlesstheyarerequiredinaccordancewith
thelawandcannotbelimited.Warrantyclaimsarelimitedtotherightto
claimrectification.
NXHX51ETM|DevelopmentBoard
DOC120606HW06EN|Revision6|English|201501|Released|Public
©Hilscher2012–2015

Introduction 8/72
1.3.5 Exportregulations
Thedeliveredproduct(includingthetechnicaldata)issubjecttoexportor
importlawsaswellastheassociatedregulationsofdifferentcounters,in
particularthoseofGermanyandtheUSA.Thesoftwaremaynotbe
exportedtocountrieswherethisisprohibitedbytheUnitedStatesExport
AdministrationActanditsadditionalprovisions.Youareobligatedto
complywiththeregulationsatyourpersonalresponsibility.Wewishto
informyouthatyoumayrequirepermissionfromstateauthoritiestoexport,
reexportorimporttheproduct.
NXHX51ETM|DevelopmentBoard
DOC120606HW06EN|Revision6|English|201501|Released|Public
©Hilscher2012–2015

Descriptionsanddrawings 9/72
2 Descriptionsanddrawings
2.1 DescriptionoftheNXHX51ETM
TheNXHX51ETMisadevelopmentboardforthenetX51controller.
ItisequippedwithannetX51andfeatures:
·Hostinterface,usableindifferentinterfacemodes:8/16/32bitparallel
dualportmemory,16bitTImultiplexedparalleldualportmemory,serial
dualportmemory(SPISlave),MIIandPIO
·2portRJ45RealTimeEthernetinterface
·DIPswitchtoconfigurebootmodeandhostinterfacemode
·PowersupplyanddiagnosticviaUSBinterface
·MMIOsignalsandI2Cinterface
·ETMinterfacefordebugging
·SystemstatusandcommunicationstatusLEDs
·QuadSPIflashforFastStartUpfeatureofPROFINETIODevice
·microSDCardslot
·3interfacesforadditionalFieldbusandRS232modules
·HiTOPUSBdebugginginterface
NXHX51ETM|DevelopmentBoard
DOC120606HW06EN|Revision6|English|201501|Released|Public
©Hilscher2012–2015

Descriptionsanddrawings 10/72
2.2 Drawings
2.2.1 Blockdiagram
Figure1:NXHX51ETMblockdiagram
NXHX51ETM|DevelopmentBoard
DOC120606HW06EN|Revision6|English|201501|Released|Public
©Hilscher2012–2015

Descriptionsanddrawings 11/72
2.2.2 Printedcircuitboard
Figure2:NXHX51ETMprintedcircuitboard
No.in
figure
Name Description Fordetailsseesection
(1) X5 FieldbusinterfaceCH0 Fieldbusconnector(X510pin)[}page28]
(2) X6 FieldbusinterfaceCH1 Fieldbusconnector(X610pin)[}page28]
(3) V30 CommunicationstatusLED0
(green/red)
LEDs[}page32]
(4) V31 CommunicationstatusLED1
(green/red)
(5) S1 Bootstrapoptions ConfigurationBootStrapOptionsSwitch(S1)[}
page12]
(6) X9 ETMInterfacenetX51 ETMconnector(X9)[}page30]
(7) X7 UART0interface Serialconnector(X710pin)[}page29]
(8) SW30 4pol.DILswitchasgeneralinput MMIOgeneralinputswitch(S30)[}page15]
(9) V15 LEDyellow,MMIO27asgeneraloutput LEDs[}page32]
(10) V14 LEDyellow,MMIO26asgeneraloutput
(11) V13 LEDyellow,MMIO25asgeneraloutput
(12) V12 LEDyellow,MMIO24asgeneraloutput
(13) X4 microSDCardconnector microSDcardreader(X4)[}page27]
(14) X8 USBconnectorTypB,HiTOP USBconnectorHITOP(X8)[}page29]
(15) X100 24Vpowerconnectorforboard Powersupply+24V(X100)[}page31]
(16) X50 2xRJ45connector 2*RJ45RTEthernet(X50)[}page31]
(17)  Matrixlabel Matrixlabel[}page67]
(18) V1 SystemstatusLED(yellow/green) LEDs[}page32]
(19) T1 Poweronreset Reset[}page12]
NXHX51ETM|DevelopmentBoard
DOC120606HW06EN|Revision6|English|201501|Released|Public
©Hilscher2012–2015

Descriptionsanddrawings 12/72
No.in
figure
Name Description Fordetailsseesection
(20) X2 MiniBUSBconnector MiniBUSBconnector(X2)[}page27]
(21) X3 Hostinterface Hostinterface(X3)[}page19]
(22) S2 Hostinterfacemode ConfigurationHostModeSwitch(S2)[}page15]
(23) X10 Hostinterfaceconfigurationjumper HostInterfaceConfigurationJumper(X10)[}page16
]
Table4:Listofpositionsonprintedcircuitboard
2.3 Operatingelements
2.3.1 Pushbuttons
2.3.1.1 Reset(T1)
T1 Function
Whenbuttonispushed,systeminitiatespoweronreset.
Table5:PushbuttonT1
Position(19)insectionPrintedcircuitboard[}page11].
2.3.2 Switches
2.3.2.1 Configurationbootstrapoptionsswitch(S1)
Bootstrapoptions.
S1 SW Signal Connectto Functions
1 RDY# with390ΩtoGND Bootmode
2 RUN# with390ΩtoGND
3 SPI_MOSI with1.5kΩto+3.3V Hostinterfacemode
4 SPI_CLK with1.5kΩto+3.3V
5 SPI_MISO with1.5kΩto+3.3V
6 RUN# SDAofSecurity
Memory
AccesstoSecurityMemory
ON=Enable
OFF=Disable
NotethattheSecurity
Memorywillonlybe
accessedifSW1andSW2
(RDY#andRUN#)areset
toOFF!
Table6:BootstrapoptionsconfigurationswitchS1
Position(5)insectionPrintedcircuitboard[}page11].
ThebootmodeandthehostinterfacemodeareevaluatedbytheROM
loaderduringboot.
NXHX51ETM|DevelopmentBoard
DOC120606HW06EN|Revision6|English|201501|Released|Public
©Hilscher2012–2015

Descriptionsanddrawings 13/72
Bootmode
IfS1.6isONandS1.1andS1.2arebothsettoOFF,thebootmodeisread
fromthesecuritymemory.Thebootmodedefinedinthesecuritymemoryis
theFLASHbootmode(seeNo.4inthetablebelow).
IfS1.6issettoOFForoneorbothoftheS1.1andS1.2switchesaresetto
ON,thesecuritymemorywillnotbeaccessed.Inthiscase,thebootmode
isdeterminedbyS1.1andS1.2asdescribedinthefollowingtable:
No. Selection S1.1 S1.2 Bootsequence
1 FLASH/Ethernetbootmode off off 1.BootfromserialFLASHusingQuadSPIand
XIP(CS0),ifbootloadercodeisfound.
2.BootfromSDcard,ifbootloadercodeis
found.
3.BootfromEthernetCH_AwithDHCPand
TFTP,ifbootloadercodeisfound.
2 Serial–UART0andUSBbootmode on off Bootfromserialinterface:UART0orUSB.
3 FLASH/DualPortMemorybootmode off on 1.BootfromserialFLASHusingQuadSPIand
XIP(CS0),ifbootloadercodeisfound.
2.BootfromSDcard,ifbootloadercodeis
found.
3.Bootfromdualportmemory.Selectthehost
interfacemodewithS1.3,S1.4andS1.5(as
describedinTable8).
4FLASHbootmode on on 1.BootfromserialFLASHusingQuadSPIand
XIP(CS0),ifbootloadercodeisfound.
2.BootfromSDcard,ifbootloadercodeis
found.
Table7:Bootmodesettings
Note:
Ifyouusebootmode1,2or4,sethostinterfacemodeto“Ignore
hostinterfaceduringboot”(seefollowingtable).
NXHX51ETM|DevelopmentBoard
DOC120606HW06EN|Revision6|English|201501|Released|Public
©Hilscher2012–2015

Descriptionsanddrawings 14/72
Hostinterfacemode
ThehostinterfacemodeisselectedbythesignalsSPI_MOSI(S1.3),
SPI_CLK(S1.4)andSPI_MISO(S1.5).TheROMcodereadsthesesignals
andusesthemtoinitializethehostinterfaceduringthebootprocess.This
meansthatdependingontheselectedmode,signalsaredrivenactively
fromnetXorfromthehost.
Toselecttherighthostinterfacemodeconsiderthefollowing:
1. specifythedevicethatisphysicallyconnectedtothehostinterfaceof
thenetXand
2. specifywhichdevicenetXhastouseassourceordestinationdevice
duringboot.
S1.3 S1.4 S1.5 Description Usablewith
bootmode
No.
Note
netXbootsfromtheconnectedmemory:
off off off Ignorehostinterfaceduringboot
Usethissetting,ifnetXshouldnotbootfrom
thehostinterface.
1,2,4 
off off on SDRAM16bitdata/4MByte
Usethissetting,whenusingthemoduleNXHX
PHYSDR.SDRAMisusedasdestination
device.
1,3,4 Usingthismoderequires
additionallythatthedestination
deviceinthebootblockofthe
bootableimageissetproperly.
off on off SRAM16bitdata/4MB
Usethissetting,ifyouhaveconnectedparallel
Flash(CS0)atthehostinterfaceandnetXhas
tobootfromit.TheparallelFlashisusedas
sourcedevice.
or
Usethissetting,ifyouhaveconnectedstatic
RAM(CS0,1,2or3)atthehostinterface.The
staticRAMisusedasdestinationdevice.
1,3,4
on off on SDRAM32bitdata/4MB
Usethissetting,whenusingthemoduleNXHX
SDR.SDRAMisusedasdestinationdevice.
1,3,4
HostCPUsupported:HostCPUbootsnetXviaDualPortMemory:
off on on Serialdualportmemory(SPM)mode
Usethissetting,ifyouhaveconnectedaserial
dualportmemoryatthehostinterfaceandnetX
hastobootfromit.Theserialdualportmemory
isusedassourcedevice.
3 Thedualportmemoryisused
forbootingnetX.ThenetXwaits
fortheHostCPU,whichhasto
transferthebootableimage
(e.g.SecondStage
Bootloader).ThereforetheHost
CPUhastousethemailboxes
ofnetXfortransferringtheboot
code.
on off off Paralleldualportmemory(DPM)8bitdata/
2KB
Usethissetting,ifyouhaveconnecteda
paralleldualportmemoryatthehostinterface
andnetXhastobootfromit.Theparalleldual
portmemoryisusedassourcedevice.
3
on on on Paralleldualportmemory(DPM)8bitdata/
64Kbyte
Usethissetting,ifyouhaveconnecteda
paralleldualportmemoryatthehostinterface
andnetXhastobootfromit.Theparalleldual
portmemoryisusedassourcedevice.
3
Reserved:
on on off Donotusethissetting!  
Table8:HostinterfacemodeatX3(settings)
NXHX51ETM|DevelopmentBoard
DOC120606HW06EN|Revision6|English|201501|Released|Public
©Hilscher2012–2015

Descriptionsanddrawings 15/72
2.3.2.2 Configurationhostmodeswitch(S2)
ThehostmodeisevaluatedbytheSecondStageBootloaderduringboot.
TheSecondStageBootloaderusesthissettingtoinitializetheselected
DualPortMemoryModeinthehostinterface.
Note:
TheS2Switchwasalteredinthehardwarerevision4oftheNXHX
board.Pleasenotethedifferentsettingsrelatingtohardware
revisions≤3and4showninthetablesbelow.
Hardwarerevisions1–3:
S2 1 2 Function
ON ON SerialDualPortMemoryMode(SPISlave
Mode3)
OFF
OFF ON ParallelDualPortMemoryMode
16bitmode
OFF OFF ParallelDualPortMemoryMode
8bitmode
Table9:ConfigurationSwitchS2,hostmode(validforhardwarerevisions1–3)
Sincehardwarerevision4:
S2 1 2 Function
ON ON SerialDualPortMemoryMode(SPISlave
Mode3)
OFF
OFF ON ParallelDualPortMemoryMode
8bitmode
OFF OFF ParallelDualPortMemoryMode
16bitmode
Table10:ConfigurationSwitchS2,hostmode(validsincehardwarerevision4)
Position(22)insectionPrintedcircuitboard[}page11].
2.3.2.3 MMIOgeneralinputswitch(S30)
Thesefoursignalscanbeusedbytheusersoftware.
S30 SW Signal Connectedto Description
1 MMIO36 with1.5kΩto+3.3V ON=Pullupconnected
OFF=NoPullupconnected
2 MMIO37 with1.5kΩto+3.3V
3 MMIO38 with1.5kΩto+3.3V
4 MMIO39 with1.5kΩto+3.3V
Table11:DILSwitchS30
Position(8)insectionPrintedcircuitboard[}page11].
NXHX51ETM|DevelopmentBoard
DOC120606HW06EN|Revision6|English|201501|Released|Public
©Hilscher2012–2015

Descriptionsanddrawings 16/72
2.3.3 Hostinterfaceconfigurationjumper(X10)
Thesejumpersconfigureafewsignalsatthehostinterfaceaccordingto
theconnectedextensionmodulesandDPMmodes.
X10 Pin Description
1 MMIO02(netX51)
2 MMIO05(netX51)
3 DPM_SIRQ#(X3pin4)
4 DPM_DIRQ#(X3pin11)
5 DPM_SIRQ#(netX51)
6 DPM_DIRQ#/PI047(netX51)
7 RSTIN#(X3pin7)
8 DPM_A16(netx51)
9 RSTIN#(X3pin7)
10 RSTIN#(netx51)
Table12:PinassignmentX10
Position(23)insectionPrintedcircuitboard[}page11].
Usethefollowingsettingifdualportmemoryisconnected:
X10DPM Description
DPM_DIRQ#signalisconnectedtoX3pin11
DPM_SIRQ#signalisconnectedtoX3pin4
RSTIN#signalisconnectedtoX3pin7
Table13:X10–SettingforDualPortMemoryathostinterfaceX3
UsethefollowingsettingifExtensionbusisconnected:
X10EXT Description
IfNXHX6REorNXHX52REBoardisconnectedtothehostinterface
andusedasextensionbus!
MMIO02signalisconnectedtoX3pin4(configureMMIO02as
interruptinputforDPM_SIRQ#)
MMIO05signalisconnectedtoX3pin11(configureMMIO05as
interruptinputforDPM_DIRQ#)
DPM_A16signalisconnectedtoX3pin7(256KBaddressrangeat
HIF)
Table14:X10SettingforExtensionBusathostinterfaceX3
NXHX51ETM|DevelopmentBoard
DOC120606HW06EN|Revision6|English|201501|Released|Public
©Hilscher2012–2015

Descriptionsanddrawings 17/72
UsethefollowingsettingiftheNXHXIOBoardisconnected:
X10DPM Description
DPM_DIRQ#/PIO47isconnectedtoX3pin11
Table15:X10SettingforNXHXIOBoardathostinterfaceX3
UsethefollowingsettingiftheNXHXSDRBoardisconnected:
X10SDRAM Description
SDRAM_CLKisconnectedtoX3pin4
SDRAMRAS#isconnectedtoX3pin7
Table16:X10SettingforNXHXSDRBoardathostinterfaceX3
UsethefollowingsettingiftheNXHXPHYBoardisconnected:
X10PHY Description
DPM_DIRQ#isconnectedtoX3pin11
DPM_SIRQ#isconnectedtoX3pin4
Table17:X10SettingforNXHXPHYBoardathostinterfaceX3
NXHX51ETM|DevelopmentBoard
DOC120606HW06EN|Revision6|English|201501|Released|Public
©Hilscher2012–2015

Descriptionsanddrawings 18/72
UsethefollowingsettingiftheNXHXPHYSDRBoardisconnected:
X10PHYSDR Description
SDRAM_CLKisconnectedtoX3pin4
MII_RXD0toX3pin11
SDRAMRAS#isconnectedtoX3pin7
Table18:X10SettingforNXHXPHYSDRBoardathostinterfaceX3
UsethefollowingsettingiftheNXHXSDRSPIBoardisconnected:
X10SDRSPI Description
SDRAM_CLKisconnectedtoX3pin4
DPM_DIRQ#/PIO47isconnectedtoX3pin11
SDRAMRAS#isconnectedtoX3pin7
Table19:X10SettingforNXHXSDRSPIBoardathostinterfaceX3
NXHX51ETM|DevelopmentBoard
DOC120606HW06EN|Revision6|English|201501|Released|Public
©Hilscher2012–2015

Descriptionsanddrawings 19/72
2.4 Interfaces
2.4.1 Hostinterface(X3)
Position(21)insectionPrintedcircuitboard[}page11].
2.4.1.1 DPMmodes
X3 Pin Signal Hostinterfacemodes
PIO DPM
32Bit
DPM
8/16Bit
DPM
16Bit
TIMultiplex
1 +3V3
2 GND
3 PIO59 DPM_A17 DPM_A17
4 DPM_SIRQ#
5 GND
6 RSTOUTn
7 RSTIN#or PIO58 DPM_A16
8 PIO85 DPM_D31
9 PIO40 DPM_D18
10 PIO36 DPM_D16
11 MMIO05or PIO47 DPM_DIRQ DPM_DIRQ
12 PIO46 DPM_RDY DPM_RDY DPM_RDY
13 GND
14 PIO52 DPM_RDn DPM_RDn DPM_RDn
15 PIO44 DPM_BE3n
16 PIO45 DPM_WRn DPM_WRn DPM_WRn
17 WDG_ACT DPM_D19
18 PIO35 DPM_D17
19 PIO43 DPM_BE1n DPM_BHEn DPM_BE1n
20 GND
21 PIO84 DPM_D30
22 PIO79 DPM_D28
23 PIO80 DPM_D29
24 PIO51 DPM_CSn DPM_CSn DPM_CSn
25 GND
26 PIO72 DPM_D27
27 PIO71 DPM_D26
28 PIO68 DPM_D25
29 PIO67 DPM_D24
30 PIO63 DPM_D23
31 PIO62 DPM_D22
32 PIO59 DPM_D21
33 GND
34 PIO55 DPM_A15 DPM_A15
35 PIO54 DPM_A14 DPM_A14
36 PIO48 DPM_A13 DPM_A13
37 PIO49 DPM_A12 DPM_A12
NXHX51ETM|DevelopmentBoard
DOC120606HW06EN|Revision6|English|201501|Released|Public
©Hilscher2012–2015

Descriptionsanddrawings 20/72
X3 Pin Signal Hostinterfacemodes
PIO DPM
32Bit
DPM
8/16Bit
DPM
16Bit
TIMultiplex
38 PIO50 DPM_A11 DPM_A11
39 PIO53 DPM_A10 DPM_A10
40 PIO56 DPM_A9 DPM_A9
41 PIO57 DPM_A8 DPM_A8
42 PIO60 DPM_A7 DPM_A7
43 PIO61 DPM_A6 DPM_A6
44 PIO64 DPM_A5 DPM_A5
45 PIO65 DPM_A4 DPM_A4
46 PIO66 DPM_A3 DPM_A3
47 PIO69 DPM_A2 DPM_A2
48 PIO70 DPM_BE2n DPM_A1 DPM_ADV
49 PIO73 DPM_BE0n DPM_A0 DPM_BE0n
50 GND
51 PIO41 DPM_D15 DPM_D15 DPM_AD15
52 PIO42 DPM_D14 DPM_D14 DPM_AD14
53 PIO37 DPM_D13 DPM_D13 DPM_AD13
54 PIO38 DPM_D12 DPM_D12 DPM_AD12
55 PIO39 DPM_D11 DPM_D11 DPM_AD11
56 PIO33 DPM_D10 DPM_D10 DPM_AD10
57 PIO34 DPM_D9 DPM_D9 DPM_AD9
58 PIO32 DPM_D8 DPM_D8 DPM_AD8
59 PIO74 DPM_D7 DPM_D7 DPM_AD7
60 PIO75 DPM_D6 DPM_D6 DPM_AD6
61 PIO76 DPM_D5 DPM_D5 DPM_AD5
62 PIO77 DPM_D4 DPM_D4 DPM_AD4
63 PIO78 DPM_D3 DPM_D3 DPM_AD3
64 PIO81 DPM_D2 DPM_D2 DPM_AD2
65 PIO82 DPM_D1 DPM_D1 DPM_AD1
66 PIO83 DPM_D0 DPM_D0 DPM_AD0
67 +3V3
68 PIO58 DPM_D20
Table20:PinassignmentX3hostinterfaceDPMmodes
NXHX51ETM|DevelopmentBoard
DOC120606HW06EN|Revision6|English|201501|Released|Public
©Hilscher2012–2015