Hitachi HD64465 User manual

Windows®CE Intelligent Peripheral Controller
HD64465
User’s Manual
ADE-602-168B
Rev. 3.0
03/08/01
Hitachi Ltd.

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particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
installation conditions and other characteristics. Hitachi bears no responsibility for failure or
damage when used beyond the guaranteed ranges. Even within the guaranteed ranges,
consider normally foreseeable failure rates or failure modes in semiconductor devices and
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semiconductor products.

Revisions and Additions in this Edition
Page Item Description
- Description of register address <Former Edition> 0x……… / ………h
<This Edition> H’………
- Description of HD64465BQ Add the description of new product “HD64465BQ”
- HD64465BP Specifications
Changed <Former Edition> PLL used in bypass mode and 48 MHz clock input into
UCK terminal
<This Edition>
PLL used in bypass mode
16 Add the description of M12 to M15 pins
Add the description of N12 to N15, P12 to P15, R12 to
R15 pins
17
Table 4.1 HD64465BP Signal
Names (by pin numbers in
alphabetical order)
26 Table 4.4 Pin Descriptions of
CPU Interface
Signal name of R1 pin
<Former Edition>
RESET#
<This Edition>
RESETPI#
Table 4.24 Pin Descriptions of
No Connected Pins Correct the table name
<Former Edition>
Pin Descriptions of LCD Interface
<This Edition>
Pin Descriptions of No Connected Pins
39
Table 4.25 Pin Descriptions of
Power/Ground Pin description of AVSS3
<Former Edition>
Ground for analog circuit (can not connected)
<This Edition>
NC (No Connected Pin)
52 6.3 Register Dexcription
Table 6.1 The Register List Of
Power Management and System
Configuration
<Former Edition>
Register Size = 2
Access Size = 2
<This Edition>
Register Size = 16
Access Size = 16

Page Item Description
54 6.3.2 System Configuration
Register (SCONFR)
Description of Bits 11 - 8
Add the following description
Note that the relationship between HW[3:0] and CPU
programmed inserted wait states (IWS) is 2 ≤1 WS ≤
1+HW[3:0]. Hence, the CPU default inserted wait
states should be 2.
58 6.3.4 System Peripheral Clock
Control Register (SPCCR) <Former Edition> Note: The parameter, Twkst, please refer the AC
timing specification.
<This Edition>
Note: The parameter, Twkst = 15 ms
59 Figure 6.1 AFECK & LCK
Related Clock Diagram Add the description ofACCLK pin
71 7.3.1 Port Data Register <Former Edition>
GPCDR -- Address: 100004018h
<This Edition>
GPEDR -- Address: H’100004018
91 Table 9.1 The Register List of
Timer Module <Former Edition> Register Size = 2
Access Size = 2
<This Edition>
Register Size = 16
Access Size = 16
93 9.2.3 TRVR1:Timer 1 Read Vlue
Register
94 9.2.4 TRVR0:Timer 0 Read
Value Register
<Former Edition> R/W value = R/O
<This Edition> R/W value = R
99 9.2.9 PWM1CS: PWM1 Clock
Scale Register
Bits 5 - 0
102 9.2.12 PWM0CS: PWM0 Clock
Scale Register
Bits 5 - 0
Delete the default value
Description of bit 7
<Former Edition> PCC0
<This Edition> PCC1
121 10.4.8 PCC1 General Control
Register (PCC1GCR)
Description of bit 4
<Former Edition> VCC0SEL1
<This Edition> VCC1SEL0

Page Item Description
152 (26) Timing control Register
(ITMCR)
Bits 5 - 0
Delete the default value
(2) ECP Address FIFO Register
(ECPAFifo) Default value of bits 2 - 0
<Former Edition> 111b
<This Edition> 111
176
(4) Device Control Register (der)
(Address H’1000A004, Mode All) Default value of bits 2 - 0
<Former Edition> 11b
<This Edition> 11
227 Table 14.3 AC97 Timing <Former Edition> Unit : Us
Ns
<This Edition> Unit : µs
ns
336 19.2.1 A/D Data Registers A to D
(ADDRA to ADDRD, ADCAL) <Former Edition> Bit 9 : AD8 Bit 8 : AD9
<This Edition> Bit 9 : AD9
Bit 8 : AD8
341 19.3.2 Acan Mode (SCAN = 1) Add the ADCSR table
352, 353 Table 20.13 AFECK clock input
AC Timing Spec. (PLL1:bypass)
(unit : ns)
Table 20.14 AFECK clock input
AC Timing Spec.
(PLL1:operatings) (unit : ns)
Table 20.15 AFECK clock input
AC Timing Spec. (PLL2:bypass)
(unit : ns)
Table 20.16 AFECK clock input
AC Timing Spec.
(PLL2:operating) (unit : ns)
New tables added
363, 364 Figure 20.26 AFECK Clock Input
Timing
Figure 20.27 UCK Clock Input
Timing
New figures added

HD64465BP Specifications Changed
1. Change in Specifications
Item changed Guaranteed value before change Guaranteed value after change
PLL stabilization time 5ms Not guaranteed
2. Major Influences Due to Above Change in Specifications
Preconditions Problems in usage
PLL used in bypass mode No problem (no standby time added)
Reset signal input after turning power on No problem (no standby time added)
PLL standby not used although oscillation stop used No problem (no standby time added)
Certain interval allowed between PLL standby and
wakeup Several seconds may be required for access by HD64465BP from CPU.
3. Countermeasures
•Use the system in a state without any problem by referring to "2." above.
•Create your program in a way to prohibit access other than to the HD64465BP system
configuration register (offset address: H'00000000 to H'00000ff0) for a certain period of time
after returning from PLL standby.
4. Debugged Version
The cause of this problem has already been clarified, which can be solved by correcting the
wiring layer. The new mask product (HD64465EBP) is available as the debugged version.

Rev. 3.0, 03/01, page i of xiii
Contents
Section 1 Features............................................................................................1
1.1 CPU Interface....................................................................................................................1
1.2 PCMCIA Controller..........................................................................................................1
1.3 AFE Interface....................................................................................................................1
1.4 GPIO Function(Port Interrupt)..........................................................................................1
1.5 Interrupt Controller ...........................................................................................................2
1.6 Power Management...........................................................................................................2
1.7 Timer.................................................................................................................................2
1.8 Keyboard Controller Interface...........................................................................................2
1.9 UART................................................................................................................................2
1.10 Printer interface.................................................................................................................3
1.11 Audio CODEC Interface...................................................................................................3
1.12 IrDA ..................................................................................................................................3
1.13 Clock Generator and PLL..................................................................................................3
1.14 USB Host Controller.........................................................................................................4
1.15 10-bit ADC........................................................................................................................4
1.16 Package .............................................................................................................................4
Section 2 General Description.........................................................................5
Section 3 System Block Diagram....................................................................7
3.1 Application Circuit............................................................................................................7
3.2 System Block Diagram......................................................................................................8
3.3 Physical Address Space.....................................................................................................9
3.4 HD64465 Memory Address ..............................................................................................10
3.5 Pin Configuration..............................................................................................................11
3.5.1 HD64465BP Top View........................................................................................11
3.5.2 HD64465BP Bottom View...................................................................................12
3.5.3 HD64465BQ Top View .......................................................................................13
3.5.4 HD64465BQ Bottom View..................................................................................14
Section 4 Pin Description................................................................................15
Section 5 Internal CPU Interface.....................................................................41
5.1 Introduction.......................................................................................................................41
5.2 CPU Interface Signal Description .....................................................................................42
5.2.1 System Bus Interface Signals...............................................................................42
5.2.2 Internal Bus Interface Signals ..............................................................................43
5.3 Function Description.........................................................................................................44

Rev. 3.0, 03/01, page ii of xiii
5.4 Signal Timing Description ................................................................................................45
5.4.1 Low Speed Timing...............................................................................................45
5.4.2 High Speed Timing ..............................................................................................47
5.5 Internal Bus Data Swap Rules...........................................................................................49
5.6 Internal Peripheral Bus AC Timing Specification.............................................................50
Section 6 Power Management and System Configuration..............................51
6.1 Overview...........................................................................................................................51
6.2 Features .............................................................................................................................51
6.3 Register Description..........................................................................................................52
6.3.1 System Module Standby Control Register (SMSCR) ..........................................52
6.3.2 System Configuration Register (SCONFR) .........................................................54
6.3.3 System Bus Control Register (SBCR)..................................................................55
6.3.4 System Peripheral Clock Control Register (SPCCR)...........................................57
6.3.5 System Peripheral S/W Reset Control Register (SPSRCR) .................................61
6.3.6 System PLL Control Register (SPLLCR) ............................................................63
6.3.7 System Revision Register (SRR)..........................................................................64
6.3.8 System Device ID Register (SDID) .....................................................................64
6.4 System Hardware Reset Timing........................................................................................65
6.4.1 Power-On Reset Output .......................................................................................65
6.4.2 Manual Reset Output............................................................................................66
Section 7 General Purpose I/O Port ................................................................67
7.1 Overview...........................................................................................................................67
7.1.1 Features................................................................................................................67
7.2 Register Configuration......................................................................................................69
7.3 Register Descriptions ........................................................................................................70
7.3.1 Port Data Register ................................................................................................70
7.3.2 Port Control Register............................................................................................72
7.3.3 Port Interrupt Control Register.............................................................................74
7.3.4 Port Interrupt Status Register...............................................................................76
Section 8 Interrupt Controller (INTC) ............................................................79
8.1 Overview...........................................................................................................................79
8.1.1 Features................................................................................................................79
8.1.2 Block Diagram .....................................................................................................80
8.1.3 Pin Configuration.................................................................................................80
8.1.4 Register Configuration.........................................................................................80
8.2 Interrupt Sources ...............................................................................................................81
8.2.1 On-Chip Module Interrupt ...................................................................................81
8.2.2 Interrupt Exception Processing and Priority.........................................................81
8.3 NIRR: Interrupt Request Register.....................................................................................82
8.4 NIMR: Interrupt Mask Register ........................................................................................84

Rev. 3.0, 03/01, page iii of xiii
8.5 NITR: Interrupt Trigger Mode Register............................................................................86
Section 9 Timer ...............................................................................................89
9.1 Overview...........................................................................................................................89
9.1.1 Features................................................................................................................89
9.1.2 Block Diagram .....................................................................................................90
9.1.3 Pin Configuration.................................................................................................91
9.1.4 Register Configuration.........................................................................................91
9.2 Timer Register...................................................................................................................92
9.2.1 TCVR1: Timer 1 Constant Value Register...........................................................92
9.2.2 TCVR0: Timer 0 Constant Value Register...........................................................93
9.2.3 TRVR1: Timer 1 Read Value Register ................................................................93
9.2.4 TRVR0: Timer 0 Read Value Register ................................................................94
9.2.5 TCR1: Timer 1 Control Register..........................................................................95
9.2.6 TCR0: Timer 0 Control Register..........................................................................96
9.2.7 TIRR: Timer Interrupt Request Register..............................................................97
9.2.8 TIDR*: Timer Interrupt Disable Register ............................................................98
9.2.9 PWM1CS: PWM 1 Clock Scale Register.............................................................99
9.2.10 PWM1LPC: PWM 1 Low Pulse Width Counter Register....................................100
9.2.11 PWM1HPC: PWM 1 High Pulse Width Counter Register ..................................101
9.2.12 PWM0CS: PWM 0 Clock Scale Register.............................................................102
9.2.13 PWM0LPC: PWM 0 Low Pulse Width Counter Register....................................103
9.2.14 PWM0HPC: PWM 0 High Pulse Width Counter Register ..................................104
9.3 Special Register Programming Sequence..........................................................................104
9.4 Interrupt Timing................................................................................................................104
9.5 A/D Trigger Signal ADTRIG#..........................................................................................106
9.6 DMA Request Enable Function.........................................................................................108
9.7 PWM Operation ................................................................................................................108
Section 10 PC Card Controller (PCC)...............................................................109
10.1 Overview...........................................................................................................................109
10.2 Features .............................................................................................................................109
10.3 Register Configuration......................................................................................................109
10.4 Register Description..........................................................................................................110
10.4.1 PCC0 Interface Status Register (PCC0ISR).........................................................110
10.4.2 PCC0 General Control Register (PCC0GCR)......................................................112
10.4.3 PCC0 Card Status Change Register (PCC0CSCR)..............................................114
10.4.4 PCC0 Card Status Change Interrupt Enable Register (PCC0CSCIER)................116
10.4.5 PCC0 Software Control Register (PCC0SCR).....................................................118
10.4.6 PCC Serial Power Switch Control Register (PCCPSR).......................................119
10.4.7 PCC1 Interface Status Register (PCC1ISR).........................................................119
10.4.8 PCC1 General Control Register (PCC1GCR)......................................................121
10.4.9 PCC1 Card Status Change Register (PCC1CSCR)..............................................123

Rev. 3.0, 03/01, page iv of xiii
10.4.10 PCC1 Card Status Change Interrupt Enable Register (PCC1CSCIER)................125
10.4.11 PCC1 Software Control Register (PCC1SCR).....................................................127
Section 11 FIR Module.....................................................................................129
11.1 Overview...........................................................................................................................129
11.1.1 Features................................................................................................................129
11.1.2 Functional Block Diagram of FIR........................................................................130
11.2 FIR Controller Register Description..................................................................................132
11.2.1 UART Register of FIR Portion ............................................................................132
11.2.2 FIR Controller Register........................................................................................133
11.2.3 Register Description.............................................................................................134
11.3 FIR Transmit Operation ....................................................................................................153
11.4 FIR Receive Operation......................................................................................................154
11.5 Example of Initialization and Programming Procedure for HP-SIR.................................156
Section 12 UART..............................................................................................157
12.1 Overview...........................................................................................................................157
12.2 Features .............................................................................................................................157
12.3 Serial Channel Register Description..................................................................................158
12.3.1 Data Register........................................................................................................158
12.3.2 Control Registers: UIER, UIIR, UFCR, UDLL, UDLM, ULCR, UMCR ...........159
12.3.3 Status Register ULSR and UMSR........................................................................164
12.4 Reset..................................................................................................................................167
12.5 Programming.....................................................................................................................168
12.5.1 Programming Sequence........................................................................................168
12.6 Software Reset...................................................................................................................168
12.7 Clock Input Operation.......................................................................................................168
12.8 FIFO Interrupt Mode Operation........................................................................................169
12.9 CAUTION.........................................................................................................................170
Section 13 Parallel Port.....................................................................................171
13.1 Overview...........................................................................................................................171
13.2 Features .............................................................................................................................171
13.3 Parallel Port Register Description .....................................................................................171
13.3.1 SPP and EPP Modes.............................................................................................173
13.3.2 ECP Mode............................................................................................................174
Section 14 Serial CODEC Interface..................................................................181
14.1 Overview...........................................................................................................................181
14.1.1 Features................................................................................................................181
14.1.2 Block Diagram .....................................................................................................182
14.2 Register Description..........................................................................................................183
14.2.1 Transmit Data Register (TDR).............................................................................184