HP Vectra VEi 7 Product manual

Technical Reference Manual
Vectra Technology
This manual is a technical reference document for engineers and
technicians providing system level support. It is assumed that the reader
possesses a detailed understanding of AT-compatible microprocessor
functions and digital addressing techniques.
Technical information that is readily available from other sources, such as
manufacturer’s proprietary publications, has not been reproduced.
This manual contains summary information only. For additional reference
material, refer to the bibliography inside this document.
HP Vectra VEi 7, VEi 8, VLi 8 and
VLi 8 SF PCs

Contents
Francais iii
Core Components and Technologies
Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Intel Celeron (Socket 370) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Intel Pentium II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Intel Pentium III. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
GTL+ Technology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pentium Processor Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chip Sets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
The Intel 440ZX AGPset (VEi 8, VLi 8 and VLi 8SF PCs). . . . . . . . . . . . 11
Intel 440ZX PAC Chip. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
The PIIX4E PCI/ISA Bridge Chip (82371EB). . . . . . . . . . . . . . . . . . . . . .13
The SiS 620/5595 Chip Set (VEi 7 PCs) . . . . . . . . . . . . . . . . . . . . . . . . . . 17
The SiS 620 Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
The SiS 5595 PCI/ISA Bridge Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Mass-Storage Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Ultra-ATA Hard Disk Drives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
DVD Drives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
AGP Graphics Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Matrox Millennium G200 AGP Graphics (VEi 8, VLi 8 and VLi 8SF PCs) . . .
26
SiS Super AGP Graphics (VEi 7 PCs). . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Crystal Integrated PCI Audio. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Network Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
HP 10/100 3Com 3C905B-TX Network Interface Card (D7504A and D7505A)
33

iv Francais
HP 10/100 Intel PRO/100+ Management Adapter (D7506A and D7507A) . .
34
LAN Card Ready Program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Input Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Standard HP Keyboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Enhanced HP Keyboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Scrolling Mouse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Connectors and Sockets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

5
Bibliography
Data sheets can be obtained at:
❒Matrox Millennium G200 AGP (graphics controller)
www.matrox.com/mga/products/millennium_g200/home.htm
❒Intel Chipsets. 440ZX AGPSet (82443ZX) and
PIIX4E PCI/ISA Bridge Chip (82371EB)
www.intel.com/design/chipsets/datashts
❒SiSChipsets.SiS620andSiS5595PCI/ISABridgeChip(includes
information on the integrated super AGP graphics controller)
www.sis.com/tw/products/pentium2/s620.htm
❒Celeron, Pentium II & Pentium III Processors
www.intel.com/design/celeron/datashts
www.intel.com/design/pentiumII/datashts
www.intel.com/design/pentiumIII/datashts
❒PC Data Sheets
www.hp.com/vectra
❒Crystal Audio
www.cirrus.com/products/overviews/cs4280.html
www.cirrus.com/products/overviews/cs4297.html
❒Intel LAN card
www.intel.com/network/products/pro100mgmt.htm
Hewlett-Packard white papers are available on a variety of subjects
including AGP graphics, SDRAM memory and the Ultra ATA/33
protocol at:
❒www.hp.com/desktop/library/wp.html

6

Core Components and Technologies
This chapter describes core components of the PCs such as processors,
chip sets, mass storage devices, graphics controllers, audio controllers,
network features and input devices.

Core Components and Technologies
Processors
8
Processors
Intel Celeron (Socket 370)
The Socket 370 Intel®Celeron™processor has the following features:
•128K on-die L2 cache
•Intel MMX™technology, which gives higher performance for media,
communications and 3D applications.
Socket 370 is a conversion of Slot 1 (used by the Pentium®II and
Pentium III) to a socket. The Socket 370 Celeron shares the same P6
microarchitecture as the Pentium II. The reduction in size achieved by
the Socket 370 Celeron is due to the integration of the L2 cache on the
processor die.
The heatsink is supplied separately from the processor. The processor
is locked in place in the plastic pin grid array (PPGA) by a lever.
Thermal efficiency is further enhanced by a heat interface gum
supplied with the heatsink.
Intel Pentium II
The Pentium II processor connects to the motherboard via a single
edge 242-contact slot (Slot 1) connector. It comes in eithera SECC or a
SECC 2 package (see “Pentium Processor Packages” below).
The Pentium II processor has several performance-enhancing features:
•Dual Independent Bus architecture, which combines a dedicated 64-
bitL2 cache bus(supportinglevelcache sizes of 512K),plus a64-bit
system bus with non-ECC that enables multiple simultaneous
transactions.
•Intel MMX technology, which improves video
compression/decompression, image manipulation, encryption and
I/O processing.
•Dynamic execution to speed up software performance.

9
Core Components and Technologies
Processors
Intel Pentium III
The Pentium III processor uses the same basic core and L2 cache as
the Pentium II. In addition to this, however, it uses 70 new multimedia-
oriented instructions known as SSE (streaming SIMD extensions).
These SIMD (single instruction multiple data) instructions enable the
CPU to perform simultaneous floating point calculations on multiple
data. This brings substantial improvements to 3D graphics, video
encoding and decoding and other floating point-intensive operations
that operate on large sets of data such as voice recognition. Like the
Pentium II, the Pentium III processor connects to the motherboard by
a Slot 1 connector. It comes in a SECC 2 package only (see “Pentium
Processor Packages” below).
GTL+ Technology
The Processor-Local (PL) bus of Socket 370 Celeron, Pentium II and
Pentium III processors, also referred to as their FSB (Front Side Bus),
is implemented in GTL+ technology. This technology features open-
drain signal drivers that are pulled-up to 1.5 V through 56 ohm
resistors on the bus, acting as bus terminators.
The supported operating frequencies of the GTL+ bus are 66 or
100 MHz. The width of the data bus is 64 bits, the width of the address
is 32 bits.
The control signals of the PL bus allows the implementation of a “split
-transaction” bus protocol. This allows the processor to send its
request (such as asking for the contents of a given memory address)
and then to release the bus, rather than waiting for the result, thereby
allowing the bus to accept another request. The target device (PCI
AGP controller chip) then requests the bus again when it is ready to
respond, and sends the requested data packet. Up to four transactions
can be outstanding at any given time.
Pentium Processor Packages
The processor and level-2 cache memory are packaged in a self-
contained, pre-sealed module, installed in a Slot 1socket on the system
board.

Core Components and Technologies
Processors
10
The heat sink is supplied with the processor, and is bolted to it by the
manufacturer. The processor is held in place by a retention mechanism.
Pentium II processors use either a Single Edge Contact Cartridge
(SECC) or a Single Edge Contact Cartridge 2 (SECC 2) packaging
technology. These packages allow the L2 cache to be tightly coupled to
the processor, while enabling the use of high volume commercial SRAM
components. The Pentium III comes in the SECC2 package only.
Pentium Processor Packaging
SECC
(Single Edge Contact
Cartridge)
SECC2
(Single Edge Contact
Cartridge 2)
Heat Sink ATXV2 SECC2 Heat Sink
Weight 237 g 130 g
Dissipation 40 W 36 W
Attach Locations Interfaces with thermal plate Substrate holes
Connector SC242 SC242
Heat SinkClip Riv screws SECC2 H/S clip
SECC 2 package
(exploded view) processor
heatsink clips
heatsink
SECC package

11
Core Components and Technologies
Chip Sets
Chip Sets
The Intel 440ZX AGPset (VEi 8, VLi 8 and VLi 8SF PCs)
The Intel 440ZX AGPset is used in conjunction with either a Socket 370
Celeron, a Pentium II or a Pentium III processor depending on the
model of PC. For information on the various configurations available,
refer to the Technical Reference Manual - Product Line Overview.
The 440ZX chip set is derived from and has the same benchmarks as
the 440BX. The only differences in features are:
•512MB of RAM supported instead of 1GB on the 440BX
•One less PCI master
•No ECC memory support.
The Intel 440ZX AGPset is comprised of two chips: the 440ZX PAC
(PCI AGP Controller) chip and the PIIX4E chip.
•The PAC chip (440ZX) is the bridge between four buses: the
Processor Local Bus (GTL+, also referred to as the Host, or Front
Side Bus), the main memory bus, the PCI bus and the AGP
(graphics) bus.
•The PIIX4E chip is the bridge between three buses: the PCI bus, the
SM bus and the ISA bus. In addition, it contains the IDE controller,
USB controller and Power Management logic.
The Intel 440ZX AGPset is contained in a Ball Grid Array (BGA)
package, giving a smaller footprint and higher reliability.
The two chips that make up the Intel 440ZX AGPset are explained
below:
Intel 440ZX PAC Chip
The 440ZX PAC chip integrates a Host-to-PCI bridge, optimized DRAM
controller and data path, and an Accelerated Graphics Port (AGP)
interface. AGP is a high performance, component level interconnect,
targeted at 3D graphics applications.

Core Components and Technologies
Chip Sets
12
Features of the Intel
440ZX Chip
Processor Local Bus
Interface The 440ZX chip monitors each cycle that is initiated by the processor,
and forwards those to the PCI bus that are not targeted at the local
memory. It translates Processor Local (PL) bus cycles into PCI bus
cycles.
The chip can support one processor at up to 100MHz Front Side Bus
clock frequency.
PCI Bus Interface The 82443ZX PCIinterface is 3.3V (5Vtolerant), 33 MHz and is PCI 2.1
compliant.
The maximum PCI burst transfer rate is 132 MB/s. The chip supports
advanced snooping for PCI master bursting, and provides a pre-fetch
mechanism dedicated for IDE read.
The PCI arbiter supports PCI bus arbitration for up to six masters using
a rotating priority mechanism. Its hidden arbitration scheme minimizes
arbitration overhead.
AGP Bus Interface A controller for the AGP (Accelerated Graphics Port) slot is integrated
inthe440ZXPACchip.ThePACchipsupports only a synchronousAGP
interface, coupling to the host bus frequency. The AGP characteristics
are described in detail in “Matrox Millennium G200 AGP Graphics (VEi
8, VLi 8 and VLi 8SF PCs)” on page 26.
Main Memory
Controller The main memory controller in the 440ZX chip supports two DIMM
slots. Each slot can host a 168-pinunbuffered SDRAM module,running
at 100MHz, for a total of up to 512 MB of dynamic random access
memory (non-ECC SDRAM).
The memory bus is 72-bits wide, comprised of 64 bits of data and 8 bits
of ECC. However, the 440ZX chip does not support ECC operation.

13
Core Components and Technologies
Chip Sets
Read/Write Buffers The440ZXchipdefinesadatabufferingschemetosupporttherequired
level of concurrent operations and provide adequate sustained
bandwidth between the DRAM subsystem and all other system
interfaces (Host, AGP and PCI).
System Clocking The 440ZX chip operates the host interface at 100MHz, the
SDRAM/core at 100MHz, PCI at 33 MHz and AGP at 66 MHz. Coupling
between all interfaces and internal logic is done in a synchronous
manner.Theclockingschemeusesanexternalclocksynthesizer(which
produces reference clocks for the host and PCI interfaces).
The PIIX4E PCI/ISA Bridge Chip (82371EB)
The universal host controller interface (UHCI) chip, known as PIIX4E,
is encapsulated in a Ball Grid Array (BGA) package.
The PIIX4E chip is a multi-function PCI device implementing a PCI-to-
ISA bridge function, a PCI IDE function, a Universal Bus host/hub
function, and an Enhanced Power Management function.

Core Components and Technologies
Chip Sets
14
Intel PIIX4E PCI-ISA Bridge Chip Block Diagram
Processor
Host-to-PCI
Bridge
(440ZX)
Main Memory
SDRAM
PCI/ISA Bridge(PIIX4E)
82371EB
PCI Bus (3.3V or 5V, 33 MHz)
ISA/EIO Bus (5V)
BIOS
SP,PP,
FDC
KBD
PCI Slots
Host Bus
USB1
USB2
GP[I,O] (30+)
SM Bus
Hard Disk
CD-ROM
BMIIDEUltra
DMA/33
Second Level
Cache
AGP Bus
Matrox G200 Memory Bus
DVD/Zip
Audio

15
Core Components and Technologies
Chip Sets
Features of the Intel PXII4E PCI-ISA Bridge Chip
PCI Bus Interface This part of the chip is responsible for transferring data between the
PCI bus and the ISA expansion bus. It performs PCI-to-ISA, andISA-to-
PCI bus cycle translation. It supports the Plug-and-Play mechanism.
Data buffers are provided, to isolate the PCI and ISA buses.
ISA Bus Interface As well as accepting cycles from the PCI bus interface, and translating
them for the ISA bus, the ISA bus interface also requests the PCI
master bridge to generate PCI cycles on behalf of a DMA or ISA master.
The ISA bus interface contains a standard ISA bus controller and data
buffering logic. It can directly support six ISA slots without external
data or address buffering.
SMBus Controller The System Management (SM) bus is a two-wire serial bus provided by
thePIIX4Econtroller.Itrunsatamaximumof16 kHz.Thebusmonitors
some of the hardware functions of the main board, both duringboot-up
andrun-time.AllaccesstotheSMbusishandledbythemainprocessor,
via the PIIX4E SM bus registers.
IDE Controller The PCI master/slave IDE controller supports four devices, two on
each of two channels.
USB Controller The PCI USB (Universal Serial Bus) controller, supports two stacked
USBconnectorsonthebackpanel.TheseportsarebuiltintothePIIX4E
controller as standard USB ports.
Ultra DMA Controller ThesevenchannelDMAcontrollerincorporatesthefunctionalityoftwo
82C37DMAcontrollers.Channels0to3arefor8-bitDMAdevices,while
channels5to 7are for16-bitdevices.The channels can beprogrammed
for any of the four transfer modes: the three active modes (single,
demand and block), can perform three different types of transfer: read,
write and verify. The address generation circuitry supports 24-bit
addresses for DMA devices.

Core Components and Technologies
Chip Sets
16
Interrupt Controller The interrupt controller incorporates the functionality of two 82C59
interrupt controllers. The two controllers are cascaded, supporting 15
interrupts (edge/level triggered).
Counter / Timer The chip contains a three-channel 82C54 counter/timer. The counters
use a division of the 14.318 MHz OSC input as the clock source.
For tips on where to find more information on the Intel 440ZX AGPset,
refer to the bibliography at the beginning of this document.

17
Core Components and Technologies
Chip Sets
The SiS 620/5595 Chip Set (VEi 7 PCs)
The SiS 620/5595 chip set is used in conjunction with a Socket 370
Celeron processor. The SiS 620/5595 chip set is comprised of two chips:
the SiS 620 host chip and the SiS 5595 PCI/ISA bridge chip.
•The SiS 620 is the bridge between three buses: the Processor Local
Bus(GTL+,alsoreferredtoastheHost,orFrontSideBus),themain
memory bus, and the PCI bus.
•TheSiS5595chipisthebridgebetweenthreebuses:thePCIbus,the
SM bus and the ISA bus. In addition, it contains the USB controller
and Power Management logic.
The SiS 620 Chip
The SiS620 integrates the host bus interface, the DRAM controller, the
IDE controller, the PCI interface, 2D/3D Graphics accelerator and video
playback accelerator. The SiS 620 is contained in a Ball Grid Array
(BGA) package, giving a smaller footprint and higher reliability.
Features of the SiS 620 chip
PL Bus Interface The SiS 620 chip monitors each cycle that is initiated by the processor,
and forwards to the PCI bus those that are not targeted at the local
memory. It translates PL (Processor Local) bus cycles into PCI bus
cycles.
The chip can support one Celeron processor at a Front Side Bus clock
frequency of 66 MHz.
PCI Bus Interface ThePCIinterfaceis PCI2.2compliantandsupportsupto4PCImasters.
The built-in PCI arbiter uses a rotating priority arbitration scheme with
guaranteed minimum access timefor PCI masters, providing fair access
and low latency for each PCI master.

Core Components and Technologies
Chip Sets
18
DRAM (Main Memory)
Controller The DRAM controller supports two DIMM slots. The maximum system
memory size supported is 512MB. The memory clock frequency can be
operated at up to 100MHz and can be in synchronous or asynchronous
modes with respect to host bus frequency. The host/DRAM clock
scheme is 66/66MHz.
IDE Controller The PCI master/slave IDE controller supports four devices, two on each
of two channels.
Read/Write Buffers The SiS 620 chip defines a data buffering scheme to support the
requiredlevelof concurrentoperationsandprovideadequate sustained
bandwidth between the DRAM subsystem and all other system
interfaces (Host, AGP and PCI).
System Clocking The SiS 620 chip operates the host interface at 66 MHz, the
SDRAM/core at 66 MHz, PCI at 33 MHz and AGP at 66 MHz. Coupling
between all interfaces and internal logic is done in a synchronous
manner.Theclockingschemeusesanexternalclocksynthesizer(which
produces reference clocks for the host and PCI interfaces).
The SiS 5595 PCI/ISA Bridge Chip
The SiS 5595 chip is a multi-function PCI device implementing a PCI-
to-ISA bridge function, a PCI IDE function, a Universal Bus host/hub
function, and an Enhanced Power Management function.
The following figure shows an example of the system block diagram
using the SiS 5595 chip.

19
Core Components and Technologies
Chip Sets
SiS 5595 PCI-ISA Bridge Chip Block Diagram
Processor
Host Bridge
& super AGP
(SiS620)
Main Memory
SDRAM
PCI/ISA Bridge
(SiS5595)
PCI Bus (3.3V or 5V, 33 MHz)
ISA/EIO Bus (5V)
BIOS
SP,PP,
FDC
KBD
Mouse
PCI Slots
Host Bus
USB1
USB2
GP[I,O] (30+)
SM Bus
Hard Disk
CD-ROM
BMIIDEUltra
DMA/33
Second Level
Cache
Memory Bus
DVD/Zip
Hard Disk

Core Components and Technologies
Chip Sets
20
Features of the SiS 5595 Chip
PCI Bus Interface This part of the chip is responsible for transferring data between the
PCI bus and the ISA expansion bus. It performs PCI-to-ISA, andISA-to-
PCI bus cycle translation. It supports the Plug-and-Play mechanism.
Data buffers are provided to isolate the PCI and ISA buses.
ISA Bus Interface As well as accepting cycles from the PCI bus interface, and translating
them for the ISA bus, the ISA bus interface also requests the PCI
master bridge to generate PCI cycles on behalf of a DMA or ISA master.
The ISA bus interface contains a standard ISA bus controller and data
buffering logic. It can directly support six ISA slots without external
data or address buffering.
SMBus Controller The System Management (SM) bus is a two-wire serial bus provided by
the SiS 5595 controller. It runs at a maximum of 16 kHz. The bus
monitorssomeofthehardwarefunctionsofthemainboard,bothduring
boot-up and run-time. All access to the SM bus is handled by the main
processor, via the SiS 5595 SM bus registers.
USB Controller The PCI USB (Universal Serial Bus) controller, supports two stacked
USB connectors on the back panel. These ports are built into the
SiS5595 controller as standard USB ports.
Ultra DMA Controller ThesevenchannelDMAcontrollerincorporatesthefunctionalityoftwo
82C37DMAcontrollers.Channels0to3arefor8-bitDMAdevices,while
channels5to 7are for16-bitdevices.The channels can beprogrammed
for any of the four transfer modes: the three active modes (single,
demand and block), can perform three different types of transfer: read,
write and verify. The address generation circuitry supports 24-bit
addresses for DMA devices.
Interrupt Controller The interrupt controller incorporates the functionality of two 82C59
interrupt controllers. The two controllers are cascaded, supporting 15
interrupts (edge/level triggered).