HP Vectra XU5 User manual

Vectra XU Technical Reference Introduction •• 1
Vectra XU Hardware and BIOS Technical Reference
Manual
Trademarks
Printed Manual Information
Introduction
Preface
Conventions
Ordering Information for the Phoenix BIOS Manual
Bibliography
System Overview
Introduction
PCI Local Bus Architecture
System Block Diagram
Principal Components and Features
System Board
Processor
Superscalar Architecture
Floating Point Unit (FPU)
Dynamic Branch Prediction
Instruction and Data Cache
Data Integrity
PCI Chip Set
PCI, Cache, and Memory Controller (PCMC)
Local Bus Accelerator (LBX)
The PCI/ISA Bridge (PCEB and ESC)
Super I/O Chip Set
Flexible Drive Controller (FDC)
Serial/Parallel Ports
Graphics/Integrated Video
Video Controller
Video Clock Generator
Video Resolutions Supported
PCI LAN/SCSI-2 Controller
IDE to PCI Controller
Flash ROM
Security Features
System Specifications
Physical Characteristics
Electrical Specifications
Environmental Specifications
Summary of the HP BIOS
Overview
Overview of Address Space
I/O Addresses Used by the System
System Memory Map

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Product Identification
Machine Capability and Extension of Capability Markers
BIOS Version Number
Year of the ROM BIOS Release
Week of the ROM BIOS Release
HP BIOS I/O Port Map
Addressing System Board Components
Interrupt Controllers
PCI Interrupt Request Lines
The Integrated Ultra VGA Controller
Overview
Video Memory
Video Modes
Energy Saving Screen Blanking
Supported Enhanced Video Modes
VESA Connector
Power-On Self Tests
Overview
Power-On Self Test (POST)
Shadow RAM
Error Codes

Vectra XU Technical Reference Introduction •• 3
Trademarks
Centronics® is a registered trademark of Centronics
Data Computer Corporation.
Microsoft® and MS-DOS® are U.S. registered trademarks
of Microsoft Corporation.
LANManager, Microsoft Windows and OS/2 are products
of Microsoft Corporation.
Novell® and NetWare® are U.S. registered trademarks
of Novell, Inc.
Pentium™ is a trademark of Intel Corporation.

Vectra XU Technical Reference Introduction •• 4
Printed Manual Information
Printed in France, April 1995
HP Part Number D3080-90911, Edition 2

Vectra XU Technical Reference Introduction •• 5
Introduction

Vectra XU Technical Reference Introduction •• 6
Preface
This manual is a technical reference and BIOS document for engineers and technicians who
provide system level support, or who are engaged in the design of system-compatible
products. It is assumed that the reader possesses a fairly detailed understanding of AT-
compatible microprocessor functions and digital addressing techniques.
Technical information that is readily available from other sources, such as manufacturer's
proprietary publications, has not been reproduced.
For additional reference material, refer to the bibliography.
This manual contains summary BIOS information only. For detailed information, we
recommend the reference work cited in the next section.

Vectra XU Technical Reference Introduction •• 7
Conventions
The following conventions are used throughout this manual to identify specific elements:
•Hexadecimal numbers are identified by a lower case h.
For example, 0FFFFFFFh or 32F5h
•Binary numbers and binary bit patterns are identified by a lower case b.
For example, 11101b or 1001011b

Vectra XU Technical Reference Introduction •• 8
Ordering Information for the Phoenix BIOS Manual
System BIOS for IBM PCs, Compatibles, and EISA Computers (ISBN 0-201-57760-7) by
Phoenix Technologies is available in many bookstores. It can also be ordered directly from
the publisher as follows:
In the U.S.A.
Call Addison-Wesley in Massachusetts at [phone], and be prepared to give a
credit card number and expiry date.
In Europe
Send a request to:
Addison-Wesley
Concertgebouwplein 25
1071 LM Amsterdam, The Netherlands
Tel.: [phone]
Fax: [phone]

Vectra XU Technical Reference Introduction •• 9
Bibliography
•Vision864 GUI Accelerator© S3 Incorporated, 2770 San Tomas Expressway, Santa
Clara, CA 95051-0981
•Am79C960 PCnet-ISA, Single-Chip Ethernet Controller for ISA™ Advanced Micro
Devices, Incorporated
•System BIOS for IBM PCs, Compatibles, and EISA Computers (ISBN 0-201-57760-7)
by Phoenix Technologies. Addison-Wesley (publisher)
The following Hewlett Packard publications may also assist the reader of this manual.
•HP Vectra XU PC Setting Up Your PC and Getting Started manuals
(D3080B xxxxx, where xxxxx is the language option)
•HP Vectra XU PC Familiarization Guide (D308xA+49A+90001)
•HP Vectra PC Service Handbook (5963-6104)
The following Intel® publications provide more detailed information:
•PENTIUM Processor (241595-1)
•82430 PCIset for the PENTIUM Processor (290481-001)
•82424TX Cache and DRAM Controller (290471-001)
•82423TX Data Path Unit (290472-001)
•823781B System I/O (290473-001)

Vectra XU Technical Reference System Overview •• 10
System Overview

Vectra XU Technical Reference System Overview •• 11
Introduction
This chapter provides a description of the HP Vectra XU PC Series, and includes detailed
system specifications.

Vectra XU Technical Reference System Overview •• 12
PCI Local Bus Architecture
This HP Vectra PC uses the PCI local bus architecture. The PCI (Peripheral Component
Interconnect) architecture lets system devices operate at speeds approaching that of the
processor and removes the data transfer bottleneck imposed by the ISA, EISA, and MCA
buses.
This performance improvement is of particular value to graphics accelerators, disk
controllers, and network adapters which need to transfer large blocks of data very quickly.
The principal features of the PCI bus are:
•Processor independence
•Support for up to 21 physical PCI device packages (each device package may contain
up to 8 PCI devices, which enables support for up to 168 PCI devices)
•132 MByte per second peak transfer rate for both read and write transfers
•PCI bus speed of up to 33 MHz.
NOTE The PCI bus specification was developed by Intel Corporation. For information
regarding the specification, contact: PCI Special Interest Group c/o Intel
Corporation, 5200 NE Elam Young Parkway, HF3-15A Hillsboro, OR 97124, U.S.A.

Vectra XU Technical Reference System Overview •• 13
System Block Diagram

Vectra XU Technical Reference System Overview •• 14
Principal Components and Features
The HP Vectra XU PC is an ISA/PCI-based PC and features the Pentium&TM;
microprocessor and the 82430 chip set.

Vectra XU Technical Reference System Overview •• 15
System Board
Main Memory
Module sockets
Level-two
cache memory
Main processor
socket
Dual Processor
socket
PCI accessory board slot
Combination PCI or ISA slot ISA accessory
board slots
The main features of the system board are:
•a Pentium 75, 90 or 100 MHz microprocessor
•a socket for a dual companion processor
•a PCI bus video controller:
◊◊ the HP Vectra XU 5/75 and XU 5/90 has an integrated Ultra VGA+ video controller
on the PCI bus with 2 MB of video memory (for 1280 x 1024 resolution in 256 colors)
◊◊ the HP Vectra XU 5/90C and XU 5/100C do not have an integrated video controller.
They are supplied with a pre-installed Matrox MGA PCI/2+ video board or a Matrox
Impression Plus video board. Both Matrox video boards have 2 MB of video memory
(for 1600 x 1200 resolution in 256 colors). The video boards can be upgraded to 4
MB (for 1600 x 1200 in 64K colors).
•a combined LAN/SCSI controller on the PCI bus
•an Enhanced IDE controller on the PCI bus, with one IDE device connector
•an integrated flexible disk controller for two flexible disk drives
•eight sockets for DRAM main memory modules--allowing installation of up to 256 MB
•a system ROM (using flash ROM technology) that can be easily updated using an
HPROMInit, containing:
◊◊ the BIOS
◊◊ a power-on hardware test that allows you to view the results of the diagnostics as
well as a corrective action message
◊◊ SETUP in local language with context-sensitive help
◊◊ LAN boot code (to start the PC from a LAN server) for use with Ethernet LAN
adapters and either a Novell Netware or LAN Manager server

Vectra XU Technical Reference System Overview •• 16
•a keyboard/mouse controller and interface
•one serial connector and one parallel connector--for attaching peripherals
•an integrated 16-bit Ethernet interface, configurable from SETUP
•a system board mounted LAN connector (UTP) and link beat LED
•a system board mounted Coax LAN connector

Vectra XU Technical Reference System Overview •• 17
Processor
The Pentium processor uses 64-bit architecture and is 100% compatible with Intel's family of
x86 microprocessors. All application software that has been written for Intel 386 and
Intel 486 microprocessors can run on the Pentium without any modification. It contains all
the features of the Intel 486 microprocessor, with the following features added to enhance
performance:
•Superscaler Architecture
•Floating Point Unit
•Dynamic Branch Prediction
•Instruction and Data cache
•Data Integrity
•Supports MultiProcessor Specification (MPS) 1.1
•PCI Bus Architecture.
The microprocessor is seated in a Zero Insertion Force (ZIF) socket.

Vectra XU Technical Reference System Overview •• 18
Superscalar Architecture
The Pentium processor's superscaler architecture has two instruction pipelines and a
floating-point unit, each capable of independent operation. The two pipelines let the Pentium
execute two integer instructions, in parallel, in a single clock cycle. Using the pipelines
halves the instruction execution time and almost doubles the performance of the processor,
compared to an Intel486 microprocessor of the same frequency.
Frequently, the processor can issue two instructions at once (one instruction to each
pipeline). This is called instruction pairing. Each instruction must be simple. One pipeline will
always receive the next sequential instruction of that issued to the other pipeline.

Vectra XU Technical Reference System Overview •• 19
Floating Point Unit (FPU)
The Floating Point Unit incorporates optimized algorithms and dedicated hardware for
multiply, divide, and add functions. This increases the processing speed of common
operations by a factor of three.

Vectra XU Technical Reference System Overview •• 20
Dynamic Branch Prediction
The Pentium processor uses dynamic branch prediction. To dynamically predict instruction
branches, the processor uses two prefetch buffers. One buffer is used to prefetch code in a
linear way and one to prefetch code depending upon the contents of the Branch Target
Buffer (BTB). The BTB is a small cache that keeps a record of the last instruction and
address used. It uses this information to predict the way that the instruction will branch, the
next time it is used. When it has made a correct prediction the branch is executed without
delay, enhancing performance.