Icom IC-725 User manual

HF ALL BAND TRANSCEIVER
IC-725
lcom Inc.

INTRODUCTION
This service manual describes the latest service informa-
tion for the IC-725 HF ALL BAND
TRANSCEIVER at the
time of going to press.
If you require assistance or further information regarding
the operation
and capabilities of the IC-725, contact your
nearest authorized lcom Dealer or lcom Service Center.
ORDERING PARTS
Be sure to include the following four points when
ordering replacement parts:
1. 10-digit order numbers
2. Component part number and name
3. Equipment model name and unit name
4. Quantity required
<SAMPLE ORDER>
1110001310 IC µPC577HA IC-725 MAIN UNIT 5pieces
8810005510 Screw PHM3x6ZKBS IC-725 Topcover 10pieces
Addresses are provided on the inside back cover for your
convenience.
DANGER
NEVER connect the transceiver to an AC outlet or
to a
DC power supply that uses more than 16 V. This
will ruin the transceiver.
DO NOT expose the transceiver to rain, snow or
any liquids.
DO NOT reverse the polarities of the power supply
when connecting the transceiver.
DO NOT apply an RF signal of more than 20 dBm
(100 mW) to the antenna connector. This could
damage the transceiver's front end.
REPAIR NOTE
1. Make sure a problem is internal before disassembling
the transceiver.
2. DO NOT open the transceiver until the transceiver
is disconnected from a power source.
3. DO NOT force any of the variable components. Turn
them slowly and smoothly.
4. DO NOT short any circuits or electronic parts.
An insulated tuning tool MUST be used for all
adjustments.
5. DO NOT keep power ON tor a long time when the
transceiver
is defective.
6. DO NOT tr~nsmit power into a signal generator
or a sweep generator.
7 ALWAYS connect a
40 dB-50 dB attenuator between
the transceiver
and a deviation meter or spectrum
analyzer when using such test equipment.
8. READ the instructions of test equipment thoroughly
before connecting equipment to the transceiver.

TABLE OF CONTENTS
SECTION 1 SPECIFICATIONS.................................................... 1 -1
SECTION 2 INSIDE VIEWS. ... ..... . .. . ... . .. .. . .. . .. .... .... . .... ... . .. .. .. ...... 2 - 1 -·2
SECTION 3 BLOCK DIAGRAM .. .. .. .. . .. .. .. .. .. . .. .... ... ... .... .. .. .. . ... ...... 3 - 1
SECTION 4 CIRCUIT DESCRIPTION............................................... 4-1 -7
4 • 1 RECEIVER CIRCUITS . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .. . . . 4- 1
4 · 2
TRANSMITTER CIRCUITS. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .. . . . . . . 4 - 4
4 • 3
PLL CIRCUITS............................................................. 4-6
4 · 4 LOGIC CIRCUITS. . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .. . . . . 4 - 7
4 • 5
REGULATOR CIRCUITS . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . 4 - 7
SECTION 5 MECHANICAL PARTS AND DISASSEMBLY.................. .. ... ... .. 5 -1 ....., 7
5 · 1 FRAME DISASSEMBLY ................................. : . . . . . . . . . . .. . . . . . . . 5- 1
5 · 2
PA UNIT AND ACCESSORIES . . . . . . . . . . . . . . . . .. . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . 5- 3
5 • 3
FRONT AND PLL UNITS CONNECTOR ASSEMBLY. . . . .. . . . . . . . . . . . . . . . . . .. .. . . . . 5 - 5
5 •4
FRONT AND MAIN UNITS CONNECTOR ASSEMBLY . . . . .. . . . . . . . . . . . . . . . .. . . . . . . 5 - 6
5 • 5
PA AND FIL TEA UNITS CONNECTOR ASSEMBLY. . . . .. . . . . . . . . . . . . . . . . . .. . . . . . . . 5- 7
SECTION 6 ADJUSTMENT PROCEDURES. . .. .. . .. .. ... .... .. ..... ... . .. .. .. ...... 6 - 1-7
6·1 PREPARATION BEFORE SERVICING;.......................................... 6-1
6 • 2 PLL ADJUSTMENT . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .. . . . . . . . . 6 _.: 2
6 · 3
RECEIVER ADJUSTMENT. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . . . . .. . . . 6 - 4
6 •4
TRANSMITTER ADJUSTMENT . .. . . . . . . . . . . . . .. . . .. . . . . . . . .. . . . . . . . . . . . . . . . . . . . 6 - 6
SECTION 7 BOARD LAYOUTS .. .. .. . .. ... .. .. .. . .. ..... ... ... ..... .. .. .. .. ... .. .. 7 - 1 ,...., 5
7 · 1 FRONT UNIT . . .. . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . 7- 1
7 · 2 MAIN UNIT ....................................... · . . .. . . . . . . . . . . . . . . .. . . . . 7- 2
7 -3
PLL UNIT. . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . . . . . . .. . . . . . . 7 - 3
7 · 4
PA UNIT. . . .. . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . 7 - 4
7 •5
DDS UNIT .............................................................. ; . 7 - 5
7 · 6
AM • FM UNIT (OPTIONAL) . . . . . . . . . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . . . . . . .. . . . . . 7 - 5.
SECTION 8 PARTS LIST .......................................................... 8-1-13
SECTION 9 VOLTAGEDIAGRAMS ................................................ 9-1-2
9 • 1 FRONT AND MAIN UNITS . . . . . . . . . . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . 9 - 1
9 • 2
PLL AND PA UNITS . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . . .. . . . . 9 - 2

SECTION 1 SPECIFICATIONS
•GENERAL
• Frequency coverage
•Modes
• Number of memory channels
• Antenna impedance
• Usable temperature range
• Frequency stability
• Power supply requirement
• Current drain (at 13.8 V DC)
• Dimensions
•Weight
•TRANSMITTER
• Output power
• Spurious emissions
• Carrier suppression
• Unwanted sideband
•Microphone impedance
•RECEIVER
• Receive system
• Intermediate frequencies
• Sensitivity (preamplifier ON)
• FM squelch sensitivity
• Selectivity
• Spurious response rejection
• Audio output impedance
• Audio output power
• RIT variable range
Receive 500
kHz-30 MHz
Transmit 160-m band
1.8- 2.0 MHz
80-m band 3.5- 4.0 MHz
40-m band 7.0- 7.3 MHz
30-m band 10.1-10.15 MHz
20-m band 14.0-14.35 MHz
SSB (A3J), CW (A 1 ), AM (A3), FM (F3)
17-m band 18.068-18.168 MHz
15-m band 21.0 -21.45 MHz
12-m band 24.89 -24.99 MHz
10-m band 28.0 -29.7 MHz
(Ul-7 AM · FM UNIT is required for AM transmit and FM transmit/receive.)
26
50 a unbalanced
-10 °C-+60 °C (+14 °F-+140 °F)
Less than ±200 Hz up to one hour after power is turned ON.
Less than ±30 Hz after one hour at +25 °C (+ 77 °F).
Less than ±350 Hz at 0 °C-+50 °C (+32 °F-+122 °F).
13.8 V DC ±15 %, negative ground
Receive squelched 1.2 A max. audio output 1.5 A
Transmit
20 A
241
(W) x
94
(H) x 239 (D) mm (Projections not included)
9.5 (W) x 3.7 (H) x 9.4 (D) in
4.6 kg (10.1 lb)
SSB, CW, FM 10-100 W continuously adjustable
AM 10-40 W continuously adjustable
More than 50 dB below peak output power
More than
40 dB below peak output power
More than
50 dB down with 1 kHz AF input
6000
SSB, CW, AM Double-conversion superheterodyne
FM
1st SSB
Triple-conversion superheterodyne
70.4515 MHz
cw 70.4506 MHz
AM, FM 70.4500 MHz
2nd
SSB 9.0115 MHz
CW 9.0106 MHz
AM, FM 9.0100 MHz
3rd
FM 455 kHz
SSB, CW (10 dB S/N) 1.8-30 MHz Less than 0.15 µV (-123 dBm)
AM (10 dB SIN) 0.5-1.8 MHz Less than 13.0 µV (-85 dBm)
1.8-30 MHz Less than 2.0 µV (-101 dBm)
FM (12 dB SINAD)
28-30 MHz Less than 0.5 µV (-113 dBm)
Less than 0.3 µV (preamplifier ON)
SSB, CW More than 2.3 kHz/-6 dB
AM More than 6.0 kHz/-6 dB
FM More than 15 kHz/-6 dB
More than
70 dB
an
Less than 4.0 kHz/-60 dB
Less than 20.0 kHz/-40 dB
Less than 30 kHz/-50 dB
More than
2.6 W at 1o% distortion with an 8 a load
More than ± 1 kHz
All stated specifications are subject to change without notice or obligation.
1-1

SECTION 2 INSIDE VIEWS
• PLL UNIT
A/D converter------
(IC12: MB4052M-G)
Cl-V interface-------=
Cl-V diode matrix-----
CPU (IC8: HD63A01YOG83P)
Lithium backup battery---
+5 V regulator-------=
(IC10: TA78005AP)
Sensor
circuit------
Band voltage buffer----....;:;;,:..,.,.-""""
(IC9: M54562P)
•MAIN UNIT
Rx bandpass filters ------=-
Rx 1st mixer circuit-----+
Tx 2nd mixer circuit---_...
MCF (Fl1: FL-71)-----,
Noise blanker circuit-----
Rx 2nd/Tx 1st mixer----:
(IC1: ND487C1-3R)
MCF (Fl2:
FL-23)----~====!-i..--I
9 MHz SSB • CW filter
(Fl3: FL-30)
2-1
-----1st LO amp circuit
Phase detector/Prescaler
------Sub loop VCO
c---------DDS UNIT
-:::-------2nd LO circuit
'---------=;----Reference crystal
(X2: CR-21 30.72 MHz)
Divider (IC15: M74ALS74AP)
Space for Ul-7 AM • FM UNIT
+------APC/ALC circuit
'+-------- BFO circuit
;.;------SSB modulator
(IC6: µPC1037HA)
~----Product detector
(IC5: µPC1037HA)
----Rx 2nd IF amplifier
.------9.01 MHz AM filter
(Fl4: FL-116)

• PA AND FILTER UNITS
Tx/Rx switching relay-----;;.-=:-;;-
(RL13: DS1-M-DC12V)
--------Predrive amplifier
(01: 2SC1971)
~----Drive amplifier
(02, 03: 2SC3133)
'=+----Final amplifier
(05, 06: 2SC2904)
-'------Thermal switch
(81: OHD-3 90M)
2-2

c.>
I
....
a:~Tr~N 1 .-1 , • ,,. <
022
2SK241
I 14 I~ ~I
+•
TB
••·••)b ~
SW -+~
DELAY
..
MAIN UNIT
!lb 2nd mlur.1
Tx !ti mixer
TXC
"" ~I '.
RF POWl!:R
CTRL
13.BV
o----<--------- 13.81/
0.151"\..1,IMHz
ATT SW
T1 2nd mlur
PA UNIT
~
"~8MH;
~
,, ..,----L:..:._jJ 3.5MH~
~
., ....------L::._jj- --7.0MH;
07.8
IK&OX2
ANT
--------------~~;~
015, 17, ,., 21 -r::;;l I
~-1·--·- --- -
VCOI • 70.H15"'- 71.4514MH1
VC02 '78.4&15"" 85.4&f4MHz
VC03 '85.4514.,,. 92.4514MHr
VC04 '92.40115" 100.451!5MHz
PLL UNIT
IC17
pPCI037H
2SK112A )f4 PA LPF BUFF
Lt ... LI I
I
01
MVO
Q4
2801406
D2,3
MV5X2
', QT 2SBOl2
I
··~ 0
~
L---------
•••
DATA
CPU
tea
HD83AOIY
IC12 M84052
MAIN
DUL
RIT
I- s & • VFO. MHr •IC.
DISPLAY
D~
IC4 pPD4069
IC6
BA222
~
-151/ 13.81/
v

SECTION 4 CIRCUIT DESCRIPTION
4·1 RECEIVER CIRCUITS
4-1·1 RF SWITCHING CIRCUIT
(PA AND MAIN UNITS)
RF signals from the antenna connector pass through the
transmit/receive switching relay
(RL13) and a low-pass
filter,
and are applied to the MAIN UNIT via P2 (MAIN
UNIT:
J12).
The signals from the PA UNIT either bypass or are
attenuated at
20 dB attenuator (R102, R103, RL1). There
are no non-linear components between the antenna
connector
and attenuator to prevent distortion caused
by strong signals. The signals are then applied to
RF
filters.
4·1·2 RF BANDPASS FILTER CIRCUIT
(MAIN UNIT)
The RF UNIT has 7 RF. bandpass filters (BPF) for signals
above 1.6
MHz and 1 low-pass filter (LPF) for signals below
1.6
MHz. The signals pass through one of the bandpass
or low-pass filters depending
on the receive frequency
range.
(1) 0.5-1.6 MHz
A diode
is not used at the low-pass filter entrance
removing diode distortion from very strong signals.
Signals bypass a preamplifier by the bypass switch (012).
(2) 1.6 MHz AND ABOVE
Signals are applied to a high-pass filter consisting of
L42,
L43, C143-C146. This filter suppresses strong signals
below 1.6
MHz such as a broadcasting station.
The filtered signals are applied to one of 7 bandpass filters
depending
on the frequency of the signals and then to the
preamplifier circuit (08, 09).
(3) FILTER SWITCHING CIRCUIT
An RF bandpass filter is selected with BPF switching
voltage (BO-B7) from the
CPU via IC16 current amplifier.
The switching voltage of the BPF entrance is higher than
the
BPF exit to improve multi-signal and strong signal
characteristics.
4·1·3 PREAMPLIFIER CIRCUIT (MAIN UNIT)
The preamplifier circuit uses low-noise junction FETs
(2SK125 x 2) to provide 1O dB gain over a wideband
frequency
range.
When the [PRE] switch is turned ON, the signals from
the
RF filter are amplified by the preamplifier circuit (08,
09).
When the [PRE] switch is turned OFF, the signals
bypass the preamplifier through 030
and 032. When the
operating frequency is below
1.6 MHz, 012 turns ON and
the signals bypass the preamplifier regardless of the
[PRE] switch.
4-1
Amplified or bypassed signals are applied to the 1st mixer
circuit via the low-pass filter. The low-pass filter cuts
off at
35 MHz to suppress image frequency at the 1st
mixer circuit (013, 014).
PREAMP CIRCUIT
RF signal
from BPF
030
Q10
Fig.1
4·1·4 1ST MIXER CIRCUITS (MAIN UNIT)
The signals from the low-pass filter enter the 1st mixer
circuit (013, 014) to
be converted to a 70.45 MHz tst IF
signal.
EXACTNESS 1ST IF FREQUENCY
MODE
FREQUENCY (MHz)
SSB
70.4515
cw
70.4506
AM, FM
70.4500
The 1st mixer circuit employs a balanced mixer using
low-
noise junction FETs (2SK125 x 2) to expand the dynamic
range.
The 1st LO signal (70.9515-100.4515 MHz) enters the
MAIN UNIT from the PLL UNIT via J5. The signal is
amplified at 04, filtered by a low-pass filter, and then
applied to the 1st mixer circuit (013, 014). The low-pass
filteremploys a ring core inductortoprevent 1st LO leakage
signals.
The output level from 04 is approx. 25 dBm.
The 1st IF signal is applied to
an MCF (Monolithic Crystal
Filter;
Fl 1) to suppress out-of-band signals. The signal is
amplified at the 1st IF amplifier (015), and then applied
to the 2nd mixer
(IC1).

4·1·5 IF CIRCUITS (MAIN UNIT)
The 1st IF signal from 015 is converted to a 9 MHz 2nd
IF signal at the 2nd mixer (IC1). IC1 is a DBM (Double
Balanced Mixer).
EXACTNESS 2ND IF FREQUENCY
MODE FREQUENCY (MHz)
SSB 9.0115
cw 9.0106
AM, FM
9.0100
The 2nd LO signal (61.44 MHz) from the PLL UNIT via J4
is applied to the 2nd mixer. The converted 2nd IF signal
passes through D4 (D35 for transmitting) and is applied
to the
MCF (Fl2) to suppress unwanted signals.
The signal output from Fl2 passes through the noise
blanker gate
(D5-D8) and is amplified at the 2nd IF am-
plifier (021). The signal enters one of the three 9 MHz
filters (Fl3, Fl4, optional
CW narrow filter) or optional AM
· FM UNIT via D52. The filters are selected with mode
selecting signals (SSB ·CW, AM, CW-N) and the "TB"
voltage line.
The signal from a 9 MHz filter is amplified at the 2nd IF
amplifiers (027-029) and applied to the demodulator
circuit.
Dual-gate
FETs are used on the 1st and 2nd IF amplifiers
(015, 021, 027). The 2nd gates of 015, 021 and 027 are
controlled by
AGC bias voltage. A rapid time constant
is used for 027 to prevent raising the edge distortion of
receive signals.
R140, connected to the gate of 028, improves the
temperature characteristics of the receiver gain.
R138
adjusts the receiver gain.
IF CIRCUIT
AF signal SQL
IC8
BFO
SSB DET
AM OET
062
4·1·6 NOISE BLANKER CIRCUITS
(MAIN UNIT)
The IC-725 uses a noise trigger noise blanker circuit that
cuts out pulse-type noise signals at the noise blanker gate
(D5-D8).
A portion of the signals from Fl2 is amplified at the noise
amplifiers (016,
IC2) and detected at the noise detector
(D12,
D13). The detected voltage from the noise detector
is applied to the noise blanker switch (019).
The threshold level of the noise blanker switch
is set at
0.9 V. When the detected voltage exceeds the threshold
level, 020 outputs a blanking signal to activate the noise
blanker gate
(05-08).
A portion of the detected voltage is applied to the noise
AGC circuit (018) and fed back to the noise amplifier (IC2)
as noise AGC voltages. The time constant of the noise
AGC circuit is determined by R43, R47 and C60. This
AGC circuit does not operate to detect pulse-type noise.
When the operating frequency or mode is changed, the
"ONB" signal line becomes "LOW," turning 020 ON. The
noise blanker gate prevents PLL click noise.
4·1·7 BFO CIRCUIT (MAIN UNln
A 9 MHz signal oscillated at the BFO circuit (031, X1)
is buffer-amplified at 042 and used at the balanced
modulator
(IC6) and a product detector (IC5). The BFO
frequency is shifted with a mode signal using 067-069.
In USB mode, the "USB" signal line becomes "HIGH,"
turning ON 069. The frequency is then adjusted with
C294 to set the
USB carrier point.
At
CW mode transmitting, the "CW" signal line becomes
"HIGH" and 033 becomes OFF, turning ON 068. The
frequency is then adjusted with L83 to set the CW
transmit carrier point.
In LSB mode, the "LSB" signal line becomes "HIGH,"
turning ON 067. The frequency is then adjusted with
L82 to set the
LSB carrier point.
NOISE
BLANKER
Fig. 2
059, 060
4-2

BFO FREQUENCY IN EACH MODE
MODE
FREQUENCY (MHz)
USB
9.0130
CW (Tx)
9.0106
LSB
9.0100
CW (Rx)
9.0098
AM
NO OUTPUT
4·1·8 DEMODULATOR CIRCUITS
(MAIN UNIT)
The IC- 725 has 2 detector circuits, a product detector and
a diode detector to demodulate the SSB, CW signal and
AM signal respectively.
In SSB or CW mode, the 2nd IF signal from the IF amplifier
(029) is mixed with the BFO signal at the product detector
(IC5) to demodulate the 2nd IF signal into an AF signal.
The detected signal passes through the AF input mode
selector switch
(IC8).
In AM mode, the 2nd IF signal from 029 passed through
C121 is detected at D62 and passes through the AF input
mode selector switch (IC8).
4-1·9 AF INPUT MODE SELECTOR SWITCH
(MAIN UNIT)
The AF signal from a detector circuit or the optional AM
· FM UNIT is applied to the AF input mode selector switch
(IC8). IC8 consists of 4 analog switches and they are
selected with a mode signal from IC15 and the squelch
control signal. The AF signal
is applied to the AF amp
circuit.
IC8 AF INPUT MODE SELECTOR SWITCH
MODE
ACTIVATING
CONTROL
PIN NUMBERS
PIN NUMBER
USB, CW 2-1 13
AM 3-4
5
FM 10-11 12
ANY MODES
9-8 6
(for S-meter)
AGC, S-METER AND SQUELCH CIRCUIT
Squelch signal
av
S.meter
signal FM S·meter
signal
SQLS
to [RX)
indicator
Fig. 3
4-3
4·1·10 AF AMP CIRCUIT (MAIN UNIT)
The AF signal from the AF input mode selector switch is
applied to the AF preamplifier (035, 036). The CW
sidetone signal is applied to 036.
The output from the AF preamplifier is applied to the [AF]
control
(FRONT UNIT, R1 b) and the 2.8 kHz cut-off active
low-pass filter (037). The
AF signal is power-amplified at
IC9 to drive the speaker.
4·1·11 AGC AND S·METER CIRCUIT
(MAIN UNIT)
The receiver gain is determined by the voltage on the AGC
line (030, collector). When strong signals are received,
the
AGC circuit decreases the voltage on this line.
The IF signal from the IF amplifier (029) passes through
C117, is detected at D59 and 060, and applied to the base
of 030. A time constant
(C113, R120) is connected to
the AGC line that determines the AGC release time.
The time constant is controlled by the [AGC] switch. When
the [AGC] switch is pushed OUT, C112 and R119 are
connected
in parallel with the AGC line to obtain a slow
AGC release time.
The AGC bias voltage is applied to the differential amplifier
(IC4, pin 6) where the difference between the bias and
reference voltages is detected. The resulting S-meter
signal passes through the meter switching circuit
(IC8)
and is then applied to the meter on the front panel. The
reference voltage is adjusted with R116. IC8 pins 8 and
9 are connected inside the IC in receiving.
The FM S-meter signal from the optional AM · FM UNIT is
applied to the meter switching circuit (IC8) via 057. The
signal is also applied to the squelch circuit (IC4 pin 2).

4·1·12 SQUELCH CIRCUIT (MAIN UNIT)
The squelch circuit mutes the audio output when the S-
meter signal is lower than the [SOL] control setting level.
The S-meter signal from IC4 pin 7 is applied to the
comparator
(IC4 pin 2) to be compared to a threshold
level controlled by the
[SOL] control. The squelch control
signal is applied to control terminals of the
AF input mode
selector switch (IC8).
When the S-meter signal is lower than the threshold level,
the comparator turns "HIGH" and then
032 turns OFF to
deactivate the
AF input mode selector switch. This
signal is applied to 034, turning OFF the [RX] indicator
and is also applied to the [MIC] connector pin 4.
4·2 TRANSMITTER CIRCUITS
4-2·1 MIC AMPLIFIER (MAIN UNln
Audio signals from the [MIC] connector are applied to the
[MIC] control and amplified at the mic amplifier (045).
External modulation input from the [ACC(1)] socket pin 4
is also applied to 045 via R255.
The AF signals from 045 or CW keying signal is applied
to the balanced modulator
(IC6). 044 cuts the signals
from
045 in CW or receiving.
4-2·2 BALANCED MODULATOR (MAIN UNln
Output signals from the mic amplifier or CW keying signal
are applied to the balanced modulator circuit
(IC6) to be
converted to a 9
MHz IF signal using a BFO signal. The
BFO signal, buffer-amplified at 042, is applied to IC6 pin 7
as a carrier signal. IC6 outputs a double sideband signal
and passes through a 9
MHz filter to create an SSB
signal.
R177 and R179 adjust the balance level of IC6 for
maximum carrier suppression.
In CW mode, the CW
keying signal upsets the balance to create a carrier signal.
4·2·3 IF CIRCUITS (MAIN UNln
The 9 MHz IF signal passes through one of the three
9 MHz filters where unwanted sideband or out-of-band
signals are removed.
The filters are selected with mode
selecting signals
and the "T8" voltage line. The optional
CW narrow filter is not used in transmitting.
The resulting signal is amplified at 022, and is then mixed
with the 2nd
LO signal to be converted to a 70.45 MHz IF
signal at IC1. IC1 is used in receiving and transmitting.
The FM signal from the optional AM · FM UNIT is amplified
at
022 and is then applied to IC1.
The 70.45 MHz IF signal is amplified at the IF amplifier
(07) and is then converted to the displayed frequency at
the balanced mixer (02, 03).
4-4
The gates of the IF amplifiers (07, 022) are controlled
by ALC bias voltage from the ALC circuit. R89, con-
nected to the gate of 022, improves the temperature
characteristics of the transmitter gain.
R85 adjusts the
transmitter gain.
4·2·4 RF CIRCUITS (MAIN AND PA UNITS)
The converted signal from 02 and 03 is applied to the
bandpass filter where the unwanted
LO signal emission is
reduced. The converted signal is amplified at 01. and
is then applied to the PA UNIT via J11.
Incoming signals from the MAIN UNIT are amplified at the
predrive amplifier (01), drive amplifier (02, 03) and power
amplifier (05, 06) to obtain stable 100 W
RF output
power. The predrive amplifier is a class A amplifier with a
Vee of 13.8 V. The drive and power amplifiers are class
AB push-pull amplifiers with a Vee of 13.8 V. A stable bias
voltage is applied to these amplifiers.
01 controls a bias
voltage to the drive amplifier. 04,
02 and 03 supply a
bias voltage to the power amplifier.
A 0.012 n resistor (R26), inserted in the 13.8 V Vee line, is
provided for the le APC circuit. A voltage generated at
both terminals of
R26 is applied to the MAIN UNIT via
the "ICH" and "ICL" signal line.
Thermal switch S1 and thermistor R32 detect the
temperature of
06 and 05 respectively, and control the
cooling fan speed.
TEMPERATURE °C (°F)
Below50 50-90
(122)
(122-194)
THERMAL SWITCH (S1) OFF OFF
RESISTANCE OF R32 HIGH LOW
COOLING
RECEIVE
STOP
LOW
FAN SPEED
TRANSMIT LOW
COOLING FAN CONTROL CIRCUIT
THERMAL SWITCH
S1
THERMISTOR
R32
Fig. 4
D6
Above90
(194)
ON
LOW
HIGH
HIGH
PATS
(8 Vin Tx)

4-2·5 RF FILTER CIRCUIT (PA UNIT)
The PA UNIT has 6 Chebyshev low-pass filters. The
signal from the power amplifier (05, 06), applied to one of
the low-pass filters depending
on the transmit frequency
range, suppresses high harmonic components.
The filter switching voltage, obtained at the
PLL UNIT, is
applied to the PA UNIT via P7.
FREQUENCIES AND APPROPRIATE FILTERS
FILTER
FREQUENCY RANGE (MHz)
L1
Below 2
L2
2-4
L3
4-8
L4
8-15
L5
15-22
L6
22-30
The filtered signal passes through the SWR detector
circuit (L51) and is then applied to the antenna connector.
The forward signal from
L51 is detected at D7 and applied
to the MAIN UNIT as the "FOR" voltage. The reflection
signal from
L51 is detected at DB and applied to the MAIN
UNIT as the "REF" voltage.
4·2·6 ALC CIRCUIT (MAIN UNIT)
The ALC (Auto Level Control) circuit stably controls the
RF output power using the [RF POWER] control.
The "FOR" voltage from the PA UNIT is applied to IC11
pin 2 and IC1 O pin 3. The "POC" voltage controlled
by the [RF PWR] control is also applied to IC11 pin 3 as
the reference voltage.
When the "FOR" voltage exceeds the "POC" voltage, ALC
bias voltage from IC11 pin 1 controls the IF amplifiers
to reduce the output power until the "FOR" and "POC"
voltages are equalized.
ALC CIRCUIT
REF
voltage
R203
S V from 041
MAIN UNIT
056
2SM
In AM mode, IC11 operates as an averaging ALC
amplifier, because a capacitor on the optional AM · FM
UNIT (C51) is connected to the cathode of D76. 054
turns ON and the "POC" voltage is shifted for 40 W AM
output power (maximum).
The.
ALC bias voltage from IC11 pin 1 is also applied to
the inversion-amplifier
(IC11 pin 6) to control an intensity
of the [TX] indicator, showing the ALC level.
An external ALC input from the [ALC] jack is applied to
the buffer amplifier (053).
ALC operation is identical to
that of the internal
ALC.
4·2·7 APC CIRCUITS (MAIN UNIT)
The APC circuits protect the final transistors from high
SWR and excessive current. The "REF" voltage from
the
PA UNIT is applied to 056. When the "REF" voltage
exceeds the reference voltage, determined by R203 and
R204, 056 turns ON and the "POC" voltage is shifted
for
12 W output power.
The "ICH" and "ICL" voltages are applied to the le APC
amplifier (IC10, pins 5 and 6) and then to the ALC bias
voltage line to prevent excessive current flow.
4·2·8 CW KEYING CIRCUIT (MAIN UNIT)
When the CW key is closed, the "KEY" signal line
becomes "LOW." 038 outputs 8 V to control break-in
operation, sidetone signal and transmit signal.
When the [BK IN] switch is pushed IN, 8 V from 038
charge C252 and 026 is turned ON, turning ON 052.
052 grounds the SEND line for transmitting. The [DELAY]
control (R244) adjusts the transmit release delay time.
The 8 V from 038 charges C249 and D91 is turned OFF,
disconnecting C249 from 040. 040 then oscillates a
sidetone signal.
R268 prevents sidetone click noise.
The 8 V from 038 is applied to a time constant and then to
the balanced modulator (IC6) to create a carrier signal.
R241 in the time constant adjusts a transmit delay timing
for
12 msec.
FOR voltage
-5V
______ ALC
voltage
R209
054
AMS
+ External
---~ALC
voltage
AMS
Fig. 5
4-5

While no CW transmit IF signal exists, 039 and 023 turn
the switching diode
(D35) OFF to ensure transmit isolation.
4-2·9 OUTPUT POWER METER CIRCUITS
(MAIN UNIT)
The "FOR" voltage from the PA UNIT is applied to the Po
meter amplifier (IC10 pin 3) and then to the meter. R189
and C261 are used for peak power measurement.
4-2·10 T/R SWITCHING CIRCUIT
(MAIN UNIT)
When the PTT or [TRANSMln switch is set to transmit,
IC13 pin 10 and IC13 pin 3 are "LOW." At this time,
049 turns ON, and O Vis present on the ''R8" voltage line.
050 turns OFF, and there is 8 V present on the "T8"
voltage line.
When the PTT or [TRANSMln switch is set to receive,
IC13 pin 10 and IC13 pin 3 are "HIGH." At this time,
049 turns OFF, and 8 V is present on the "RB" voltage
line.
050 turns ON, and there-is O V present on the
"T8" voltage line.
When PLL data or the operating mode is changed, the
"DNB" signal line becomes "LOW," turning OFF the TB -
preventing unwanted transmission.
4.3 PLL CIRCUITS
4·3·1 GENERAL DESCRIPTION
The PLL UNIT generates a 1st LO signal (70.9515-
100.4515 MHz variable) and 2nd LO signal (61.44 MHz
fixed)
used in the MAIN UNIT. The IC-725 uses a dual loop
PLL system. A main loop PLL uses 4 VCO circuits for
all HF band coverage within 512 kHz steps. A sub loop
PLL uses a DDS (Direct Digital Synthesizer) system for
512 kHz coverage within 10 Hz steps. The DDS system
provides a rapid lockup time and high quality frequency
oscillation.
4-3·2 REFERENCE OSCILLATOR CIRCUIT
(PLL UNIT)
A 30.72 MHz reference frequency is produced by the
oscillator 033 and X2. The reference frequency, buffer-
amplified at 034, is divided by 2 at IC15 and is then
applied to the PLL circuit as the PLL reference frequency.
The signal oscillated at 033 is multiplied by 2 at 036. The
resulting 61.44 MHz signal
is filtered at the bandpass
filter
and is then applied to the MAIN UNIT via P4 as
the 2nd LO signal.
4.3.3 MAIN LOOP (PLL UNIT)
The main loop uses a PLL IC (IC13) which contains a
programmable divider, phase detector, data shift register
and data latch circuits. The main loop generates
70.9515-100.4515 MHz signals in 512 kHz steps.
4-6
Because the sub loop produces 1O Hz steps, the PLL
produces a 30 MHz frequency range in 10 Hz steps.
The oscillated signal at one of the 4 VCOs (015, 017,
019, 021 ;
see Section 4-3-4 for details) is amplified at 023.
The signal is mixed with the sub loop output (fLO:
62.05-62.56199 MHz) at IC16. 023 is an isolator which
ensures that the mixer input does not affect the
VCO
output.
The mixed signal is amplified at 027 and is then filtered
at the low-pass filter (L23-L25, C92, C93, C99-C103).
The filtered signal, amplified at 026, is divided by 4 at
IC14 and is then applied to the PLL IC (IC13).
The phase of the divided signal at IC14, detected at
the
PLL IC (IC13) using a reference frequency (fREF) of
512 kHz, is then output from pin 17. The 512 kHz
frequency is obtained from the reference oscillator (033).
30.72 MHz oscillated at 033, is divided by 2 at IC15 and
divided by 30 at the programmable divider section of IC13.
The phase detected signal is then converted to the lock
voltage at the loop filter
(012-014), and applied to the
VCO. Thus, the VCO output (PLL output) is locked to
produce stable oscillation.
The PLL oscillation frequency is obtained by the following
calculation:
fv=fLo+NrxfREF
fv : Main loop output
fLO : Sub loop output
Nr : Dividing·ratio from the CPU
fREF: Reference frequency (512 kHz)
4.3.4 VCO CIRCUIT (PLL UNIT)
The transceiver's C/N ratio is determined by the VCO and
the loop filter. 4 VCO circuits keep the low noise and
reduce spurious emissions. 016, 018, 020
and 022 are
VCO switches which select the operating VCO with
"VC01"-"VC04" lines.
4.3.5 SUB LOOP (PLL UNIT)
The sub loop uses the DDS system that generates
62.05-62.56199 MHz signals in 10 Hz steps.
The oscillated signal at the VCO (029) is buffer-amplified at
030 and mixed with the 2nd LO signal (61.44 MHz) at
IC17. The resulting signal passes through the low-pass
filter, is amplified at 032, and is then applied to the DDS
UNIT.
The output pulse-type signal from the DDS UNIT passes
through the loop filter (R133, R134, C114, C115, L42)
where it is converted into a DC signal (lock voltage). The
lock voltage is applied to the VCO to lock the oscillating
frequency.

PLL CIRCUIT BLOCK DIAGRAM
MAIN LOOP
r-------------------------,
I
I
012-014
LOOP
FILTER
IC13
IC14
DIVIDER
1/4
VC01-VC04
0 VC01
015
VC02
017
VC03
019
VC04
021
fv: 70.9515-
100.4515 MHz
AMP
023
fv
fv-fLO: 8.5015-37.88951 MHz
BUFFER
026 LPF AMP
027
L_ - 2.:-~~H!.,_ ----- ----------- __ .J
r-------------------1
VC05 I
LO AMP
024
DIVIDER
1/2
DDS
LOOP
FILTER I
fLo: 62.05-
1 62.56199 MHz
DATA
I
I
I
0.61-1.12199 MHz
I
BUFFER + IC17 I
I a~ I
L--- --- --- -- ------ ___ J
BUFFER
034
REFERENCE
OSCILLATOR
033
MULTIPLIER
x2 036
SUB LOOP
Fig. 6
2nd LO
........ ....---• 61.44 MHz
4·4 LOGIC CIRCUITS BAND
FREQUENCY (MHz) BPF
VOLTAGE
4-4·1 BAND SELECTION DATA (PLL UNIT)
To select the correct bandpass filter, the low-pass filter and
VCOs on the MAIN and PLL UNITS, the CPU outputs the
following data.
R29-R40 and D29-D35 convert the "B0"-"87" signals
into a band voltage
(O- 7 .5 V) for external equipment.
0.5-1.599
1.6-1.999
2.0-3.999
4.0-7.999
8.0-10.999
11.0-14.999
15.0-21.999
22.0-30.0
BO
7.5 v
81
82 5.9V
83
5.0V
B4
O.OV
85
4.1 v
86 3.2 v
87 2.2 v
1st LO to
MAIN UNIT
LPF
L1
L2
L3
L4
LS
L6
vco
VC01
VC02
VC03
VC04

4-4·2 CPU (PLL UNIT)
The CPU (IC8) contains an 8-bit CMOS CPU, 16k-byte ROM
and 256-byte RAM. The CPU controls operating
frequency,
mode and the function display, etc. The
memory contents are stored in the CPU using a lithium
backup battery for more than 5 years.
The lcom Cl-V network system allows that the IC-725 can
be remotely controlled by a personal computer using an
RS-232C signal line.
4-4-3 RIT CIRCUIT (PLL UNln
IC12 is an AID converter which outputs 8-bit serial data
regarding analog input voltage. A voltage, controlled by
the
[Rln control, is applied to IC12 pin 4 and the resulting
serial data
is applied to the CPU matrix Y 4-+ DB4.
4.4.4 KEY MATRIX
YO
Y1
Y2
Y3
Y4
BAND M-CH UP
MIC UP/DN
Fig. 7
4-4-5 PARALLEL/SERIAL CONVERTER
(PLL UNln
IC11 is a parallel/serial converter IC. Parallel data from
the
CPU are converted into serial data to transfer the PLL
N-clata, DDS N-data, data for LCD driver, etc.
When the power is turned ON, the CPU also outputs
programmable divider data and a control signal for
universal ports to the PLL IC (IC13).
4-5 REGULATOR CIRCUITS
Either 8, 5 or - 5 V DC are supplied from corresponding
regulator circuits. 8, 5 and - 5 V DC are regulated at
the following circuits using 13.8 V
DC.
(1) 5 V REGULATOR (PLL UNIT)
5 V DC are regulated by the three-terminal voltage
regulator
(IC10).
(2) 8 V REGULATOR (MAIN UNIT)
8 V DC are regulated by the three-terminal voltage
regulator
(IC14).
(3) -5 V REGULATOR (PLL UNIT)
IC6 generates a negative pulse-type voltage by converting
the
DC input to AC voltages (approx. 6.7 kHz) as a
multivibrator.
The voltage is rectified at D8 and D9,
regulated by a Zener diode (D10) and C13, and is then
applied to the MAIN UNIT.
4-7

SECTION 5 MECHANICAL PARTS AND DISASSEMBLY
5·1 FRAME DISASSEMBLY

i
I
~
0 c
"'-..'
~
..,
@
CD
~
I
VRUNIT
(81786C)
I
~@
l---®
5-1

• FRAME DISASSEMBLY
LABEL ORDER
DESCRIPTION QTY.
LABEL ORDER
DESCRIPTION
QTY.
NUMBER NO. NUMBER
NO.
© 8110003270 Top cover 1 @ 8930000720 Thread spacer M 4
® 8110003280 Bottom cover 1 @ 8930013990 610 Brake plate 1
® 8930002900 Rubber foot (A) 2 @ 8930014030
61 OBrake pat 1
© 8930005790 Foot
(A)
1 @ 8930013940
61 OBrake sheet 1
® 8930005800 Foot (B) 1
®>
8810001110 PH BO M3x6 1
® 8010001520 Stand
(C)
1
@>
8810005470
PH M2.6 x 14 ZK 1
(J)
8810005520 PH B1 M3x8 ZK 4 @ 8810001650 PH FT M3x6
9
® 8810005540
PH B1 M4x10
2 @ 8810001320
PH B1 M2.6x6 Ni 4
® 8010007851 610 Chassis-1 1 @ 8510001330 79 shield case 1
@>
8810001350 PH B1 M3x6
16 @ 8510001340 79 shield case cover 1
(jJ)
8810002160 FH M3x5
16 @ 8510001060 Shield case 1
@ 8810003670 ICOM
screw A 6 2 @ 8510001740 Shield case cover 1
@ 8810005510
FH M3x6 ZK BS
16 @ 8510000881 194
VCO case-1 1
0 8210004670 610 Front panel
(B} 1 @ 8510003460 194 VCO case cover (A) 1
@ 8610004640 Button K119 [VFO] 1 @ 8510000230 220 shield case 1
@ 8610004650 Button K119
(A) [SPLIT] 1 '®)
8510002200
VCO case 1
@ 8610004660 Button K119 (B) [UP] 1 @ 8510000881 194 VCO case-1 1
@ 8610004670 Button K119 (C) [MEMO] 1 ® 8510002690 PA shield case (B) 1
@ 8610004680 Button K119 (D) [MW] 1 @ 8510004360
PA shield case (B) cover (A)
1
" @ 8610004690 Button K119
(E) [DOWN] 1 @ 8510005310 DDS shield case 1
~· \ @ 8610004700 Button K119 (F) [FUNC] 1 ® 8510005320 DDS shield case cover 1
@ 8610004710 Button K119 (G) [RIT, TUNER] 2 ® 2230000120 Switch [POWER] SDDSA3159A 1
@ 8610004720 Button K120 [SSB, CW/N, AM/FM]
3 @ 6510000190 Connector [MIC] FM214-8SS
(P) 1
@ 8610004730 Button K121 [kHz, MHz, BAND] 3 @ 7600000100 Rotary encoder EC24B50B0013A 1
@ 8610003850 Button K98 [TRANSMIT] 1 I@ 7210000570 Variable resistor [RIT] 1
@ 8610004741 Button K122-1 [LOCK] 1 Connector [PHONES]
~
6450000810 HLJ4306-01-3070 1
@ 8610004751 Button K123-1 [NB, ATT, PRE, AGC] 4
@ 8610004760 Dial N104 (A) {!) 7210001320 Variable resistor [AF/SOL]
(incl. rubber ring and screw) 1 RK124221002DA 1
@ 8610004770 Knob N45C [AF, MIC] 2 Variable resistor [MIC/RF
PWR]
(@
7210001550 RK1242210032A 1
®)
8610000500 Knob N69 [SOL,
RF PWR] 2
@ 8610001560 Button K42 [POWER] 1 Variable resistor [RIT]
(@ 7210001530 RK09K1110AEGA 1
@ 8610004780 Knob N87 (B) [RIT] 1
@ 8010007860 610 Sub chassis 1 @ 0910006330 Flexible cable
P.C. Board B 792 1
@ 8930003200 Spacer
(P)
1
Screw abbreviations
PH: Pan head FH: Flat head BO, B1, FT: Self-tapping screw ZK: Black Ni: Nickel
BS: Brass
5-2

ACCESSORIES
5·2 PA UNIT AND
~/
r1 '
@
I FIL TEA UNIT
(B 1791C) ~
5-3
PA UNIT
(B 17900)
®

•PA UNIT
LABEL
ORDER
DESCRIPTION
NUMBER NO.
Q)
8410000781
401 Heatsink-1
® 8510005462
PA cover-2
@ 6810001910
PH M3x6 Ni BS
© 8850000420 Spring washer
M3 Ni
® 8810001350
PH B1 M3x6
® 8810003170 Set screw A M3 x 8
(j) 6910000310 Bushing B312D
® 8810003670 ICOM screw
A6
® 8810003210 Set screw A
M3x15
@)
8810000220
PH M3x5
([j)
8810001980
PH M5x 16 Ni BS
@ 8850000590 Star washer M5
@ 8850000440 Spring washer M5
Ni
0 8830000210 Nut M5 Ni
BS
@ 8850000150 Flat washer
M5 Ni BS
@ 8830000360 Wing nut
M5 Ni
@ 6510004880 ANT connector
MR-DS-E 01
@ 2510000040 Speaker C065K1210810
@>
6510003780 DC power socket LLR-6
Screw abbreviations PH: Pan head B1: Self-tapping screw Ni: Nickel BS: Brass
• ACCESSORIES
wa
ORDER
DESCRIPTION
NUMBER NO.
Q) Optional product
DC power cable OPC-025 A
® Optional product Hand microphone HM-12
@ 5210000080 Spare fuse
FGB 20A
© 5210000130 Spare fuse
FGB 4A
® 8810005500
FH B1 M4x12 CR
® 8810001600
PH ST M3x6
Screw abbreviations · PH : Pan head FH : Flat head
B1, ST: Self-tapping
screw
QTY.
Q) @
1
1
1
1
2
4
®ii
5-4
QTY.
1
1
2
2
24
7
1
2
1
4
1
1
1
1
2
1
1
1
1
@
~
@
~
@'iiii