Icom IC-7600 User manual

S-14523XZ-C1
Mar. 2009
HF/50 MHz TRANSCEIVER

This service manual describes the latest technical
information for the IC-7600 HF/50 MHz TRANSCEIVER
TRANSCEIVER at the time of publication.
NEVER connect the transceiver to an AC outlet or to a DC
power supply that uses more than specified. This will ruin
the transceiver.
DO NOT expose the transceiver to rain, snow or any liquids.
DO NOT reverse the polarities of the power supply when
connecting the transceiver.
DO NOT apply an RF signal of more than 20 dBm (100 mW) to
the antenna connector. This could damage the transceiver’s
front-end.
To upgrade quality, any electrical or mechanical parts and
internal circuits are subject to change without notice or
obligation.
MODEL VERSION TX OUTPUT POWER
IC-7600
[USA]
100 W
[EUR]
[EUR-1]
[ESP]
[KOR]
[TPE]
[CHN]
[ITR]
[FRA]
[EXP]
Be sure to include the following four points when ordering
replacement parts:
1. 10-digit Icom parts numbers
2. Component name
3. Equipment model name and unit name
4. Quantity required
<ORDER EXAMPLE>
1130013010 SN74AHC1G08DCK3 IC-7600 LOGIC UNIT 1 piece
8930079060 3073 DC PLATE IC-7600 CHASSIS 2 pieces
Addresses are provided on the inside back cover for your
convenience.
Icom, Icom Inc. and ICOM logo are registered trademarks of Icom Incorporated (Japan) in Japan, the United States, the United
Kingdom, Germany, France, Spain, Russia and/or other countries.
ORDERING PARTS
1. Make sure that the problem is internal before
disassembling the transceiver.
2. DO NOT open the transceiver until the transceiver is
disconnected from its power source.
3. DO NOT force any of the variable components. Turn
them slowly and smoothly.
4. DO NOT short any circuits or electronic parts. An
insulated tuning tool MUST be used for all adjustments.
5. DO NOT keep power ON for a long time when the
transceiver is defective.
6. DO NOT transmit power into a Standard Signal
Generator or a Sweep Generator.
7. ALWAYS connect a 50 dB to 60 dB attenuator between
the transceiver and a Deviation Meter or Spectrum
Analyzer when using such test equipment.
8. READ the instructions of test equipment throughly
before connecting a test equipment to the transceiver.
REPAIR NOTES
INTRODUCTION CAUTION

TABLE OF CONTENTS
SECTION 1 SPECIFICATIONS
SECTION 2 INSIDE VIEWS
SECTION 3 CIRCUIT DESCRIPITON
3-1 RECEIVER CIRCUITS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3-2 TRANSMITTER CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3-3 FREQUENCY SYNTHESIZER CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
3-4 VOLTAGE BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3-5 CPU PORT ALLOCATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
SECTION 4 ADJUSTMENT PROCEDURES
4-1 PREPARATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4-2 REFERENCE FREQUENCY SIGNAL LEVEL ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4-3 PLL UNIT ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4-4 PA UNIT ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
4-5 CTRL UNIT ADJUSTMENT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
4-6 MAIN ADJUSTMENT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
4-7 MAIN UNIT (SCOPE) ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
4-8 RF UNIT ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
4-9 SOFTWARE ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17
SECTION 5 PARTS LIST
SECTION 6 MECHANICAL PARTS
SECTION 7 BOARD LAYOUTS
SECTION 8 GENERAL WIRING
SECTION 9 BLOCK DIAGRAM
SECTION 10 VOLTAGE DIAGRAM
LOGIC UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
DISPLAY UNIT (Incl. VR-A, VR-B, VR-C, MIC, JACK and RIT BOARDS) . . . . . . . . . . . . . . . . 10-5
MAIN UNIT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8
PLL UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14
RF UNIT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17
TUNER UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-19
FILTER UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-20
CTRL UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-21
BPF UNIT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-24
DCDC UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-24
BPF UNIT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-24
PREAMP BOARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-25
PA UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-25
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1 - 1
SECTION 1
.
SPECIFICATIONS
NGeneral
• Frequency coverage : (unit: MHz)
Receive
0.030–60.000*1*2
Transmit
1.800–1.999*2, 3.500–3.999*2,
5.33050*3, 5.34650*3, 5.36650*3,
5.37150*3, 5.40350*3,
7.000–7.300*2, 10.100–10.150*2,
14.000–14.350*2, 18.068–18.168*2,
21.000–21.450*2, 24.890–24.990*2,
28.000–29.700*2,50.000–54.000*2
*1Some frequency bands are not guaranteed.
*2Depending on version. *3USA version only.
• Mode : USB, LSB, CW, RTTY, PSK,
AM, FM
• No. of memory channels : 101 (99 regular, 2 scan edges)
• Antenna connector type : SO-239 ×2 and phono jack
(RCA; 50 øimpedance)
• Temperature range : 0˚C to +50˚C (+32˚F to +122˚F)
• Frequency stability : Less than ±0.5 ppm 5 min. after
power ON.
(0˚C to +50˚C; +32˚F to
+122˚F)
• Frequency resolution : 1 Hz
• Power supply :
13.8 V DC ±15% (negative ground)
• Power consumption
Transmit : Max. power 23 A
Receive : Standby 3.0 A
Max. audio 3.5 A
• Dimensions :
340(W) ×116(H) ×279.3(D) mm
(projections not included) 133⁄8(W) ×49⁄16(H) ×11(D) in
• Weight (approx.) : 10.0 kg; 22 lb
• ACC 1 connector : 8-pin DIN connector
• ACC 2 connector : 7-pin DIN connector
• CI-V connector : 2-conductor 3.5 (d) mm (1⁄8″)
• Display : 5.8-inch (diagonal)
TFT color LCD
NTransmitter
• Output power (continuously adjustable)
SSB/CW/RTTY/FM : Less than 2 to 100 W
AM : Less than 1 to 30 W
• Modulation system
SSB : Digital PSN modulation
AM : Digital Low power modulation
FM : Digital Phase modulation
• Spurious emission
HF bands : Less than –50 dB
50 MHz band : Less than –63 dB
• Carrier suppression : More than 40 dB
• Unwanted sideband : More than 55 dB
suppression
• ∂TX variable range : ±9.999 kHz
• Microphone connector : 8-pin connector (600 ø)
• ELEC-KEY connector : 3-conductor 6.35(d) mm (1⁄4″)
• KEY connector :
3-conductor 6.35(d) mm (1⁄4″)
• SEND connector : Phono jack (RCA)
• ALC connector : Phono jack (RCA)
NReceiver
• Receive system : Double superheterodyne
system
• Intermediate frequencies
1st : 64.455 MHz
2nd : 36 kHz
• Sensitivity (typical)
SSB, CW, RTTY : 0.15 μV (1.80–29.99 MHz)*1
(10 dB S/N) BW=2.4 kHz 0.12 μV (50.0–54.0 MHz)*2
AM (10 dB S/N) : 6.3 μV (0.1–1.799 MHz)*1
BW=6 kHz 2 μV (1.80–29.99 MHz)*1
1.6 μV (50.0–54.0 MHz)*2
FM (12 dB SINAD) : 0.5 μV (28.0–29.99 MHz)*1
BW=15 kHz 0.3 μV (50.0–54.0 MHz)*2
*1Pre-amp 1 is ON. *2Pre-amp 2 is ON.
• Squelch sensitivity (Pre-amp: ON)
SSB : Less than 3.2 μV
FM : Less than 0.3 μV
• Selectivity
(IF filter shape is set to SHARP.)
SSB (BW: 2.4 kHz) : More than 2.4 kHz/–6 dB
Less than 3.8 kHz/–60 dB
CW (BW: 500 Hz) : More than 500 Hz/–6 dB
Less than 900 Hz/–60 dB
RTTY (BW: 350 Hz) : More than 350 Hz/–6 dB
Less than 650 Hz/–60 dB
AM (BW: 6 kHz) : More than 6.0 kHz/–6 dB
Less than 15.0 kHz/–60 dB
FM (BW: 15 kHz) : More than 12.0 kHz/–6 dB
Less than 20.0 kHz/–60 dB
• Spurious and image : More than 70 dB
rejection ratio
(except IF through on 50 MHz band)
• AF output power : More than 2.0 W at 10%
(at 13.8 V DC) distortion with an 8 øload
• RIT variable range : ±9.999 kHz
• PHONES connector : 3-conductor 6.35 (d) mm (1⁄4″)
• External SP connector : 2-conductor 3.5 (d) mm
(1⁄8″)/8 ø
• DSP ANF attenuation : More than 30 dB
(with 1 kHz single tone)
• DSP NR attenuation : More than 6 dB
(noise rejection in SSB)
NAntenna tuner
• Matching impedance range
HF bands : 16.7 to 150 øunbalanced
(Less than VSWR 3:1)
50 MHz band : 20 to 125 øunbalanced
(Less than VSWR 2.5:1)
• Minimum operating input : 8 W (HF bands)
power 15 W (50MHz band)
• Tuning accuracy : VSWR 1.5:1 or less
• Insertion loss : Less than 1.0 dB
(after tuning at RF power 100W)
Spurious signals may be displayed on the spectrum scope screen
regardless of the transceiver’s state (Tx or Rx). They are gener-
ated in the scope circuit. This does not indicate a transceiver mal-
function.
All stated specifications are typical and subject to change without
notice or obligation.
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2 - 1
SECTION 2
.
INSIDE VIEWS
• MAIN UNIT
USB INTERFACE
ATTENUATOR CIRCUITS
DDS CIRCUITS
3RD LO CIRCUIT
(For SCOPE )
2ND RX LO CIRCUITS
VCA (For TX AF CIRCUITS)
(IC2601)
T8 LINE CONTROLLER
(Q1102)
DC AMP
(IC1404)
D/A CONVERTER
(IC1403)
2ND TX IF FILTER SW
(IC3502)
2ND TX IF FILTER SW
(IC3501)
A/D, D/A CONVERTER
(IC4301)
LIMITER
(IC3002)
FLASH ROM
(IC5102)
R8 LINE CONTROLLER
(Q1112)
1/2 PRESCALER
(IC4005)
A/D CONVERTER
(IC4004)
VCA (For RX AF CIRCUIT)
(IC2331)
FLASH ROM
(IC5002)
TRX DSP
(IC5001)
SCOPE DSP
(IC5101)
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2 - 2
• CTRL UNIT
DC AMP
(FOR CURRENT DTECT)
(IC81)
TUNER LINE SW
(RL105)
TUNER LINE SW
(RL104)
CURRENT DETECTOR
(D81)
TX LINE CONTROLLER (1/2)
(Q132)
EXPANDER
(IC261 )
+5V REGULATOR
(IC204 )
DC AMP
(FOR SWR DETECT)
(IC1)
PHASE COMPARATOR
(IC23)
DC AMP
(FOR RESISTANCE AND
REACTANCE DETECT)
(IC51)
DC AMP
(FOR PHASE DETETECT)
(IC21)
TX LINE CONTROLLER (2/2)
(Q131)
BUFFER AMP
(FOR PHASE DETECT)
(IC22)
TUNER CPU
(IC201)
EEPROM
(IC202)
CPU REGULATOR
(IC203)
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2 - 3
• PA UNIT
+5V LINE REGULATOR
(IC2)
+3R3V LINE REGULATOR
(IC1)
DRIVER
(Q2)
ATC 5 A FUSE
(F1)
POWER AMP
(Q2)
DRIVER
(Q3)
COOLING FAN CONTROLLER
(IC101)
COOLING FAN DRIVER
(Q101)
POWER AMP
(Q101)
PRE-DRIVER
(Q1)
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2 - 4
• PLL UNIT
LEVEL CONVERTER
(IC2)
PLL CIRCUIT (FOR VCO-A)
(IC381)
EXPANDER
(IC4)
VCO-A
DDS CIRCUIT (FOR VCO-A)
(IC101)
DDS CIRCUIT
(FOR 2ND RX LO, 3RD TX LO)
(IC701)
VCO-B
DDS CIRCUIT (FOR VCO-B)
(IC403)
PLL CIRCUIT (IC681) AND
LO AMP AND FILTER CIRCUITS
(FOR VCO-B)
LO AMP AND FILTER CIRCUITS
(FOR VCO-A)
SUB LOOP VCO
(Q451)
EXPANDER
(IC3) LEVEL CONVERTER
(IC102)
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2 - 5
1ST RX IF CIRCUIT
(FOR SUB READOUT)
• RF UNIT
XTAL FILTER (Bw=15 kHz)
(FI7001)
PREAMP
(Q4201, 4202)
1ST RX IF CIRCUIT
(FOR MAIN READOUT)
PRE AMP BOARD
BPF UNIT
MCF-M BOARD
MCF-W BOARD
MCF-N BOARD
XTAL FILTER (Bw=6 kHz)
(FI6001)
XTAL FILTER (Bw=3 kHz)
(FI5001)
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3 - 1
• RF CIRCUITS
SECTION 3
.
CIRCUIT DESCRIPTION
TUNER_
NETWORK
RL101
1.6-
LP F
0.03-1.599999 MHz
TX circuits
LPF
PRE
AMP
Q4201/Q4202
PRE
AMP
Q4203
59.999999 MHz
8-
7.999999 MHz
ATT ATT
D131
CP3
CP4
CURRENT
DETECT
ANT1
J5 J6
ANT2
TUNER
UNIT
CTRL UNIT
RF UNIT
To the 1st RX
IF circuits
B0
D801D802
RX ANT
6 dB12 dB
D201
PREAMP
BOARD
IN OUT
D8 1
RL105
RL104
RL103
TX circuits
RL105
RL104
RL101
RL102
RL103
BPF BOARD
BPFs
(B1-B5)
RX FILTER CIRCUITS
BPFs
(B5-B10,
B10W)
3-1 RECEIVER CIRCUITS
ANTENNA SWITCHING CIRCUIT AND ANTENNA
MATCHING CIRCUITS (CTRL AND TUNER UNITS)
RX signals from the antenna connector; [ANT1] (J5) or
[ANT2] (J6) are passed through the antenna switch (RL101)
and current detector (D81), and applied to the RF UNIT
via the tuner switches (RL104 and RL105), RX line switch
(RL103) and LPF.
If the automatic antenna tuning function is activated, the RX
signals from the current detection circuit (D81, 301, 302)
are applied to the antenna tuning network on the TUNER
UNIT to match the transceiver to the connected antenna
automatically.
The RX signals from the TUNER UNIT are applied to the RF
UNIT via the RX line switch (RL103) and LPF.
ATTENUATOR CIRCUITS (RF UNIT)
The RX signals from the CTRL UNIT are passed through
the RECEIVE ANTENNA IN/OUT CONNECTOR switches
(RL104, 105) and RX line cut switch (RL101), then passed
through or bypassed the attenuator circuits, according to the
setting.
The combination of attenuator (or bypass) that the RX
signals are passed through determines the entire attenuation
level; 0 dB, 6 dB, 12 dB or 18 dB.
The RX signals which are passed though or bypassed the
attenuator circuits are applied to the BPF circuits.
BPF CIRCUITS (RF UNIT AND BPF BOARD)
The RX signals from the attenuator circuits are passed
through an LPF or one of BPFs correspond to the operating
frequency, to remove unwanted out-of-band signals.
The table below shows filter which the RX signals are
passed in each frequency range.
Name of
BPF Frequency range Located on
B0 0.03–1.599999 MHz RF UNIT
B1 1.6–1.999999 MHz BPF BOARD
B2 2.0–2.999999 MHz BPF BOARD
B3 3.0–3.999999 MHz BPF BOARD
B4 4.0–5.999999 MHz BPF BOARD
B5 6.0–7.999999 MHz BPF BOARD
B6 8–10.999999 MHz RF UNIT
B7 11–14.999999 MHz RF UNIT
B8 15–21.999999 MHz RF UNIT
B9 22–29.999999 MHz RF UNIT
B10
(for RX) 50–54 MHz RF UNIT
B10W 30–49.999999 MHz
54.000001–59.999999 MHz RF UNIT
B10TX
(for TX) 50–54 MHz RF UNIT
The filtered RX signals are applied to the PREAMP BOARD.
PREAMPLIFIERS (PREAMP BOARD)
The RX signals from the BPF circuits are applied to or
bypassed the preamplifier.
When the PREAMP FUNCTION is activated, the RX signals
are amplified by one of preamplifiers (Q4201, Q4202 or
Q4203).
The amplified or bypassed RX signals are applied to the RF
UNIT again.
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• 1ST RX IF CIRCUITS
3 - 2
LPF
BPF
XTAL
BPF
XTAL
BPF
XTAL
SPLIT
L1018
HYBRID
COMBINER
PIN DIODE
PIN DIODE
ATT
IF
AMP
RF
AMP
1st RX LO signals
for sub readout
1st RX LO signals for main readout
(64.485-124.455 MHz)
(64.485-124.455 MHz)
LPF
ATT
IF
AMP
RF
AMP
TX CIRCUITS
15K
Fc=60MHz
From the PREAMP BOARD
L904,905
6K
3K
RF UNIT
MCF-N
BOARD
MCF-M
BOARD
MCF-W
BOARD
Fc=60MHz
Q1201
Q1202
D1201,1203,1204
1st RX IF mixer
<-1st RX IF
<-Main readout path
<-Sub readout path
<-1st RX IF
1st RX IF mixer
Q1203-1206
Q1208
D601
D1551
FI6001
FI5001
FI7001
Q1008
D1001-1003
Q1003-1006
Q1001
Q1002
D3702
D3701
LPF
IF
AMP
Q3601-3603
To the 2nd RX IF
circuits
MAIN UNIT
1ST RX IF CIRCUITS (RF UNIT)
The RX signals from the PREAMP BOARD are applied
to the splitter (L904) to divide the received signals for
dualwatch operation.
The separated RX signals are passed through the LPF
which removes unwanted signals (60 MHz and higher), and
amplified by the RF AMP (Main readout; Q1201, 1202/Sub
readout; Q1001, 1002), then applied to the 1st RX IF mixer
(Main readout; Q1203–1206/Sub readout; Q1003–1006).
The RX signals are converted into the 1st RX IF signal by
being mixed with 1st RX LO signals (64.485–124.455 MHz)
from the PLL UNIT.
The converted 1st RX IF signals are passed through the
2-staged attenuator (Main readout; D1201–1203/Sub
readout; D1001–1003) which adjusts the balance of both
1st RX IF signals, and amplified by 1st RX IF AMP (Main
readout; Q1208/Sub readout; Q1008).
These amplified 1st RX IF signals are combined by the
hybrid combiner (L1018), and applied to the 1st IF filter
circuits.
The combined 1st IF signal is passed through one of the
1st IF filters on the MCF-N/-M/-W BOARDS which has
different passband widths. The filter to be passed through is
according to the IF filter setting.
The filtered 1st RX IF signal is applied to the RF UNIT again,
and passed through the LPF and amplified by the RX IF
AMP (MAIN UNIT: 3601–3603).
The amplified 1st RX IF signal is then applied to the 2nd RX
IF circuits.
2ND RX IF CIRCUITS (MAIN UNIT)
The 1st RX IF signal from the 1st RX IF circuits is divided
into two paths, and each signal is applied to the 2nd RX
IF mixers (Image reduction mixer; D3202/D3201) to be
converted into the 2nd RX IF signal, by being mixed with the
2nd RX LO signal (64.494 MHz) from the PLL UNIT.
The image reduction mixer removes image frequency
components by using LO signals which are 90 degrees
phase-shifted from each other.
The converted 2nd RX IF signals are amplified independently
by the buffer (Q3202/Q3201) and IF AMP (IC3203).
These amplified 2nd RX IF signals are 90 degrees phase-
shifted from each other by the phase shifter (IC3202; pins
8-10, pins 12–14). These phase-shifted 2nd RX IF signals
are combined by the combiner (IC3202; pins 5–7) to be
converted into the 3rd RX IF signal.
The converted 3rd RX IF signal is amplified by the 3rd IF
AMP (IC3201), and passed through the limiter (IC3002) and
balance-unbalance converter (Balun; IC4001/IC4002), then
applied to the demodulator circuits.
DEMODULATOR CIRCUITS AND DSP (MAIN UNIT)
The 3rd RX IF signal from the 3rd RX IF circuits is applied
to the A/D converter (IC4004) to be converted into the digital
signal.
The converted digital signal is applied to the DSP (IC5001),
and demodulated and processed.
The demodulated signal is applied to the D/A converter
(IC4301) to be converted into the analog signal, then applied
to the buffer amplifier (IC4401; pins 1–3).
The buffer amplified AF signals are applied to the RX AF
circuits.
IC4401
To the AF circuits
DSP
IC5001
D3201
IF
AMP
BALUN
IC4001,
IC4002
BALUN
IF
AMP
IC3203
IC3203
BUFF
Q3202
2nd RX LO signal
D3202 From the 1st
RX IF circuits
IF
AMP
IC3201
BUFF
Q3201
IC3202 IC3202
COMBINER
(64.491 MHz)
LIMITER
IC3002
A/D
IC4004
D/A
IC4301
90deg.
PHASE
SHIFT
Σ
MAIN UNIT
<-2nd RX IF
<-3rd RX IF<-Digital<-Analog<- RX AF
• 2ND RX IF, 3RD RX IF AND DEMODULATOR CIRCUITS
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3 - 3
AM P
RL2302
PWR
AMP
IC2312
VCA
IC2331 IC2331
AF
AM P
IC2301
SP1
LPF
Q2361
Squelch gate
AF mute SW
From the demodulation circuits
INT. SP
CHASSIS
J7
PHO/AFO
[PHONES]
[EXT-SP]
• RX AF CIRCUITS
3-2 TRANSMITTER CIRCUITS
TX AF CIRCUITS (MAIN UNIT)
The audio signals from the microphone (MIC signals)
are applied to the MAIN UNIT via the MICROPHONE
CONNECTOR (MIC BOARD; J1), and applied to the Voltage
Controlled Amplifier (VCA; IC2601).
The applied MIC signals are amplified by internal MIC AMP,
and adjusted its level (=MIC gain) by internal VCA circuit.
The level-adjusted MIC signals are passed through the
MIC line selector (IC4101), and amplified by the AF AMP
(IC4205), then applied to the modulation circuits.
The signals from the external equipment connected to the
accessory socket [ACC1] on the rear panel, are directly
applied to the AF AMP (IC4205) via the MIC line selector
(IC4101).
RX AF CIRCUITS (MAIN UNIT)
The AF signals from the buffer amplifier are applied to
the AF AMP (IC2301) via the squelch gate (Q2361). The
amplified AF signals are applied to the Voltage Controlled
Amplifier (VCA; IC2231) to be adjusted its level (=audio
output level).
The level-adjusted AF signals are applied to the AF power
AMP (IC2312) via the LPF (Q2312).
The amplified MIC signals are applied to the modulation
circuits.
MODULATION CIRCUITS AND DSP (MAIN UNIT)
The MIC signals from the TX AF circuits are applied to the
Balance-Unbalance converter (Balun; IC4201, 4204), and
the converted MIC signals are applied to the A/D converter
(IC4301) to be converted into the digital signal.
The converted digital signal is applied to the DSP (IC5001)
and modulated and processed.
The modulated signal is converted into the analog signal by
the D/A converter (IC4301), and passed through the balun
(IC4401) to be converted into the 3rd TX IF signal.
The converted 3rd TX IF signal is applied to the 3rd TX IF
circuits.
The power-amplified AF signals are passed through the AF
mute switch (RL2302), then applied to the internal speaker
or external speaker jack (J2302) on the rear panel or
headphone jack (JACK BORD J2) on the front panel.
IC4401
3rd TX IF circuits
3rd TX IF->
DSP
IC5001 IC4301
IC4101
MIC
AMP
IC2601
CP1
IC4201,
IC4204
VCA
MIC GAIN ADJ.
MIC LINE SELECT
MC 1 MIC_IN
AF BALUN BALUN
AM P
IC4205 IC4301
A/D
(CODEC)
D/A
(CODEC)
ACC(1)
MOD
MIC BOARD
MAIN UNIT
• TX AF AND MODULATION CIRCUITS
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3 - 4
3RD TX IF AND 2ND TX IF CIRCUITS (MAIN UNIT)
The 3rd TX IF signal from the modulation circuits is applied
to the 3rd TX mixer (IC3402) via the LPF (IC3401) to be
converted into the 2nd TX IF signal, by being mixed with
the 3rd TX LO signal from the PLL UNIT. The converted 2nd
TX IF signal is amplified by the IF AMP (Q3501), passed
though the one of 2nd TX filters (FI3501; for FM, AM mode
or FI3502; for SSB, CW, RTTY, PSK mode) via the filter
switches (IC3501 and IC3502).
The filtered 2nd TX IF signal is amplified by the 2nd TX IF
AMP (Q3504), and applied to the 2nd TX mixer (D3703) via
the attenuator to be converted into the 1st TX IF signal, by
being mixed with the 2nd TX LO signal from the PLL UNIT.
The converted 1st TX IF signal is applied to the 1st TX IF
circuits on the RF UNIT via the attenuator and IF switch
(D3702).
D3703
BPF
CERAMIC
FI3501
IC3401
From the modulation circuits
2nd TX IF->
LPF
IC3501 IC3502
ATT
3rd TX LO signal
(491 kHz)
IC3402
ATT
2nd TX LO signal
(64 MHz)
IF
AM
FILTER
SWITCH
FILTER
SWITCH
P
Q3501
ALC
IF SW
RX circuits
To the 1st TX IF circuits
D506
1st TX IF->
2nd TX MIXER
3rd TX mixer
BPF
CERAMIC
FI3502
IF
AMP
Q3504
4kHz
20kHz
MAIN UNIT RF UNIT
• 3RD AND 2ND TX IF CIRCUITS
1.6-
HPF
50MHz
8-
7.999999MHz
D1401
LPF
Fc=60 MHz
D201
RX circuits
RF
AMP
D1451
1st TX MIXER
TX SIGNAL->
ATT
RF UNIT
IC1401
1st TX LO signal
(64.485-124.455 MHz)
BPF BOARD
BPFs
(B1–B5)
BPFs
(B5–B9,
B10TX)
IF
AM P LPF
Q1551
1st TX IF SIGNAL->
From the 2nd
TX IF mixer
To the TX AMPs
ALC
RX circuits
BPF
XTAL
15K
MCF-W
BOARD
FI7001
• 1ST TX IF CIRCUITS
1ST TX IF CIRCUITS (RF UNIT AND MCF-W BOARD)
The 1st TX IF signal from the 2nd TX IF circuits is passed
through the 1st TX IF filter (MCF-W BOARD; FI7001) to
remove unwanted signals in wide bandwidth. The filtered 1st
TX IF signal is passed through the TX/RX switch (D1551),
amplified by the IF AMP (Q1551), and applied to the 1st TX
mixer (D1451) via the LPF to be converted into the TX signal
(TX frequency itself), by being mixed with the 1st TX LO
signals from the PLL UNIT.
The converted TX signal is passed through the LPF, and
amplified by the RF AMP (IC1401), then applied to the BPF
circuits via the attenuator.
BPF CIRCUITS
The TX signal from the 1st TX IF circuits is passed through
an LPF or one of BPFs according to the transmitting
frequency, to remove unwanted signals contained in the TX
signal.
Refer to the table on page 4-1 for the filter which the TX
signal is passed through.
The filtered TX signal is applied to the TX amplifier circuits
via the HPF and TX line switch (D201).
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3 - 5
RL252 RL253
D301/D302
TUNER_
CPU
TUNER_
NET
RL101
ATT YGR
AMP
LPF-1
LPF-2
LPF-3
LPF-4
LPF-5
LPF-6
LPF-7
RL402 RL401
RL352 RL351
RL252 RL251
RL302
RL102
RL201
RL101
RL202
RL301
PHASE
DET
D21,22
L21
SWR
DET
D 1/D2
DRIVE
PRE
LPF
PWR
AM P
DRIVE
(PUSH-PULL)
RESIST
DET
RL151RL152
ATT
LPF
AMP
AMP
AMP
FORV (FORWARD WAVE)
REFV (REFLECT WAVE)
CURRENT
DETECT
ANT1 ANT2
TUNER
UNIT
CTRL UNIT
1.8MHz
3.5M/3.8M/4.63MHz
5M/7MHz
18M/21MHz
24M/28MHz
50MHz
10M/14MHz
PA UNIT FILTER UNIT
RF UNIT
D8
IC201
IC1
IC51
IC51
RL103
RX circuits
IC201
Q1
Q2,Q3
Q4,Q5
D41/D42
From TX circuits
• TX AMPLIFERS AND TX FILTER CIRCUITS
TX AMPLIFIER CIRCUITS (RF AND PA UNITS)
The TX signal from the BPF circuits is applied to the YGR
AMP (RF UNIT; IC201) via the attenuator. The amplified TX
signal is applied to the PA UNIT via the LPF.
The TX signal from the RF UNIT is applied to the pre-drive
AMP (Q1) via the attenuator, and the amplified TX signal is
applied to the drive AMP (Q2, 3) via the LPF. The amplified
TX signal is then power-amplified by the power AMP (Q4, 5).
The power-amplified TX signal is applied to the TX filter
circuits.
TX FILTER CIRCUITS
The power-amplified TX signal from the PA UNIT is passed
through one of LPFs according to the transmitting frequency,
to remove harmonic components contained in the TX signal.
The filtered TX signal is applied to the CTRL UNIT.
ANTENNA TUNING AND SWITCHING CIRCUITS
(CTRL UNIT)
The TX signal from the FILTER UNIT is passed through
4 detection circuits on the CTRL UNIT before being fed to
the antenna connector [ANT1] or [ANT2].
Based on the parameters from these 4 detection circuits,
the tuner CPU (IC201) controls matching networks on the
TUNER UNIT to match the transceiver and connected
antenna.
SWR DETECTION CIRCUIT
The forward wave is rectified by D2 at the current detect
transformer (L1). The rectified voltage is DC amplified by IC1
and applied to the A/D port of the tuner CPU (IC201).
The reflected wave is rectified by D1 at the current detect
transformer (L1). The rectified voltage is DC amplified by IC1
and applied to the A/D port of the tuner CPU (IC201).
PHASE DETECTION CIRCUIT
The TX signal which is picked up at the current detect
transformer (L21) and the TX signal which is divided by C21,
C22 and C24, are rectified by D21 and D22, and amplified
by C-MOS IC (IC21).
The amplified signal is applied to the IC23 via the buffer
(IC22) for phase comparison. The resulting signal of phase
comparison is rectified by D23 and D24, and composed and
amplified by IC51, then applied to the A/D port of the tuner
CPU (IC201).
This AMP, as the first stage, employs a C-MOS type AMP to
detect the low TX signal. The inverter AMP requires input level
lower than others need, and provides high speed operation
for stable high frequency operation with low TX signal.
RESISTANCE DETECTION CIRCUIT
A portion of the TX signal is divided by C42 and C44, and
rectified by D42 to be converted into DC signal.
Another portion of the TX signal is rectified at the current
detect transformer (L41) to be converted into DC signal too.
And the voltage of these signals are the same when the
connected load (=antenna) is 50 Ω. Thus the difference of
these voltages represents the resistance components.
By comparing the difference of these voltages, the
transceiver detects the resistance components.
The detected resistance components are amplified by IC51
and applied to the A/D port of the tuner CPU (IC201).
CURRENT DETECTION CIRCUIT
A portion of the TX signal is rectified by D81, L81 and R81,
and applied to IC81 to be level-compared with the voltage
from the SWR detection circuit.
When the connected load (=antenna) is less than 10 Ω,
the TX signal is bypassed the TUNER UNIT via the tuner
switches (RL104 and RL105) compulsorily, to protect the
circuit on the TUNER UNIT from reflected waves.
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3 - 6
3-3 FREQUENCY SYNTHESIZER (PLL UNIT)
REFERENCE FREQUENCY OSCILLATOR CIRCUIT
The crystal oscillator (X51) oscillates the 32 MHz reference
frequency signal. This reference signal is applied to the
Local Oscillator (LO) circuits via the buffer (Q51) and LPF
(L53, C55–57).
2ND TX LO CIRCUIT
The 32 MHz reference signal from the reference frequency
oscillator circuit is doubled by the doubler (Q61) and passed
through the double-tuned filter (L61, 62) to extract the 64 MHz
of 2nd harmonic component. The extracted 64 MHz signal is
applied to the RF UNIT via the buffer (Q71) and the BPF as
the 2nd TX LO signal.
3RD TX LO CIRCUIT
Using the 32 MHz reference clock signal from the reference
frequency oscillator circuit, the 491 kHz 3rd TX LO signal is
directly generated by 10-bit DDS (IC701) and D/A converter
(R701–720). The generated 491 kHz signal is passed
through the BPF and amplified by Q702, then applied to the
RF UNIT.
The generated 491 kHz signal from Q702 is also used to
generate the 2nd RX LO signal, by being applied to the 2nd
RX LO circuit.
2ND RX LO CIRCUIT
The 64 MHz reference signal from the double-tuned filter
(L61, 62) and the 491 kHz signal from the 3rd TX LO circuit
is mixed by the 2nd RX LO mixer (D821, L821, 822), to
generate the 2nd RX LO signal.
The generated 2nd RX LO signal is filtered by the crystal
filter (FI831) and amplified by Q831, then applied to the RF
UNIT as the 2nd RX LO signal.
1ST RX (Main readout)/TX LO CIRCUITS
The 32 MHz reference signal from the reference frequency
oscillator circuit is amplified by Q152, and applied to the
DDS (IC101) as the reference clock signal. The DDS (IC101)
generates the PLL reference frequency signal, using applied
reference clock signal.
The generated PLL reference frequency signal is filtered by
the ceramic BPF (FI101) and LPF, amplified by Q151, then
applied to the PLL IC (IC381) vian LPF as the main loop
reference frequency signal.
The reference frequency signal is used for phase comparison
of oscillating signals from the VCO-A (Q201, 221, 251, 271).
The resulting signal of phase comparison is converted into
the lock voltage which controls the oscillation frequency of
VCO-A (Q201, 221, 251, 271), by being passed through the
passive loop filter.
The output signals of the VCO-A (Q201, 221, 251, 271) are
buffer-amplified by Q301, filtered by the BPF, and amplified
by IC320, then filtered by the LPF for harmonic removal.
The filtered VCO output signals are passed through the BPF
and LO mute switch (Q361, D361, 362), then applied to the
RF UNIT as the 1st RX LO (for Main readout)/TX LO signals.
A portion of VCO output signals from the LPF are fed back
to the PLL (IC381) for the phase-locked loop.
VCOs (VCO-A)
Q201, Q221, Q251 and Q271 compose four oscillators,
and each VCO generates the 1st RX/TX LO signals. These
VCO employ high "Q" components as resonator (L202, 222,
252, 272) for high C/N characteristic and wide oscillation
frequency range.
The table below shows the oscillation frequency range of
VCO-A and the RX frequency range.
Composed
by RX Frequency range
Oscillation frequency range
(1st LO)
Q271 0.03–7.999999 MHz 64.485–72.454999 MHz
Q251 8–19.999999 MHz 72.455–84.454999 MHz
Q221 20–44.999999 MHz 84.455–109.454999 MHz
Q201 45–60 MHz 109.455–124.455 MHz
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• FREQUENCY SYNTHESIZER CIRCUITS
FIL
LOOP BUFF PLL
IC
D/A
FIL
LOOPPLL
IC
BUFF
BPF
CERAMIC
DDS
FIL
LOOP SPLIT
BPF
XTAL
D505
BPF
BPF
BPF
BUFF BPF
BPF
MUTE
DDS
DDS LPF
BPF MUTE
BUFF
AMP
AMP
AMP
AMP
AMP
AMP
AMP
BPF
CERAMIC AMP LPFAMPLPFAMP
LPF
AMP D/A
BUFF BPF
2nd RX LO signal
2nd TX LO signal
64.0 MHz DSP system clock signal
3rd TX LO signal
X2 BPF
64.491 MHz
84.455-
109.454999MHz
72.455-
84.454999MHz
64.485-
72.454999MHz
109.455-
124.455MHz
64.0MHz
PLL UNIT
64.485-
72.454999MHz
64.485-124.455 MHz
64.485-124.455 MHz
109.455-
124.455MHz
84.455-
109.454999MHz
72.455-
84.454999MHz
1st RX LO signals
1st RX/TX LO signals
D361 D362
Q361
IC320
Q301
Q271
Q251
Q221
Q201
IC381
Q151
IC101 FI101
Q152
Q403
IC403
Q451
SUB LOOP VCO
Q452 R459-462
Q402
IC402
FI401
R401-424
R701-720
IC681
Q571
Q551
Q521
Q501
Q601 IC620
D661 D662
Q661
Q701 IC701 Q702
L821,822
FI831 Q831
Q71
491 kHz
Q87
Q61 L61,62
Q801
BUFF
L53,C55–57
LPF
32MHz
32MHz
32MHz
32MHz
32MHz
32MHz
REFERENCE FREQUENCY
CILLATOR CIRCUIT
SUB LOOP
MAIN LOOP
2nd TX LO CIRCUIT
VCO-A
VCO-B
2nd RX LO CIRCUIT
3rd
TX
LO
CIRCUIT
DSP CLOCK CIRCUIT
Q51 X51
1ST RX (Sub readout) LO CIRCUITS (MAIN LOOP)
The applied PLL reference frequency signal is used for the
phase comparison of oscillating signal from the VCO-B
(Q501, 521, 551, 571). The resulting signal of phase
comparison is converted into the lock voltage which controls
the oscillation frequency of VCO-B (Q501, 521, 551, 571),
by being passed through the passive loop filter.
The output signals of the VCO-B (Q501, 521, 551, 571) are
buffer-amplified by Q601, filtered by the BPF, and amplified
by IC620, then filtered by the LPF for harmonic removal. The
filtered VCO output signals are passed through the BPF and
LO mute switch (Q661, D661, 662), then applied to the RF
UNIT as the 1st RX LO (for Sub readout) signals.
A portion of VCO output signals from the LPF are fed back
to the PLL (IC681) for the phase-locked loop.
VCOs (VCO-B)
Q501, Q521, Q551 and Q571 compose four oscillators,
and each VCO generates the 1st RX LO signals. These
VCO employ high "Q" components as resonator (L502, 522,
552, 572) for high C/N characteristic and wide oscillation
frequency range.
The table below shows the oscillation frequency range of
VCO-B and the RX frequency range.
Composed
by RX Frequency range
Oscillation frequency range
(1st LO)
Q571 0.03–7.999999 MHz 64.485–72.454999 MHz
Q551 8–19.999999 MHz 72.455–84.454999 MHz
Q521 20–44.999999 MHz 84.455–109.454999 MHz
Q501 45–60 MHz 109.455–124.455 MHz
1ST RX (Sub readout) LO CIRCUITS (SUB LOOP)
The 32 MHz reference signal from the reference frequency
oscillator circuit is amplified to the C-MOS level by Q403,
and applied to the DDS (IC403) as the reference clock
signal.
The DDS (IC403) generates the DDS reference frequency
signal by using the reference clock signal. The DDS
reference frequency signal is converted its waveform by
the D/A converter (R401–424), filtered by FI401 to remove
unwanted components, and amplified to C-MOS level by
IC402, then applied to the phase comparator of DDS (IC403).
The applied DDS reference frequency signal is used for the
phase comparison of oscillating signal from the SUB LOOP
VCO (Q451). The resulting signal of phase comparison is
converted into the lock voltage which controls the oscillation
frequency of SUB LOOP VCO (Q451), by being passed
through the passive loop filter.
The output signal of SUB LOOP VCO (Q451) is amplified by
the buffer (Q452), and applied to the PLL IC (IC681) as the
PLL reference frequency signal.
A portion of sub loop VCO (Q451) is applied to the phase
comparator of DDS (IC403) via the splitter (R459–461) and
AMP (Q402), for the phase-locked loop.
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3 - 8
FRONT
POWER SW
DC-IN
13.8V
FRONT
CPU
DC-DC
+3.3V
+1.2V
-8V
+3.3V
+1.2V
+13.8V
LOGIC
CIRCUITS
+8V
REG
+5V
REG
H3.3V
REG
SW
+8V
+5V
+13.8V
H3.3V
ANALOG
CIRCUITS
+3.3V
+1.8V
REG
+1.8V
“PWRK ”
H13.8V
“PWRS”
-8V
+5V
REG
+5V
3-4 VOLTAGE BLOCK DIAGRAM
Voltage from the power supply is routed to the whole of the transceiver via regulators and switches.
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3-5 CPU PORT ALLOCATIONS
Pin
No.
Line
Name Description I/O
5–20 H8_A0–
H8_A13 DSP address bus. O
21 UNLKA PLL unlock detect signal input for VCO-A.
H=Unlock detected. I
22 UNLKB PLL unlock detect signal input for VCO-B.
H=Unlock detected. I
23 ECK EEPRROM (HN58X2464TI) clock. O
24 EDT EEPRROM (HN58X2464TI) data. I/O
26 USCK USB HUB (USB2502) clock. O
27 USDA USB HUB (USB2502) data. O
28 UPWS USB HUB (USB2502) power control.
H=USB power ON. O
29 VBUS
VBUS connection detect for USB HUB
(USB2502).
H=USB connection detected.
I
30 RTKI RTTY keying input.
H="Space" input. I
31 TRVI Transverter input (from [ACC2]).
L=A transverter is connected. I
33 SDAT Scope DDS/PLL/DSP data. O
34 SST2 Scope PLL(ADF4630-8) strobe. O
35 EXRL1 External SEND reray output.
H=Relay ON O
36 EXRL2 External SEND reray output.
H=Relay ON O
37 H8_
CS6#
Dual-port SRAM chip select signal.
L=Selected. O
38 H8_
CS7#
Expander chip select signal.
L=Selected. O
42 PCK/
CON0 DDS clock. O
43 PDAT/
CON1 DDS data. O
44 CON2 DDS mode control. O
45 PSL PLL strobe. O
46 METV External meter voltage.
(PWM, 7800 Hz, 12 bit resolution) O
47 PST PLL strobe output. O
48 ESTA External tuner "START" signal output.
L=Tuning start. O
49 EKEY External tuner "KEY" signal input.
L=While tuning/tune NG. I
51 MCK Scope PLL clock. O
52 MDAT Scope PLL data. O
53 TCON External tuner conection detect. I
54 CTXD CI-V (UART) output. O
55 CRXD/
CBSY
CI-V (UART) input/CI-V bus busy input.
L=Data "1" /Busy. I
56 DSPCK DSP clock. O
57 DSPR DSP data. O
59 SST1 Chip select signal for scope DDS (AD9834).
L=Selected. O
60 SPS0 Scope DDS (AD9834) frequency register
shift signal. O
61 SCK Scope DDS/PLL/DSP clock. O
63-
80
H8_D0-
H8_D15 DSP data bus. I/O
81 RTD DSP RTTY/BPSK/QPSK (H) decode data. I
82 TND QPSK (L) decode data. I
Pin
No.
Line
Name Description I/O
83 NSQ Input noise pulse. I
84 H8_
WAIT# Bus control "Wait" signal. I
85 TRAS SEND signal. O
87 H8_
LWR#
(Bus control) "L" write signal.
L=While writing. O
88 H8_
HWR#
(Bus control) "H" write signal.
L=While writing. O
89 H8_
RD#
(Bus control) Read signal.
L=While reading. O
90 H8_AS# (Bus control) Adress strobe. O
94 SENI PTT/ACC SEND signal.
H=While transmitting. I
104 CTFL CW TX status. I
105 RXS RX circuits power ON.
L=While receiving. O
106 TXS TX circuits power ON.
L=While transmitting. O
107 SQS Squelch signal For [ACC1].
H=While the squelch is open. O
108 USQLS For USB audio squelch (for RX AF mute).
L=While the squelch is open. O
109 SQLS Squelch signal (for RX AF mute).
L=While the squelch is open. O
113 FORL Forward wave detect voltage. (A/D) I
114 REFL Reflected wave detect voltage. (A/D) I
115 ALCL ALC meter voltage input. (A/D) I
116 IDL Drive AMP current (ID) detect voltage. (A/D) I
117 VDL Drive AMP voltage (VD). (A/D) I
118 THML Temperature detect voltage from the
thermal sensor on the PA UNIT. (A/D) I
119 SKYS Straight key/electronic keyer input. (A/D)
L=Key down. I
120 AVXL AF signals peak level detect. (A/D) I
121 DX1 TX/RX DSP data. I
122 SHSK0 Hand shake signal for Scope DSP.
H=Data output enable. I
123 SHSK1 Firm-up command for Scope DSP. I
124 DX1S Scope DSP data. I
125 UNLKS Scope PLL (ADF4630) unlock detect signal.
L=Unlock detected. I
126 THRI Internal tuner through signal.
H=Tuner through. I
133 LTXD Data output (UART) for the communication
with front CPU. O
134 LRXD Data input (UART) for the communication
with front CPU. I
135 DSKY DSP CW/RTTY keying signal.
L=Key down/space. O
137 PWRS Transceiver power ON/OFF control.
H=Power ON. O
140 IKEY Internal tuner "KEY" input (UART).
L=Tuner ON. I
142 ISTA Internal tuner "START" signal (UART). O
• MAIN CPU (LOGIC UNIT: IC604)
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Pin
No.
Line
Name Description I/O
1 CNTV TFT contrast control. (D/A)
(1–2.3 V) O
2 PWRD POWER LED control.
(0 V=Light OFF, 3.3 V=Light ON.) O
3 LDAT Expander (BU2099) data. O
4 LST Expander (BU2099) strobe. O
5 RTCCK Expander (BU2099) clock. O
8 RTCCE Clock IC (RX-4581) chip enable. O
9 MOND [MONITOR] LED control signal. O
16 RTCIRQ Clock IC (RX-4581) interlude control. I
19 RSB RIT dial (24x4 pulses) phase-B input. I
20 RSA RIT dial (24x4 pulses) phase-A input. I
21 MSB Main dial (250x4 pulses) phase-B input. I
22 MSA Main dial (250x4 pulses) phase-A input. I
23 TMD Timer LED control.
H=Light ON. O
24 LEDV LED brightness control. (PWM, 600 Hz) O
25 BKLS LCD backlight ON/OFF.
H=Backlight ON. O
26 CFLV CFL backlight brightness control. (PWM, 600
Hz) O
28 PHNI Headphone connection detect.
H=Connection detected. I
29 DTXD Falsh read data. O
30 DRXD Flash write data. I
31 SLOS Flash write clock.
H=While writing. O
32 DBP1 Flash write "BUSY." O
33 LTXD Data output (UART) for the communication
with main CPU. O
34 LRXD Data input (UART) for the communication with
main CPU. I
35 DOTK Ele-key input. (Dot) I
36 DSHK Ele-key input. (Dash) I
37 SQSS Squelch signal to the [MICROPHONE JACK].
H=Squelch open. O
38 RTCDT Clock IC (RX-4581) data. I/O
40 TRAK [TRANSMIT] input. (Pull-up) I
41 F1K [F-1] input. (Pull-up) I
42 F2K [F-2] input. (Pull-up) I
43 F3K [F-3] input. (Pull-up) I
44 LOE Expander (BU2099) output enable. O
45 F4K [F-4] input. (Pull-up) I
46 F5K [F-5] input. (Pull-up) I
47 F6K [F-6] input. (Pull-up) I
49 SSBK [SSB] input. (Pull-up) I
50 CWK [CW] input. (Pull-up) I
51 RTYK [RTTY/PSK] input. (Pull-up) I
52 AMK [AM/FM] input. (Pull-up) I
53 FILK [FILTER] input. (Pull-up) I
55 EXTK [EXIT/SET] input. (Pull-up) I
56 PLYK [PLAY key input. (Pull-up) I
57 RECK [REC] input. (Pull-up) I
58 XFCK [XFC] input. (Pull-up) I
65 MPRK [MP-R] input. (Pull-up) I
66 MWK [MW] input. (Pull-up) I
67 UPK [ ▲] input. (Pull-up) I
• FRONT CPU (LOGIC UNIT: IC101)
Pin
No.
Line
Name Description I/O
68 DWK [ ▼] input. (Pull-up) I
69 MPWK [MP-W] input. (Pull-up) I
70 VMK [V/M] input. (Pull-up) I
71 ATK [AUTO TUNE] input. (Pull-up) I
72 TSK [TS] input. (Pull-up) I
73 PWRK [POWER] input. (Pull-up) I
76 FPWRS Analog circuit control signal.
H=Transceiver power ON. I/O
83,
84
PB2B,
PB2A Input ports for [PBT2] (outer control). I
85,
86
PB1B,
PB1A Input ports for [PBT1] (inner control). I
87 LG_RES Logic circuits reset signal.
H=Reset. O
88 LG_
PWR
Logic circuits power control signal.
H=Transceiver power ON. O
89 MUDL [MIC GAIN] input. (A/D) I
90 AS4 Voltage from the analog SW (CD4501). (A/D)
(0–3.3 V) I
91 AS3 Voltage from the analog SW (CD4501). (A/D)
(0–3.3 V) I
93 AS1 Voltage from the analog SW (CD4501). (A/D)
(0–3.3 V) I
98 ASL2 Analog SW (CD4501) control signal. O
99 ASL1 Analog SW (CD4501) control signal. O
100 ASL0 Analog SW (CD4501) control signal. O
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4 - 1
SECTION 4
.
ADJUSTMENT PROCEDURE
EQUIPMENT GRADE AND RANGE EQUIPMENT GRADE AND RANGE
Short plug Modified 3.5 mm (1/8’’) monoral plug
(See the illust on the page 4-17)
Audio generator
(AG)
Frequency range : 300–3000 Hz
Output level : 1–500 mV
RF voltmeter
(50 Ω terminated)
Measuring range : 20–200 mV
Frequency range : 0.1–50 MHz AC Millivoltmeter Measuring range : 10 mV to 10 V
RF power meter
(50 Ω terminated)
Measuring range : 5–120 W
Frequency range : 0.1–50 MHz
SWR : Less than 1.2 : 1
Digital multimeter
Measuring range : 0–10 V (Voltage)
1–30 A (Current)
Input impedance : More than 50 kΩ
Frequency counter
Frequency range : 0.1–100 MHz
Frequency accuracy : ±1 ppm or better
Input level : Less than 1 mW
External speaker Input impedance : 8 Ω
Capacity : More than 2 W
Standard signal
generator (SSG)
Frequency range : 0.1–100 MHz
Output level : 0.1 mV to 32 mV
(–127 to –17 dBm)
Spectrum Analyzer Frequency range : At least 90 MHz
Bandwidth : 100 kHz
Dummy Loads
Impedance : 50
Ω/120 W
and
100 Ω/120 W
¤ REQUIRED EQUIPMENTS
4-1 PREPARATION
¤ REMOVING COVERS
Some adjustments require removal the covers to expose PCB.
CAUTION: Turn the power OFF and disconnect the
DC power cable from the transceiver before per-
forming any work on the transceiver. Otherwise,
there is danger of electric shock and/or equipment
damage.
qRemove the two screws from the carrying handle
and remove the handle from the transceiver.
wRemove the 6 screws from the top of the trans-
ceiver and the 4 screws from the sides, then lift up
the top cover.
eTurn the transceiver upside-down.
CAUTION: NEVER HOLD THE MAIN DIAL OR
ANY OTHER KNOBS when the transceiver is
being turned upside down. This may damage the
transceiver.
rRemove 6 screws from the bottom, then lift up the
bottom cover.
tRemove the 11 screws, and disconnect the speaker
cable, then remove the top shielding plate. <fig.1>
yRemove the 6 screws, then remove the bottom
shielding plate. <fig.2>
Top shielding plate Bottom shielding plate
Speaker cable
Carrying handle
Top cover
Bottom cover
PA shielding
plate
<fig.1> <fig.2>
CAUTION!:
SAVE the originally programmed contents (Memory channel contents, set mode settings, etc.) into the USB-Memory
before starting adjustment. When all adjustments are completed, these contents in the transceiver will be cleared.
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