ICP DAS USA PIO-D144 Series User manual

Version: 2.1 Date:1999/10 Page 1
PIO-D144
User’s Manual
Warranty
All products manufactured by ICP DAS are warranted
against defective materials for a period of one year from the
date of delivery to the original purchaser.
Warning
ICP DAS assume no liability for damages consequent to
the use of this product. ICP DAS reserves the right to change
this manual at any time without notice. The information
furnished by ICP DAS is believed to be accurate and reliable.
However, no responsibility is assumed by ICP DAS for its use,
nor for any infringements of patents or other rights of third
parties resulting from its use.
Copyright
Copyright © 1999 by ICP DAS. All rights are reserved.
Trademark
The names used for identification only maybe registered
trademarks of their respective companies.
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PIO-D144 User’s Manual
Page 2 Version: 2.1 Date: 1999/10
Tables of Contents
1. INTRODUCTION......................................................................................................................... 3
2. HARDWARE CONFIGURATION............................................................................................... 4
2.1 BOARD LAYOUT............................................................................................................................ 4
2.2 I/O PORT LOCATION.................................................................................................................... 5
2.3 ENABLE I/O OPERATION .............................................................................................................. 5
2.4 D/I/O ARCHITECTURE ................................................................................................................. 6
2.5 INTERRUPT OPERATION ............................................................................................................... 7
2.6 DAUGHTER BOARDS .................................................................................................................. 12
2.7 PIN ASSIGNMENT....................................................................................................................... 18
3. I/O CONTROL REGISTER....................................................................................................... 20
3.1 HOW TO FIND THE I/O ADDRESS ................................................................................................. 20
3.1.1 PIO_DriverInit............................................................................................................... 22
3.1.2 PIO_GetConfigAddressSpace........................................................................................ 23
3.1.3 Show_PIO_PISO ........................................................................................................... 24
3.2 THE ASSIGNMENT OF I/O ADDRESS............................................................................................ 25
3.3 THE I/O ADDRESS MAP ............................................................................................................. 27
3.3.1 RESET\ Control Register............................................................................................... 27
3.3.2 AUX Control Register.................................................................................................... 28
3.3.3 AUX data Register.......................................................................................................... 28
3.3.4 INT Mask Control Register.............................................................................................28
3.3.5 Aux Status Register........................................................................................................29
3.3.6 Interrupt Polarity Control Register ............................................................................... 29
3.3.7 Read/Write 8-bit data Register ...................................................................................... 30
3.3.8 Active I/O Port Control Register.................................................................................... 30
3.3.9 I/O Selection Control Register....................................................................................... 31
4. DEMO PROGRAM..................................................................................................................... 32
4.1 PIO-D144.H............................................................................................................................ 33
4.2 DEMO1: USE D/O OF CN1 ....................................................................................................... 34
4.3 DEMO2: USE D/O OF CN1~CN6.............................................................................................. 36
4.4 DEMO3: INTERRUPT DEMO1...................................................................................................... 38
4.5 DEMO4: INTERRUPT DEMO2...................................................................................................... 40
4.6 DEMO5: INTERRUPT DEMO3...................................................................................................... 42
4.7 DEMO 6: OUTPORT OF CN1-CN6............................................................................................ 44
4.8 DEMO10: FIND CARD NUMBER ................................................................................................. 47
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PIO-D144 User’s Manual
Version: 2.1 Date: 1999/10 Page 3
1. Introduction
The PIO-D144 consists of one DB-37 & five 50-pin flat-cable connectors.
There are three 8-bit port, PA, PB & PC in each connector. Every port consists of 8-
bit programmable D/I/O. So the PIO-D144 can provide 144 channels of TTL-
compatible D/I/O.
1.1 specifications
•PC compatible PCI bus
•One DB-37 connector and five 50-pin flat-cable connectors
•Each port consists of three 8-bit port, PA, PB & PC in every connector
•Each port can be programmed as D/I or D/O independently.
•Each board = 6 connector = 6×3 port = 6×3×8 bit =144 bit
•4 interrupt sources: PC0,PC1,PC2,PC3
•All signals are TTL compatible
•Operating Temperature: 0°C to 60°C
•Storage Temperature: -20°C to 80°C
•Humility: 0 to 90% non-condensing
•Dimension: 180mm X 105mm
•Power Consumption: +5V @ 1100mA
1.2 Product Check List
In addition to this manual, the package includes the following items:
•PIO-D144 card
•Demo program diskette
Attention !
If any of this items is missing or damaged, contact the dealer
from whom you purchased the product. Save the shipping
materials and carton in case you want to ship or store the
product in the future.
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PIO-D144 User’s Manual
Page 4 Version: 2.1 Date: 1999/10
2. Hardware configuration
2.1 Board Layout
PCI BUS
PIO-D144
CN1
DB-37 PIN
CN1_PA
CN1_PC
CN1_PB
CN3
50-PIN
CN3_PA
CN3_PC
CN3_PB
CN6
50-PIN
CN6_PA
CN6_PC
CN6_PB
CN4
50-PIN
CN4_PA
CN4_PC
CN4_PB
CN5
50-PIN
CN5_PA
CN5_PC
CN5_PB
CN2
50-PIN
CN2_PA
CN2_PC
CN2_PB
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PIO-D144 User’s Manual
Version: 2.1 Date: 1999/10 Page 5
2.2 I/O Port Location
There are eighteen 8-bit I/O ports in the PIO-D144. Every I/O port can be
programmed as D/I or D/O port. When the PC is first power-on, all eighteen ports are
used as D/I port. The I/O port location is given as following:
Connector of PIO-D144 PA0 to PA7 PB0 to PB7 PC0 to PC7
CN1 CN1_PA CN1_PB CN1_PC
CN2 CN2_PA CN2_PB CN2_PC
CN3 CN3_PA CN3_PB CN3_PC
CN4 CN4_PA CN4_PB CN4_PC
CN5 CN5_PA CN5_PB CN5_PC
CN6 CN6_PA CN6_PB CN6_PC
Refer to Sec. 2.1 for board layout & I/O port location.
Note: PC0, PC1, PC2, PC3 of CN1 can be used as interrupt signal source. Refer
to Sec. 2.5 for more information.
2.3 Enable I/O Operation
When the PC is first power-on, all operation of D/I/O port are disable. The
enable/disable of D/I/O is controlled by the RESET\ signal. Refer to Sec. 3.3.1 for
more information about RESET\ signal. The power-on states are given as following:
•All D/I/O operations are disable
•All eighteen D/I/O ports are configured as D/I port
•All D/O latch register are undefined.(refer to Sec. 2.4)
The user has to perform some initialization before using these D/I/O. The
recommended steps are given as following:
Step 1: Make sure which ports are D/O ports.
Step 2: Enable all D/I/O operation.(refer to Sec. 3.3.1).
Step 3: Select the active port (refer to Sec. 3.3.8).
Step 4: Send initial-value to the D/O latch register of this active port.
(Refer to Sec. 2.4 & Sec. 3.3.7)
Step 5: Repeat Step3 & Step4 for all D/O ports
Step 6: Configure all eighteen D/I/O ports to their expected D/I or D/O state.
(Refer to Sec. 3.3.9)
Refer to DEMO1.C for demo program.
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PIO-D144 User’s Manual
Page 6 Version: 2.1 Date: 1999/10
2.4 D/I/O Architecture
•The RESET\ is in Low-state !all D/I/O operation is disable
•The RESET\ is in High-state !all D/I/O operation is enable.
•If D/I/O is configured as D/I port !D/I=external input signal
•If D/I/O is configured as D/O port !D/I = read back of D/O
•If D/I/O is configured as D/I port !send to D/O will change the D/O latch
register only. The D/I & external input signal will not change.
disable\
input Latch
Clock input
D/O latch CKT
RESET\ (Sec. 3.3.1)
Data
(Sec. 3.3.7)
I/O select (Sec. 3.3.9)
D/I/O
disable
Buffer input
Clock input
D/I buffer CKT
Data
(Sec. 3.3.7)
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PIO-D144 User’s Manual
Version: 2.1 Date: 1999/10 Page 7
2.5 Interrupt Operation
The PC0, PC1, PC2, PC3 of CN1_PC can be used as interrupt signal source. Refer
to Sec. 2.1 for PC0/1/2/3 location. The interrupt of PIO-D144 is level-trigger &
Active_High. The interrupt signal can be inverted or non-inverted
programmable. The procedures of programming are given as follows:
1. make sure the initial level is High or Low
2. if the initial state is High !select the inverted signal (Section. 3.3.6)
3. if the initial state is Low !select the non-inverted signal (Section. 3.3.6)
4. enable the INT function (Section. 3.3.4)
5. If the interrupt signal is active !program will transfer into the interrupt
service routine !if INT signal is High now !
!!
!select the inverted input
!if INT signal is Low now !
!!
!select the non-inverted input
Refer to DEMO3.C & DEMO4.C for single interrupt source. Refer to
DEMO5.C for four interrupt sources.
If only one interrupt signal source is used, the interrupt service routine does not
have to identify the interrupt source. (Refer to DEMO3.C & DEMO4.C)
If there are more than one interrupt source, the interrupt service routine has to
identify the active signals as following: (refer to DEMO5.C)
1. Read the new status of the interrupt signal source
2. Compare the new status with the old status to identify the active signals
3. If PC0 is active, service CN1_PC0 & non-inverter/inverted the CN1_PC0 signal
4. If PC1 is active, service CN1_PC1 & non-inverted/inverted the CN1_PC1 signal
5. If PC2 is active, service CN1_PC2 & non-inverted/inverted the CN1_PC2 signal
6. If PC3 is active, service CN1_PC3 & non-inverted/inverted the CN1_PC3 signal
7. Save the new status to old status
Limitation: if the interrupt signal is too short, the new status may be as same as
old status. So the interrupt signal must be hold-active until the interrupt service
routine is executed. This hold time is different for different O.S. The hold time
can be as short as micro-second or as long as second. In general, 20ms is enough
for all O.S.
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PIO-D144 User’s Manual
Page 8 Version: 2.1 Date: 1999/10
Example 1: assume initial level=Low, PC0 is used as interrupt source:
Refer to DEMO3.C for source code.
Iniaial_sub()
{ now_int_state=0
_outpd(wBase+0x2a,0)
/*(select the non-inverted signal)*/
ISR_sub()
{
If (now_int_state==0) /* old state=low !change to high now */
{
now_int_state=1; /* now int_signal is High */
/*** application codes are given here ***/
_outpd(wBase+0x2a,1); /* select the inverted signal */
}
else /* old state=high!change to low now */
{
now_int_state=0; /* now int_signal is Low */
/*** application codes are given here ***/
_outpd(wBase+0x2a,0); /* select the non-inverted signal */
}
if (wIrq>=8) outp(A2_8259,0x20); /* EOI */
outp(A1_8259,0x20); /* EOI */
}
Initial=Low
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PIO-D144 User’s Manual
Version: 2.1 Date: 1999/10 Page 9
Example 2: assume initial level=High, PC0 is used as interrupt source:
Refer to DEMO4.C for source code.
Initial=High
Iniaial_sub()
{ now_int_state=1
_outpd(wBase+0x2a,1)
/*(select the inverted signal)*/
Inverted=Low
ISR_sub()
{
If (now_int_state==0) /* old state=low !change to high now */
{
now_int_state=1; /* now int_signal is High */
/*** application codes are given here ***/
_outpd(wBase+0x2a,1); /* select the inverted signal */
}
else /* old state=high!change to low now */
{
now_int_state=0; /* now int_signal is Low */
/*** application codes are given here ***/
_outpd(wBase+0x2a,0); /* select the non-inverted signal */
}
if (wIrq>=8) outp(A2_8259,0x20); /* EOI */
outp(A1_8259,0x20); /* EOI */
}
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PIO-D144 User’s Manual
Page 10 Version: 2.1 Date: 1999/10
Example 3: assume CN1_PC0 is initial Low, active High,
CN1_PC1 is initial High, active Low
CN1_PC2 is initial Low, active High
CN1_PC3 is initial High, active Low
As follows:
Refer to DEMO5.C for source program. All these four falling-edge & rising-edge
can be detected by DEMO5.C.
Note: when the interrupt is active, the user program has to identify the active
signals. These signals maybe active at the same time. So the interrupt
service routine has to service all active signals at the same time.
CN1_PC1
CN1_PC0
CN1_PC2
CN1_PC3
CN1_PC0 &
CN1_PC1 are
active at the same
time.
CN1_PC2 &
CN1_PC3 are
active at the same
time.
CN1_PC0 &
CN1_PC1 are
return to normal
at the same time.
CN1_PC2 &
CN1_PC3 are
return to normal
at the same time.
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PIO-D144 User’s Manual
Version: 2.1 Date: 1999/10 Page 11
void interrupt irq_service()
{
char cc;
int_num++;
/* 1. Read interrupt signal status */
new_int_state=inp(wBase+0x07)&0xff;
/* 2. Find the active signal */
int_c=new_int_state ^ now_int_state;
/* 3. IF PC0 is active */
if ((int_c&0x01) != 0)
{
cc=new_int_state&0x01;
if (cc !=0) CNT_H1++; else CNT_L1++;
invert=invert ^ 1;
}
/* 4. IF PC1 is active */
if ((int_c&0x02) != 0)
{
cc=new_int_state&0x02;
if (cc !=0) CNT_H2++; else CNT_L2++;
invert=invert ^ 2;
}
/* 5. IF PC2 is active */
if ((int_c&0x04) != 0)
{
cc=new_int_state&0x04;
if (cc !=0) CNT_H3++; else CNT_L3++;
invert=invert ^ 4;
}
/* 6. IF PC3 is active */
if ((int_c&0x08) != 0)
{
cc=new_int_state&0x08;
if (cc !=0) CNT_H4++; else CNT_L4++;
invert=invert ^ 8;
}
now_int_state=new_int_state;
outp(wBase+0x2a,invert);
if (wIrq>=8) outp(A2_8259,0x20);
outp(A1_8259,0x20);
}
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PIO-D144 User’s Manual
Page 12 Version: 2.1 Date: 1999/10
37-PIN cable
37pin cable
2.6 Daughter Boards
2.6.1 DB-37
The DB-37 is a general purpose daughter board for D-sub 37 pins. It is designed
for easy wire connection.
2.6.2 DN-37 & DN-50
The DN-37 is a general purpose daughter board for DB-37 with DIN-Rail
Mounting. The DN-50 is designed for 50-pin flat-cable header. They are designed for
easy wire connection. Both have Din-Rail mounting.
2.6.3 DB-8125
The DB-8125 is a general purpose screw terminal board. It is designed for easy
wire connection. There are one DB-37 & two 20-pin flat-cable header in the DB-8125.
DB-8125
(for DB-37 or
20-
p
in flat-cable header
)
DN-37
37-PIN cable DB-37
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PIO-D144 User’s Manual
Version: 2.1 Date: 1999/10 Page 13
2.6.4 ADP-37/PCI & ADP-50/PCI
The ADP-37/PCI & ADP-50/PCI are extender for 50-pin header. One side of
ADP-37/PCI & ADP-50/PCI can be connected to a 50-pin header. The other side can
be mounted on the PC chassis as following:
ADP-37/PCI: 50-pin header to DB-37 extender.
ADP-50/PCI: 50-pin header to 50-pin header extender.
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PIO-D144 User’s Manual
Page 14 Version: 2.1 Date: 1999/10
2.6.5 DB-24P, DB-24PD Isolated Input Board
The DB-24P is a 24-channel isolated digital input daughter board. The optically
isolated inputs of the DB-24P consists of a bi-directional optocoupler with a resistor
for current sensing. You can use the DB-24P to sense DC signal from TTL levels up
to 24V or use the DB-24P to sense a wide range of AC signals. You can use this
board to isolated the computer from large common-mode voltage, ground loops and
transient voltage spike that often occur in industrial environments.
DB-24P DB-24PD
50-pin flat-cable header Yes Yes
D-sub 37-pin header No Yes
Other specifications Same
V
+
V
-
PIO-D144
DB-24P
Opto-Isolated
PIO-D144
50-Pin cable
AC or DC Signal
0V to 24V
CN2 CN6
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PIO-D144 User’s Manual
Version: 2.1 Date: 1999/10 Page 15
2.6.6 DB-24R, DB-24RD Relay Board
The DB-24R, 24-channel relay output board, consists of 24 form C relays for
efficient switch of load by programmed control. The relay are energized by apply
12V/24V voltage signal to the appropriated relay channel on the 50-pin flat
connector. There are 24 enunciator LED’s for each relay, light when their associated
relay is activated.
DB-24R DB-24RD
50-pin flat-cable header Yes Yes
D-sub 37-pin header No Yes
Other specifications Same
DB-24R, DB-24RD 24 ×Relay (120V, 0.5A)
DB-24PR,DB-24PRD 24 ×Power Relay (250V, 5A)
DB-24POR 24 ×Photo MOS Relay (350V, 01.A)
DB-24SSR 24 ×SSR (250VAC, 4A)
DB-24C 24 ×O.C. (30V, 100 mA)
DB-16P8R 16 ×Relay (120V, 0.5A) + 8 ×isolated input
DB-24R
PIO-D144
50-Pin cable
Normal Open
Normal Close
Com.
Note:
Channel: 24 From C Relay
Relay: Switching up to 0.5A at 110ACV
or 1A at 24DCV.
From C Relay
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PIO-D144 User’s Manual
Page 16 Version: 2.1 Date: 1999/10
2.6.7 DB-24PR, DB-24POR, DB-24C
DB-24PR 24 ×power relay, 5A/250V
DB-24POR 24 ×Photo MOS relay, 0.1A/350VAC
DB-24C 24 ×open collector, 100mA per channel, 30V max.
The DB-24PR, 24-channel power relay output board, consists of 8 form C and
16 form A electromechanical relays for efficient switching of load programmed
control. The contact of each relay can control a 5A load at 250ACV/30VDCV. The
relay is energized by applying a 5 voltage signal to the appropriate relay channel on
the 20-pin flat cable connector(just used 16 relays) or 50-pin flat cable
connector.(OPTO-22 compatible, for DIO-24 series). Twenty - four enunciator LEDs,
one for each relay, light when their associated relay is activated. To avoid overloading
your PC’s power supply , this board needs a +12VDC or +24VDC external power
supply.
DB-24PR
PIO-D144
50-Pin cable
Normal Open
COM.
Note: 50-Pin connector(OPTO-22 compatible), for DIO-24, DIO-48, DIO-144,
PCI-D144, PIO-D144, PIO-D96, PIO-D56, PIO-D48, PIO-D24
20-Pin connector for 16 channel digital output, A-82X, A-62X, DIO-64, ISO-DA16/DA8
Channel: 16 Form A Relay , 8 Form C Relay.
Relay: switching up to 5A at 110ACV / 5A at 30DCV.
From A Relay
50-Pin cable
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PIO-D144 User’s Manual
Version: 2.1 Date: 1999/10 Page 17
2.6.8 Daughter Board Comparison Table
20-pin flat-cable 50-pin flat-cable D-sub 37-pin
DB-37NoNoYes
DN-37 No No Yes
ADP-37/PCI No Yes Yes
ADP-50/PCI No Yes No
DB-24P No Yes No
DB-24PD No Yes Yes
DB-16P8R No Yes Yes
DB-24R No Yes No
DB-24RD No Yes Yes
DB-24C Yes Yes Yes
DB-24PR Yes Yes No
Db-24PRD No Yes Yes
DB-24POR Yes Yes Yes
DB-24SSR No Yes Yes
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PIO-D144 User’s Manual
Page 18 Version: 2.1 Date: 1999/10
2.7 Pin Assignment
CN1: 37-PIN of D-type female connector.
Pin Number Description Pin Number Description
1 N. C. 20 VCC
2 N. C. 21 GND
3 PB7 22 PC7
4 PB6 23 PC6
5 PB5 24 PC5
6 PB4 25 PC4
7 PB3 26 PC3
8 PB2 27 PC2
9 PB1 28 PC1
10 PB0 29 PC0
11 GND 30 PA7
12 N.C. 31 PA6
13 GND 32 PA5
14 N.C. 33 PA4
15 GND 34 PA3
16 N.C. 35 PA2
17 GND 36 PA1
18 VCC 37 PA0
19 GND XXXXXXX This pin not available
All signals are TTL compatible.
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PIO-D144 User’s Manual
Version: 2.1 Date: 1999/10 Page 19
CN2/CN3/CN4/CN5/CN6: 50-PIN in of flat-cable connector
Pin Number Description Pin Number Description
1 PC7 2 GND
3 PC6 4 GND
5 PC5 6 GND
7 PC4 8 GND
9 PC3 10 GND
11 PC2 12 GND
13 PC1 14 GND
15 PC0 16 GND
17 PB7 18 GND
19 PB6 20 GND
21 PB5 22 GND
23 PB4 24 GND
25 PB3 26 GND
27 PB2 28 GND
29 PB1 30 GND
31 PB0 32 GND
33 PA7 34 GND
35 PA6 36 GND
37 PA5 38 GND
39 PA4 40 GND
41 PA3 42 GND
43 PA2 44 GND
45 PA1 46 GND
47 PA0 48 GND
49 VCC 50 GND
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PIO-D144 User’s Manual
Page 20 Version: 2.1 Date: 1999/10
3. I/O Control Register
3.1 How to Find the I/O Address
The plug&play BIOS will assign a proper I/O address to every PIO/PISO series
card in the power-on stage. The fixed IDs of PIO/PISO series card are given as
following:
•Vendor ID = E159
•Device ID = 0002
The sub IDs of PIO-D144are given as following:
•Sub-Vendor ID= 80
•Sub-Device ID= 01
•Sub-Aux ID = 00
We provide all necessary functions as following:
1. PIO_DriverInit(&wBoard, wSubVendor, wSubDevice, wSubAux)
2. PIO_GetConfigAddressSpace(wBoardNo,*wBase,*wIrq, *wSubVendor,
*wSubDevice, *wSubAux, *wSlotBus, *wSlotDevice)
3. Show_PIO_PISO(wSubVendor, wSubDevice, wSubAux)
All functions are defined in PIO.H. Refer to Chapter 4 for more information. The
important driver information is given as following:
1. Resource-allocated information:
•wBase : BASE address mapping in this PC
•wIrq: IRQ channel number allocated in this PC
2. PIO/PISO identification information:
•wSubVendor: subVendor ID of this board
•wSubDevice: subDevice ID of this board
•wSubAux: subAux ID of this board
3. PC’s physical slot information:
•wSlotBus: hardware slot ID1 in this PC’s slot position
•wSlotDevice: hardware slot ID2 in this PC’s slot position
The utility program, PIO_PISO.EXE, will detect & show all PIO/PISO cards
installed in this PC.
ГК Атлант Инжиниринг – официальный представитель вРФ иСНГ
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