Intel CH-486-33A User manual

CH-486-33A
User’s Manual

1st Edition, June 1991
The information contained in this manual is
subject to change without notice
__ _ _ _.___ ____________
IBM PC/XT/AT/PS-2 are registered trademarks of
International Business Machines Corporation.
AMI is a trademark of American Megatrends, inc.
486 is a trademark of Intel Corporation.
Other brand and product name or trademarks
and/or registered trademarks of respective companies.

Table Of Contents
1. Introduction
2. Hardware Description
21
I
System Description
22
-
Connector and Jumper Settings
23
I
DRAM Bank Configuration
24
-
SRAM Configuration
3 BIOS Setup
31
-
32
I
33
-
34
-
35
I
3-6
37
-
38
-
’ 1
I
I
BIOS Overview
Standard CMOS Setup
Advanced CMOS Setup
Advanced Chipset Setup
Auto Configuration with BIOS
Defaults.
Auto Configuration with Power-On
Defaults
Write To CMOS and Exit
Do Not Write To CMOS and Exit

1 htroduction
The CH-486.33A is a three-chip solution offering optional
performance for high-end 486.based AT systems. The
CH-486.33A is designed for INTEL 80486DX running 33 MHz
or INTEL 80486SX running for 20/25MHz combines three
major functions:
x
The 82C493 System Controller (sysc)
If
The 82C392 Data Buffer Contrdler (DBC)
tl
The 82C206 Integrated Peripheral Controller (IPC)
l-l. CH-486-33A Mainboard Specification
II
33 MHz INTEL 80486 DX CPU OR 20125 MHz INTEL
80486 SX CPU
ISA architecture
Copy-Back Direct-Mapped Cache with size of 64KB
or 256 KB selectable
Up to 32 MB of local high-speed page-mode DRAM
memory space
DRAM TYPE support 256K/i M/4MB
Control of two non-cacheable regions
Shadow RAM support
Optional Cacheable of shadow video BIOS
Turbo/slow speed selectable for hardware and
software controller
Introduction
1-1

WEITEK 4167 coprocessor socket on board
On board rechargeable battery back-up for CMOS
configuration and real-time dock
Optimized for OS/2, window/386, window 3.0, XENIX,
UNIX software operation
Baby AT size, with XT/AT mounting hole
l-2
lntroductlon

2. Hardware Description
2-l System Description
80486 Microprocessor
The 80486 is a high performance 32.bit microprocessor with
on-chip memory management, floating point and cache
memory units. It is binary compatible with members of the 86
architectural family. The 486 CPU contains all the features of
the 386 CPU with enhancements to increase performance.
On-chip Floating Point Control Unit
The operation of the 486 microprocessor’s on-chip floating
point control unit is exactly the same as the 387 math
coprocessor. Software written for the 387 math coprocessor will
run on the on-chip floating point unit without any
modification. It occupies I/O address range of
8OOOOOFOH-SOOOOOFFH and operates in parallel with the
arithmetic and logic unit and provides arithmetic instructions
for a variety of numeric data types.
On-chip Cache Memory
The 8KB on-chip cache is a 4-way set associative write-through
code and data cache memory. Individual pages can be
designated as cacheable or non-cacheable by software or
hardware. The cache can also be enabled and disabled by
software or hardware.
Hardware Description

4167 Floating-point Coprocessor
The WEITEK 4167 is a high-performance single-chip
floating-point coprocessor for 80486 microprocessor. It is
upwardly binary compatible with the WEITEK 3167
coprocessor.
The 4167 coprocessor is a memory-mapped peripheral that
communicates with the 80486 over the same address bus tklt
connects the main memory to CPU. The coprocessor will
respond to memory addresses COOOOOOO1: i through
CIFFFFFFH. Writing to this ;ddrcss space will cause the 4 107
to execute this
fractions
coprocessor to drive the and reading from it will cause the
data bus.
2-2 Connector and Jumper Settings
This chapter describes the CH-486.33A main bo;rrd’s jumpers
and connectors
The system layout are shown on the next purge.
Hardware Description

.
1
JPll
I I
WEITEK
82c4w
4167
1 DRAMBank
30
DRAMBank
I
J23
il
324
d
Wl
SW2
0
JP12
Hardware Description
2-3

SW1 :
Hardware Reset switch Connector
sw2:
Hardware Turbo Switch Connector
Jl
.
.
Keyboard Connector
JlO: External Battery Connector
Jll , J12: Power Connector
J23:
Keylock and Power LED Connector
J24: Speaker Connector
JP12:
Turbo LED Connector
2-4 Hardware Description

Jumper
1 Description 1 Setting
JPl
I
Monitor Type Selectable
n : Monochrome
I
JP2
JP4
I
CMOS power
1-2 : Clear CMOS RAM
2-3 : Backup CMOS RAM
1
JPS
CPU selectable
I
.
[Always 2-3 Short
1 -
1-2 : 487SX
(2-3
: 4860X
13Upen:4BSX
_
I
1
JP6
JP7
CPU selectable
CPU selectable
I
[Short : 486 OX, 487SX
J
Open : 486 SX
JP8
1 Cache $i28 Sdetctabl8 _-.--_-.-.-
Short : 256K
@pen : 64K
Jp9
JPlO
JPll
Cache size selectable
Cache size selectable
Short : 256K
IOpen : 64K
[Always Open
Short : 256K
IOpen : 64K
NOTE : 1. TItose enclosed in box ate Mainboard Default
2. This Mainbmud mly supput Intel C u Iater
stepping cfpracesscx.
Hardware Description 2-5

2-3. DRAM Bank Configuration
The CH-486.33A supports 2 banks of page mode local
memory, DRAM devices are either 256Kb, 1Mb or 4Mb large.
Total memory is between 1MB and 32MB. The following table
illustrates the configuration supported.
Bank 0 1 Bank 1
1 Total
256K
II
1MB
256K I256K 1 2MB
256K
1M
5MB
i8MB I
1 4M I
1 16MB I
I lfvl I 4M
I20MB
- -1
I 4M I lM
I2OMB
I
I 4M I
4M
1 32MB
I
* Use 80ns DRAM
2-6
Hardware Description

2-4 SRAM Configuration
The CH-486-33A has a non-pipeline mode with a 16 bytes line
size copy-back Direct-mapped cache, because this cache
controller design two-way interleave cache read/write, so only
support 64K or 256K secondary cache size.
The following table shows the TAG RAM size, cache RAM size
and cacheable main memory size supported by CH-486-33A.
Cache size (KB)
64K
TAG RAM size Cache Cacheable main
RAM size memory
8Kx 8bit U34
8K x 8bit 16MB
64K x lbit U33 u47 “U49
us1 - us5
256K 32K x 8bit U34 32K x 8bit 32MB
64K x 1 bit U33 u47 “U49
us1 - us5
Note : . If you waut to charge secortd Ier~el cache size, you
mrst change the SRA M arid TAG RAM size aud Jutqw
Setthg.
Hardware Description 2-7

3.BlOS SETUP
3-l. BIOS OVERVIEW
The SETUP program is used to configure the system. These
system options are stored in the CMOS. If the CMOS is good,
the system is configured with the values stored in the CMOS. If
the CMOS is bad, the system is configured with the default
values stored in the ROM file.
There are two (2) sets of BIOS values stored in the ROM file :
tl
The BIOS Setup default values
n
The Power-On default values
The BIOS Setup default values are the default values which are
supposed to give optimum performance for the system. They
are the best case default values.
The Power-On default values are the default values for the
table values for the system. They are the worst case default
values.
BIOS SETUP
3-l

There are two ways to enter the BIOS setup program
1. Whenever BIOS detects any equipment error or the CMOS
contents are not consistent with the equipment.
2. After the power on memory test, the screen will show:
Hit <DEL> If you want to run setup
Press the DEL key to get the following screen:
3-2
BIOS SETUP

- AMI BIOS SETUP UTILITIES
--I
(1990) American Megatrends Inc., All Rights Reserved
STANDARD CMOS SETUP
ADVANCED CMOS SETUP
ADVANCED CHIPSET SETUP
AUTO CONFIGURATION WITH BIOS DEFAULTS
AUTO CONFIGURATION WITH POWER-ON DEFAULTS
WRITE TO CMOS AND EXIT
DO NOT WRITE TO CMOS AND EXIT
.
__ _______ ___.__ ___ --
Standard CMOS Setup for changing Time, Date, Hard Disk Type, etc.
ESC:Exit I- 1 l -- : Sel
F2/F3:Color FlO:Save
& Exit
L
~~____ - ____~__
_-
_~___ _.__._ _______ _ ___~_
---___-
Explanation of keys:
FCC:
Exit to setup program
Arrow keys: Cursor movement
F2/ F3:
Change Color
FlO:
Save Setup values & &it to setup program
BIOS SETUP 3-3

The user is given a warning message before he is allowed to
change any of the setup parameters. The warning message is
shown as following:
-- ______- -- --__ _.._-____--_ -_ .- ---.- .-.
______________ __ ___ .-- __ -
BIOS SETUP PROGRAM -WARNING INFORMATION
Inc., All Rights Reserved
-_ . _ -_ _.
Improper Use of Setup may Cause Problems !!
If System Hangs, Reboot System and Enter Setup by pressing the < DEL > key
Do any of the following After Entering Setup
(i) Alter options to make system work
(ii) Load BIOS Setup Defaults
(iii) Load Power-On Defaults
Hit < ESC> to stop now, Any other key to Continue
Figure 3 : BIOS Setup Warning Message
Explanation of keys:
ESC
.
Exit to previous screen
Any* keys : Continue choose setup program
3-4 BIOS SETUP

3-2 STANDARD CMOS SETUP
This option is used to configure the following options:
Date: Month, Date and Year
Time: Hour, Minute and Second
Daylight Saving: Disabled or Enabled
Hard Disk C: and Hard Disk D: The user can choose
any of the standard hard disk types from 1 to 46 or he
can choose type 47 which is the user defineable type.
The user must enter the hard disk parameters if he
wants to choose the user-definable hard disk type
per drive, i.e., type 47 may be different for drive C: and
for drive D:.
Floppy drive A: and Floppy drive B: 360KB 5.25,
1.2MB 5.25, 720KB 3.5”, 1.44MB 3.5”, Not Installed
Primary Display: Monochrome, Color 40 x 25,
VGA/PGA/EGA, Color 80x25, Not Installed
Keyboard: Installed or Not Installed
BIOS SETUP 3-5

-
Date (mm/ date/ year): Wed, Jun 05 1991
Base memory: 640 KB
lime (hour/ min/ set): 15 : 35 : 50
Ext. memory: 7168 KB
Daylight saving
: Disabled Cyln Head
WPcom LZone Sect Size
Hard disk C: type : Not Installed
Hard disk D: type
: Not Installed
Floppy drive A
: 1.2 MB, 5.25”
Floppy drive B
: Not Installed
Primary display
: VGA/ PGA/ FGA
Key board
: Installed
BIOS SETUP PROGRAM-STANDARD CMOS SEI’UP
(C)1990 American Megatrends Inc., All Rights Reserved
Month:Jan,Feb,....Dec
Date :01,02,03....31
Year :1901,1902....2099
.-
ESC:Exit - 1 --• 1
Select F2/ F3: Color PU/ PD:Modify
1 SUN 1 MON 1 TUE
1 WED 1 THU
1 SAT
___________. _-_.-.--._- -.---
-__- - _ .-- -
3-6
BIOS SETUP

Note: Daylight Saving
The RTC has a built-in capability to automatically adjust the
time on the two daylight savings days of the year (*). If this is
desired, set the field to “Enable”.
Otherwise, set field to “Disabled”. Note that in general, nothing
will be immediately observable by setting the field to either
state.
.
Eg,
Daylight Savings.. ...... Enable
Daylight Savings..
.....
Disable
* On the lcrrt Sun&y @April” the time increments frm 1:59:59
am to 3:00:00 am On thelast Sunday in October, when the time
first reaches 1:59:59 am, it is rdled-barck to 1:OO:OO am
BIOS SETUP
3-7

3-3. ADVANCE CMOS SETUP
The ADVANCED CMOS SETUP option is used to set the
various system options for the user. The user can get various
options, some of which are listed below:
n
Weitek Processor
Ll
External Cache Memory
CI
Internal Cache Memory
II
Adaptor ROM Shadow
II
Shadow RAM
3-8 BIOS SETUP
.