inter
iSBC®
80/30
SINGLE BOARD COMPUTER
mabie Interrupt Controller, to the
I/O
line drivers as-
sociated with the 8255A Programmable Peripheral
Interface, and to the 8041A18741A Universal Pro-
grammable Interface, or may be routed as inputs to
the 8255A and 8041A18741A chips. The gate/trig-
ger inputs may be routed to
I/O
terminators associ-
ated with the 8255A
or
as output connections from
the 8255A. The third interval timer in the 8253 pro-
vides the programmable baud rate generator for the
iSSC
80/30
RS232C USART serial port.
In
utilizing
the iSSC 80/30, the systems designer simply config-
ures, via software, each timer independently to meet
system requirements.
Whenever a given time delay or count
is
needed,
software commands to the programmable timers/
event counters select the desired function. Seven
functions are available, as shown in Table'
2.
The
Table 2.
Programmable
Timer
Functions
Function
Operation
Interrupt on When terminal count
is
Terminal Count reached,
an
interrupt request
is
generated. This function
is
extremely useful for generation
of real-time clocks.
Programmable Output goes low upon receipt of
One-Shot
an
external trigger edge or
software command and returns
high when terminal count is
reached. This function
is
retriggerable.
Rate Divide by N counter. The output
Generator will go low for one input clock
cycle, and the period from one
low-going pulse to the next
is
N
times the input clock period.
Square-Wave Output will remain high until
Rate Generator one-half the count has been
completed, and go low for the
other half of the count.
Software Output remains high until
Triggered software loads count (N). N
Strobe , counts after count is loaded,
output goes low for one input
clock period.
Hardware Output goes low for one clock
Triggered period N counts after rising
Strobe edge
on
counter trigger input.
The counter
is
retriggerable.
Event Counter
On
a jumper selectable basis,
the clock input becomes
an
input from the external system.
CPU
may read the number of
events occurring after the
counting "window" has been
enabled or an interrupt may be
generated after N events occur
in
the system.
3-30
contents of each counter may
be
read at any time
during system operation with simple read operations
for event counting applications, and special com-
mands are included so that the contents of each
counter can
be
read
"on
the fly".
Interrupt Capability
The iSSC
80/30
provides vectoring for 12 interrupt
levels. Four of these levels are handled directly by
the interrupt
proceSSing
capability of the 8085A
CPU
and represent the four highest priority interrupts of
the iSSC
80/30.
Requests are routed to the 8085A
interrupt inputs, TRAP, RST 7.5, RST 6.5, and RST
5.5 (in decreasing order of priority) and each input
generates a unique memory address (TRAP: 24H;
RST 7.5: 3CH; RST 6.5: 34H; and RST 5.5: 2CH). An
8085A jump instruction at each of these addresses
then provides linkage to interrupt service routines
located independently anywhere in memory. All in-
terrupt inputs with the exception of the trap interrupt
may be masked via software. The trap interrupt
should be used for conditions such as power-down
sequences which require immediate attention by the
8085A
CPU.
The Intel 8259A Programmable Inter-
rupt Controller
(PIC)
provides vectoring for the next
eight
interrupt levels. As shown in Table
3,
a selec-
tion of four priority processing modes is available to
the systems designer for use
in
designing request
processing configurations to match system require-
ments. Operating mode and priority assignments
may be reconfigured dynamically via software
at
any
time during system operation. The
PIC
accepts inter-
rupt requests from the programmable parallel and
serial
I/O
interfaces, the programmable timers, the
system bus, or directly from peripheral equipment.
The
PIC
then determines which of the incoming re-
quests
is
of the highest priority, determines whether
this request
is
of
hig
her priority than the level cur-
renty
being serviced, and, if appropriate, issues
an
interrupt to the
CPU.
Any combination of interrupt
levels may be masked, via software, by storing a
single byte
in
the interrupt mask register of the
PIC.
The
PIC
generates a unique memory address for
each interrupt level. These addresses are equally
spaced at intervals of 4 or 8 (software selectable)
bytes. This 32- or 64-byte block may be located to
begin at any 32- or 64-byte boundary
in
the 65,536-
byte memory space. A single 8085A jump instruction
at each of these addresses then provides linkage to
locate each interrupt service routine independently
anywhere in memory.
Interrupt
Request
Generation-Interrupt
requests
may originate from 18 sources. Two jumper select-
able interrupt requests can be automatically gener-
ated by the programmable peripheral interface when
